Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device which comprises a first vertical field effect transistor and a second vertical field effect transistor, the first vertical field effect transistor is provided with a first drain electrode / source electrode region and a second drain electrode / source electrode region, and the second vertical field effect transistor is provided with a third drain electrode / source electrode region and a fourth drain electrode / source electrode region. The device includes a first power contact on a front side of the device and coupled to a first drain / source region, a second power contact on a front side of the device and coupled to a third drain / source region, and a contact, the contacts are on the backside of the device and coupled to the second drain / source region and the fourth drain / source region, thereby reducing area of the vertical field effect transistor device, increasing gate density, and reducing metal layer coupling.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a semiconductor device, and more particularly to a semiconductor device including a vertical field-effect transistor. Background Art

[0002] Generally, a vertical field-effect transistor (VFET) device includes a power contact and a reference contact located on the back side of the VFET device, and an input contact and an output contact located on the front side of the VFET device. In such a case, a vertical metal structure can be used to connect the back-side power contact and the back-side reference contact to the front side of the device and / or to connect the front-side input contact and the front-side output contact to the back side of the device. However, each vertical metal structure increases the area of the VFET device by one contacted poly pitch (CPP).

[0003] In addition, each of the VFET devices typically includes four to six horizontal track routing channels for spanning the device or cell. However, in some circuits, three or more of these horizontal track routing channels may be blocked by the front-side input contact and the front-side output contact using the horizontal track routing channels. Summary of the Utility Model

[0004] Embodiments of the present utility model provide a semiconductor device including a first vertical field-effect transistor having a first drain / source region and a second drain / source region, a second vertical field-effect transistor having a third drain / source region and a fourth drain / source region, a first power contact located on the front side of the device and coupled to the first drain / source region, a second power contact located on the front side of the device and coupled to the third drain / source region, and a contact located on the back side of the device and coupled to the second drain / source region and the fourth drain / source region.

[0005] Embodiments of the present utility model provide a semiconductor device including a first vertical field-effect transistor having a first drain / source region and a second drain / source region, a second vertical field-effect transistor having a third drain / source region and a fourth drain / source region, a first power contact located on the front side of the device and connected to a first front-side metal layer portion, and a back-side contact located on the back side of the device and directly connected to the second drain / source region and the fourth drain / source region. The first front-side metal layer portion is connected to a first diffusion upper metal layer portion connected to the first drain / source region.

[0006] Based on the above, the advantages of the front-side power contact, the back-side contact, the two-dimensional back-side contact, and the two-dimensional diffusion upper metal layer include reducing the area of the vertical field-effect transistor device, increasing the gate density, and reducing metal layer coupling.

[0007] To make the above features and advantages of the embodiments of the present utility model more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Description of the Drawings

[0008] Figure 1 FIG. schematically shows a VFET device including a front-side power contact and a back-side contact according to some embodiments.

[0009] Figure 2 FIG. schematically shows according to some embodiments Figure 1 a two-dimensional view of the VFET device shown above.

[0010] Figure 3 FIG. schematically shows according to some embodiments a complementary metal-oxide semiconductor (CMOS) inverter similar to the VFET device shown above Figure 1 and Figure 2 shown above.

[0011] Figure 4 FIG. schematically shows a filler structure according to some embodiments, the filler structure including a first metal layer (M0) connected to a gate material (MP) through a via over gate (VG) and a via material (MP2).

[0012] Figure 5 FIG. schematically shows a filler structure according to some embodiments, the filler structure including a first metal layer (M0) connected to a metal-over-diffusion (MD) layer connected to a gate material (MP).

[0013] Figure 6 FIG. schematically shows according to some embodiments Figure 4 and Figure 5 a two-dimensional view of the filler structure shown above.

[0014] Figure 7 FIG. schematically shows a VFET device according to some embodiments similar to the VFET device shown above Figure 1 but having several differences, the several differences including that the first metal layer (M0) extends in the X direction and the second metal layer M1 extends in the Y direction.

[0015] Figure 8is a diagram schematically showing according to some embodiments Figure 7 a two - dimensional view of the VFET device shown.

[0016] Figure 9 is a diagram schematically showing a filler structure according to some embodiments, the filler structure including a first metal layer (M0) extending in the X - direction and connected to a gate material (MP).

[0017] Figure 10 is a diagram schematically showing a filler structure according to some embodiments, the filler structure including a first metal layer (M0) extending in the X - direction and connected to a (MD) layer.

[0018] Figure 11 is a diagram schematically showing according to some embodiments Figure 9 and Figure 10 a two - dimensional view of the filler structure shown.

[0019] Figure 12 is a diagram schematically showing two - dimensional back - side contacts having L - shape, L - shape, H - shape, I - shape, Z - shape, P - shape, and F - shape according to some embodiments.

[0020] Figure 13 is a diagram schematically showing two - dimensional back - side contacts having U - shape, U - shape, T - shape, fork - shape, hammer - shape, and spoon - shape according to some embodiments.

[0021] Figure 14 is a diagram schematically showing a two - dimensional MD layer having L - shape, H - shape, I - shape, Z - shape, P - shape, and F - shape according to some embodiments.

[0022] Figure 15 is a diagram schematically showing a two - dimensional MD layer having U - shape, U - shape, 4 - shape, T - shape, and a mixed T - and - L shape according to some embodiments.

[0023] Figure 16 is a diagram schematically showing a CMOS NAND gate according to some embodiments.

[0024] Figure 17 is a diagram schematically showing a NAND gate according to some embodiments, the NAND gate having a first metal layer (M0) extending in the X - direction and a second metal layer (M1) extending in the Y - direction.

[0025] Figure 18 is a diagram schematically showing a NAND gate according to some embodiments, the NAND gate having a first metal layer (M0) extending in the Y - direction and a second metal layer (M1) extending in the X - direction.

[0026] Figure 19 A diagram schematically showing according to some embodiments Figure 17 the NAND gates shown and Figure 18 the OD regions, L-shaped back contacts, and pinned back contacts of the NAND gates shown.

[0027] Figure 20 A diagram schematically showing a four-input And-Or-Invert (AOI) gate according to some embodiments.

[0028] Figure 21 A diagram schematically showing an AOI gate according to some embodiments, the AOI gate having a first metal layer (M0) extending in the X direction and a second metal layer (M1) extending in the Y direction.

[0029] Figure 22 A diagram schematically showing an AOI gate according to some embodiments, the AOI gate having a first metal layer (M0) extending in the Y direction and a second metal layer (M1) extending in the X direction.

[0030] Figure 23 A diagram schematically showing according to some embodiments Figure 21 the AOI gates shown and Figure 22 the OD regions, Z-shaped back contacts, and pinned back contacts of the AOI gates shown.

[0031] Figure 24 A diagram schematically showing a flip-flop circuit according to some embodiments having a U-shaped back contact and two front-side power contacts.

[0032] Figure 25 A diagram schematically showing according to some embodiments Figure 24 a diagram of the U-shaped back contact, pinned back contact, back contact, deep via layer, and OD region of the flip-flop circuit shown.

[0033] Figure 26 A diagram schematically showing a flip-flop circuit according to some embodiments having two fork-shaped back contacts and a spoon-shaped back contact.

[0034] Figure 27 A diagram schematically showing according to some embodiments Figure 26 a diagram of the two fork-shaped back contacts, the spoon-shaped back contact, pinned back contact, back contact, deep via layer, and OD region of the flip-flop circuit shown.

[0035] Figure 28FIG. is a diagram schematically showing a flip-flop circuit having a front-side power contact, a pinned back-side layer, a back-side contact, and a deep via layer according to some embodiments.

[0036] Figure 29 is schematically showing according to some embodiments Figure 28 a diagram of the pinned back-side layer, the back-side contact, the deep via layer, and the OD region of the flip-flop circuit shown.

[0037] Figure 30 FIG. is a diagram schematically showing a flip-flop circuit having two fork-shaped back-side contacts and a spoon-shaped back-side contact according to some embodiments.

[0038] Figure 31 is schematically showing according to some embodiments Figure 30 a diagram of the two fork-shaped back-side contacts, the spoon-shaped back-side contact, the pinned back-side contact, the back-side contact, the deep via layer, and the OD region of the flip-flop circuit shown.

[0039] Figure 32 is schematically showing according to some embodiments Figure 30 a diagram of the MD layer of the flip-flop circuit shown.

[0040] Figure 33 FIG. is a diagram schematically showing a method of operating a device according to some embodiments.

[0041] Figure 34 FIG. is a diagram schematically showing a method of fabricating a device according to some embodiments.

[0042] Figure 35 FIG. is a block diagram of an example of a computer system configured to provide the semiconductor devices and methods of the present disclosure.

[0043] Figure 36 FIG. is a block diagram of a semiconductor device manufacturing system and an associated semiconductor device manufacturing process according to some embodiments.

[0044] Description of Reference Numerals

[0045] 20, 100: VFET device; 22: Front-side power contact; 24, 104, 160a - 160m: Two-dimensional back-side contact / Back-side contact; 26, 106: First VFET; 28, 108: Second VFET; 30, 110: Front-side voltage contact; 32, 40, 64, 70, 124, 144, 150, 506, 528, 546, 568: First metal layer (M0); 34, 42, 72, 112, 118, 152, 170a - 170k, 314, 384, 578: MD layer; 36, 44, 114, 120: Oxide diffusion (OD) wire; 38, 116: Front-side reference contact; 46, 122: Front-side input contact; 48, 126, 228, 234, 266, 270, 338, 344, 350, 356, 406, 410, 414, 418: Gate (MP); 50, 128: Gate material (MG); 52: Inverter; 54: PMOS transistor; 56: NMOS transistor; 60, 62, 140, 142: Filler structure; 66, 74, 146, 154: Gate material (MP); 68, 76, 148, 156: Deep through-hole; 102: Front-side power contact; 180, 200, 240: NAND gate; 182, 190, 236, 286, 301, 371: First PMOS transistor; 184, 192, 237, 287, 303, 373: Second PMOS transistor; 186, 194, 238, 290, 309, 379: First NMOS transistor; 188, 196, 239, 291, 311, 381: Second NMOS transistor; 202, 242: Front-side power contact / First power contact; 204, 244: Front-side power contact / Second power contact; 206, 246: First MD layer; 208, 248, 272, 310, 380, 430: First OD region; 210, 250, 326, 396: Second MD layer; 212, 252, 274, 312, 382, 432: Second OD region; 214, 254: L-shaped back-side contact / Two-dimensional back-side contact / Back-side contact; 216, 256, 276, 316, 386, 434: Third OD region; 218, 258: Third MD layer / MD layer; 220, 260, 278, 388, 436: Fourth OD region; 222, 262, 282, 302, 304, 306, 308, 372, 374, 376, 378, 510a - 510q, 532a - 532t, 572a - 572t: Pinned back-side contact; 224, 230, 334, 346, 352: Second metal layer; 226, 232, 264, 268, 336, 342, 348, 354, 404, 408, 412, 416: First metal layer280: L-shaped dorsal contact; 284, 300, 370: AND / OR Inverter (AOI) gate; 288, 305, 375: third PMOS transistor; 289, 307, 377: fourth PMOS transistor; 292, 313, 383: third NMOS transistor; 293, 315, 385: fourth NMOS transistor; 320, 390: Z-shaped dorsal contact / two-dimensional dorsal contact / dorsal contact; 322, 392, 438: fifth OD region; 324, 394, 440: sixth OD region; 328, 398, 442: seventh OD region; 330, 400: third MD layer; 332, 402, 444: eighth OD region; 446: Z-shaped dorsal contact; 448: first pinned dorsal contact; 450: second pinned dorsal contact; 452: third pinned dorsal contact; 454: fourth pinned dorsal contact; 500, 520, 540, 560: flip-flop circuit; 502: U-shaped dorsal contact; 504a, 504b, 542a to 542f: front-side power contact; 508, 530, 548, 570: second metal layer (M1); 512a to 512f, 534, 550a to 550j, 574: dorsal contact; 514a to 514c, 536a to 536d, 552a to 552c, 576a to 576d: deep via layer; 516, 538, 554, 580: OD region; 522, 524, 562, 564: fork-shaped dorsal contact; 526, 566: spoon-shaped dorsal contact; 544a to 544m: pinned dorsal layer; 590, 592, 594, 596: operation; 600: computer system / system; 602: processor; 604: non-transitory computer-readable storage medium / computer-readable storage medium; 606: instruction; 608: fabrication tool; 610: bus; 612: input / output (I / O) interface; 614: network interface; 616: network; 618: database; 620: user interface (UI); 622: semiconductor device manufacturing system / system / manufacturing system; 624: design agency; 626: mask agency; 628: semiconductor device manufacturer / fabricator / semiconductor device fabrication plant; 630: semiconductor device design layout / design layout; 632: mask data preparation / data preparation; 634: mask fabrication; 636: mask; 638: semiconductor wafer; 640: wafer fabrication; 642: semiconductor structure or semiconductor device; A1: input / first input; A2: input / second input; B1: input / third input; B2: input / fourth input; I: input pin; MP: gate material / gate; MP2: via material; V0: via; VD: diffusion up via; VG: gate up via / via; 1W: width; X, Y, Z: directions; ZN: output pin / output.; Detailed Description

[0046] The following disclosure provides numerous different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, when a first feature is formed "on" or "above" a second feature, embodiments in which the first feature and the second feature are formed in direct contact may be included, and embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact may also be included. Additionally, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure and is not used to define the relationship between various embodiments and / or configurations.

[0047] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms also encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used may be interpreted in the same manner.

[0048] The disclosed embodiments include a VFET device or a VFET cell, and the VFET device or the VFET cell includes a layout and a structure for reducing the area of the VFET device. These layouts and structures include a front-side power contact, a back-side contact or a back-side pin, a two-dimensional back-side contact, and a two-dimensional metal over diffusion (MD) layer. In some embodiments, the front-side power contact includes a partial front-side power contact. In some embodiments, the front-side power contact includes a power supply voltage contact and / or a power supply reference contact (such as ground). In some embodiments, the back-side contact is connected using an automatic place and route (APR) routine. In some embodiments, at least one of the back-side contacts is connected to the front side using a filler structure that extends between the back-side contact of the VFET device and the front-side metal layer.

[0049] In some embodiments, a VFET device includes a first VFET and a second VFET. The first VFET has a first drain / source region and a second drain / source region, and the second VFET has a third drain / source region and a fourth drain / source region. The VFET device includes a first power contact (e.g., a power voltage contact) and a second power contact (e.g., a reference contact). The first power contact is located on the front side of the device and coupled to the first drain / source region, and the second power contact is located on the front side of the device and coupled to the third drain / source region. The VFET device further includes a backside contact located on the back side of the device and coupled to the second drain / source region and the fourth drain / source region. In some embodiments, a two-dimensional backside contact and / or a two-dimensional MD layer connect multiple transistors (e.g., VFETs) together.

[0050] Advantages of the front-side power contact, the backside contact, the two-dimensional backside contact, and the two-dimensional MD layer include reducing the area of the VFET device, increasing the gate density, and reducing metal layer coupling.

[0051] Figure 1 FIG. is a diagram schematically showing a VFET device 20 including a front-side power contact 22 and a backside contact 24 according to some embodiments. In the front-side metal layer of the VFET device 20, a first metal layer (M0) extends in the Y direction, and a second metal layer (M1) extends in the X direction.

[0052] The VFET device 20 is an inverter that includes a first VFET 26 and a second VFET 28 connected through a backside contact 24 as an output pin ZN. The gates of the first VFET 26 and the second VFET 28 are connected at an input pin I. In some embodiments, the first VFET 26 is a p-channel metal-oxide semiconductor field-effect transistor (MOSFET), also referred to as a p-channel metal-oxide semiconductor (PMOS) transistor, and the second VFET 28 is an n-channel MOSFET, also referred to as an n-channel metal-oxide semiconductor (NMOS) transistor. In some embodiments, the first VFET 26 and the second VFET 28 are formed on a substrate (not shown for clarity) Figure 1 above.

[0053] The first VFET 26 includes a front-side voltage contact 30 in the second metal layer (M1). The front-side voltage contact 30 is connected to the first metal layer M0 32 through a via (V0). The first metal layer M0 32 is connected to the MD layer 34 that contacts the source region in the oxide diffusion (OD) wire 36 of the first VFET 26 through a diffusion up via (VD). The OD wire 36 defines the active region of the first VFET 26, and the active region includes the source region, drain region, and channel region of the first VFET 26. The back-side contact 24 is connected to the drain of the OD wire 36.

[0054] The second VFET 28 includes a front-side reference contact 38 in the second metal layer M1. The front-side reference contact 38 is connected to the first metal layer M0 40 through a via (V0). The first metal layer M0 40 is connected to the MD layer 42 that contacts the source in the OD wire 44 of the second VFET 28 through a diffusion up via (VD). The OD wire 44 defines the active region of the second VFET 28, and the active region includes the source region, drain region, and channel region of the second VFET 28. The back-side contact 24 is connected to the drain of the OD wire 44.

[0055] The gates of the first VFET 26 and the second VFET 28 include a front-side input contact 46 (input pin I) in the first metal layer (M0). The front-side input contact 46 (input pin I) is connected to the gate MP 48 through a via over gate (VG) and via material MP2 (shown in Figure 2 ). The gate MP 48 is connected to the gate material MG 50 that surrounds the OD wires 36 and 44. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate MP 48 includes polysilicon.

[0056] For the front-side power contact 22, a vertical metal structure is not used to connect the back-side power contact to the front side of the VFET device 20. Additionally, the back-side contact 24 is an output pin ZN that can be connected to other back-side contacts and / or other circuits. In some embodiments, a filler structure extending between the back-side contact 24 and the front-side metal layer (such as the first metal layer (M0)) is used to connect the back-side contact 24 to the front side. In some embodiments, the two-dimensional back-side contact 24 and / or the two-dimensional MD layers 34 and 42 are connected to multiple transistors, thereby connecting the multiple transistors together.

[0057] Figure 2FIG. is a two - dimensional view schematically showing a VFET device 20 according to some embodiments. The two - dimensional view of the VFET device 20 includes different layers of the VFET device 20 in a stripe.

[0058] The two - dimensional view of the VFET device 20 includes a front - side voltage contact 30 in the second metal layer (M1). The front - side voltage contact 30 is connected to a first metal layer 32, and the first metal layer 32 is connected to an MD layer 34 that contacts the source region of an OD wire 36, where the drain region of the OD wire 36 is connected to the back - side contact 24.

[0059] In addition, the two - dimensional view of the VFET device 20 includes a front - side reference contact 38 in the second metal layer (M1). The front - side reference contact 38 is connected to a first metal layer M0 40, and the first metal layer M0 40 is connected to an MD layer 42 that contacts the source region of an OD wire 44, where the drain region of the OD wire 44 is connected to the back - side contact 24.

[0060] Furthermore, the two - dimensional view of the VFET device 20 includes a front - side input contact 46 (input pin I) in the first metal layer M0. The front - side input contact 46 (input pin I) is connected to a gate MP 48, and the gate MP 48 is connected to a gate material MG 50 that surrounds the OD wires 36 and 44.

[0061] Figure 3 FIG. is a diagram schematically showing an inverter 52 similar to the VFET device 20 according to some embodiments. The inverter 52 includes a PMOS transistor 54 and an NMOS transistor 56. The VFET device 20 is similar to the inverter 52 such that the first VFET 26 is similar to the PMOS transistor 54 and the second VFET 28 is similar to the NMOS transistor 56.

[0062] One drain / source region of the PMOS transistor 54 is connected to a power - supply voltage contact (such as the front - side voltage contact 30), and the other drain / source region of the PMOS transistor 54 is connected to one drain / source region of the NMOS transistor 56 at the output ZN. The other drain / source region of the NMOS transistor 56 is connected to a reference contact (such as the front - side reference contact 38). The gates of the PMOS transistor 54 and the NMOS transistor 56 are connected at the input pin I.

[0063] Figures 4 to 6 FIG. is a diagram schematically showing filler structures 60 and 62 according to some embodiments. The filler structures 60 and 62 can be used to connect the back - side contact 24 to the first metal layer (M0). In the front - side metal layer of the VFET device 20, the first metal layer (M0) extends in the Y direction.

[0064] Figure 4 FIG. Figure 4 is a diagram schematically showing a filler structure 60 according to some embodiments. The filler structure 60 includes a first metal layer M0 64 connected to a gate material MP 66 through a via - gate (VG) and a via material (MP2). The first metal layer 64 is connected to the gate material MP 66 through a via - gate (VG) and a via material (MP2), and the gate material MP 66 is connected to a back - side contact 24 through a deep via 68. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate material MP 66 includes polysilicon.

[0065] Figure 5 FIG.

[0065] is a diagram schematically showing a filler structure 62 according to some embodiments. The filler structure 62 includes a first metal layer M0 70 connected to an MD layer 72 connected to a gate material MP 74. The first metal layer M0 70 is connected to the MD layer 72 through a via - diffusion (VD), the MD layer 72 is connected to the gate material MP 74 through a via material MP2, and the gate material MP 74 is connected to a back - side contact 24 through a deep via 76. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate material MP 74 includes polysilicon.

[0066] Figure 6 FIG. Figure 6 is a diagram schematically showing a two - dimensional view of the filler structures 60 and 62 according to some embodiments. The filler structure 60 includes a first metal layer 64, and the first metal layer 64 is connected to a gate material MP 66 through a via - gate VG and a via material MP2. The gate material MP 66 is connected to a back - side contact 24 (not shown in Figure 5 ). The filler structure 62 includes a first metal layer M0 70, and the first metal layer M0 70 is connected to an MD layer 72 through a via - diffusion (VD). The MD layer 72 is connected to a gate material MP 74 through a via material MP2, and the gate material MP 74 is connected to a back - side contact 24 (not shown in Figure 5 ). The filler structures 60 and 62 are small to reduce the area of the VFET device 20.

[0067] Figure 7 FIG. Figure 7 is a diagram schematically showing a VFET device 100 according to some embodiments that is similar to the VFET device 20 shown in Figure 1 but has several differences. The several differences include that the first metal layer (M0) extends in the X - direction and the second metal layer (M1) extends in the Y - direction. The VFET device 100 includes a front - side power contact 102 and a back - side contact 104.

[0068] The VFET device 100 is an inverter that includes a first VFET 106 and a second VFET 108 connected through a backside contact 104 that serves as an output pin ZN. The gates of the first VFET 106 and the second VFET 108 are connected at an input pin I. In some embodiments, the first VFET 106 is a PMOS transistor similar to the PMOS transistor 54 (shown in Figure 3 ), and the second VFET 108 is an NMOS transistor similar to the NMOS transistor 56 (shown in Figure 3 ).

[0069] The first VFET 106 includes a front-side voltage contact 110 in a first metal layer M0. The front-side voltage contact 110 is connected through a diffusion via VD to an MD layer 112 that contacts the source region in the OD wire 114 of the first VFET 106. The OD wire 114 defines the active region of the first VFET 106, which includes the source region, drain region, and channel region of the first VFET 106. The backside contact 104 is connected to the drain of the OD wire 114.

[0070] The second VFET 108 includes a front-side reference contact 116 in the first metal layer M0. The front-side reference contact 116 is connected through a diffusion via VD to an MD layer 118 that contacts the source in the OD wire 120 of the second VFET 108. The OD wire 120 defines the active region of the second VFET 108, which includes the source region, drain region, and channel region of the second VFET 108. The backside contact 104 is connected to the drain of the OD wire 120.

[0071] The gates of the first VFET 106 and the second VFET 108 include a front-side input contact 122 (input pin I) in a second metal layer M1. The front-side input contact 122 (input pin I) is connected through a via gate (VG) to a first metal layer M0 124. The first metal layer M0 124 is connected through a via gate (VG) and via material (MP2) to a gate MP 126. The gate MP 126 is connected to a gate material MG 128 that surrounds the OD wires 114 and 120. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate MP 126 includes polysilicon.

[0072] For the front-side power contact 102, a vertical metal structure is not used to connect the back-side power contact to the front side of the VFET device 100. Additionally, the back-side contact 104 is an output pin ZN that can be connected to other back-side contacts and / or other circuits. In some embodiments, a filler structure extending between the back-side contact 104 and the front-side metal layer (e.g., the first metal layer M0) is used to connect the back-side contact 104 to the front side. In some embodiments, the two-dimensional back-side contact 104 and / or the two-dimensional MD layers 112 and 118 are connected to multiple transistors, thereby connecting the multiple transistors together.

[0073] Figure 8 FIG. is a two-dimensional view schematically showing the VFET device 100 according to some embodiments. The two-dimensional view of the VFET device 100 includes different layers of the VFET device 100 in a strip.

[0074] The two-dimensional view of the VFET device 100 includes a front-side voltage contact 110 in the first metal layer. The front-side voltage contact 110 is connected to the MD layer 112 that contacts the source region of the OD wire 114, where the drain region of the OD wire 114 is connected to the back-side contact 104.

[0075] Furthermore, the two-dimensional view of the VFET device 100 includes a front-side reference contact 116 in the first metal layer (M0). The front-side reference contact 116 is connected to the MD layer 118 that contacts the source region of the OD wire 120, where the drain region of the OD wire 120 is connected to the back-side contact 104.

[0076] Additionally, the two-dimensional view of the VFET device 100 includes a front-side input contact 122 (input pin I) in the second metal layer (M1). The front-side input contact 122 (input pin I) is connected to the first metal layer M0 124, and the first metal layer M0 124 is connected to the gate MP 126, and the gate MP 126 is connected to the gate material MG 128 surrounding the OD wires 114 and 120.

[0077] Figures 9 to 11 FIG. is a diagram schematically showing the filler structures 140 and 142 according to some embodiments. The filler structures 140 and 142 include the first metal layer M0 extending in the X direction. The filler structures 140 and 142 can be used to connect the back-side contact 104 to the front-side first metal layer (M0).

[0078] Figure 9FIG. is a diagram schematically showing a filler structure 140 according to some embodiments. The filler structure 140 includes a first metal layer M0 144 that extends in the X direction and is connected to a gate material MP 146. The first metal layer 144 is connected to the gate material MP 146 through a via hole on the gate (VG) and a via material (MP2), and the gate material MP 146 is connected to the backside contact 104 through a deep via hole 148. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate material MP 146 includes polysilicon.

[0079] Figure 10 FIG. is a diagram schematically showing a filler structure 142 according to some embodiments. The filler structure 142 includes a first metal layer M0 150 that extends in the X direction and is connected to an MD layer 152. The first metal layer M0 150 is connected to the MD layer 152 through a diffusion via hole on the diffusion (VD), the MD layer 152 is connected to the gate material MP 154 through a via material (MP2), and the gate material MP154 is connected to the backside contact 104 through a deep via hole 156. In some embodiments, the via material (MP2) includes polysilicon, and in some embodiments, the gate material MP 154 includes polysilicon.

[0080] Figure 11 FIG. is a diagram schematically showing a two - dimensional view of the filler structures 140 and 142 according to some embodiments. The filler structure 140 includes a first metal layer 144, and the first metal layer 144 is connected to a gate material MP 146 through a via hole on the gate VG and a via material MP2. The gate material MP 146 is connected to the backside contact 104 through a deep via hole 148 (not shown in Figure 11 ). The filler structure 142 includes a first metal layer M0 150, and the first metal layer M0 150 is connected to an MD layer 152 through a diffusion via hole on the diffusion VD. The MD layer 152 is connected to the gate material MP 154 through a via material MP2. The gate material MP 154 is connected to the backside contact 104 through a deep via hole 156 (not shown in Figure 11 ). The filler structures 140 and 142 are small to reduce the area of the VFET device 100.

[0081] Figure 12 and Figure 13 FIG. is a diagram schematically showing two - dimensional backside contacts 160a to 160m with different shapes according to some embodiments. The backside contacts 160a to 160m can be used with VFET devices (such as Figure 1 the VFET device 20 shown and Figure 7 the VFET device 100 shown) and filler structures (such as Figures 4 to 6 the filler structures 60 and 62 shown and Figures 9 to 11Conductors used with the illustrated filler structures 140 and 142). The backside contacts 160a to 160m connect the drain / source regions of different OD regions together and / or to the deep vias. All the backside contacts 160a to 160m of different shapes can be combined with each other to connect different OD regions and / or deep vias. In some embodiments, the backside contacts 160a to 160m are similar to the backside contact 24 (shown in Figure 1 ), and the backside contact 104 (shown in Figure 7 ). In some embodiments, each of the OD regions has a width of 1W and is separated from the next column of OD regions by a width of 1W.

[0082] Figure 12 FIG. schematically shows two-dimensional backside contacts 160a to 160g having an L shape, an L shape, an H shape, an I shape, a Z shape, a P shape, and an F shape, respectively, according to some embodiments. The backside contacts 160a to 160g are shown connected to the OD regions and / or the deep vias, however this is merely illustrative such that any of the OD regions can be changed to a deep via, and any deep via can be changed to an OD region.

[0083] The backside contact 160a is an L-shaped backside contact connected to three OD regions, and the backside contact 160b is an L-shaped backside contact connected to two OD regions and one deep via, where the deep via can be part of one of the filler structures or part of another structure. The backside contact 160c is an H-shaped backside contact connected to four OD regions, the backside contact 160d is an I-shaped backside contact connected to four OD regions, and the backside contact 160e is a Z-shaped backside contact connected to four OD regions. The backside contact 160f is a P-shaped backside contact connected to four OD regions and one deep via, where the deep via can be part of one of the filler structures or part of another structure, and the backside contact 160g is an F-shaped backside contact connected to five OD regions.

[0084] Figure 13 FIG. schematically shows backside contacts 160h to 160m having a U shape, a U shape, a T shape, a fork shape, a hammer shape, and a spoon shape, respectively, according to some embodiments. The backside contacts 160h to 160m are shown connected to the OD regions and / or the deep vias, however this is merely illustrative such that any of the OD regions can be changed to a deep via, and any deep via can be changed to an OD region.

[0085] The dorsal contact 160h is a U-shaped dorsal contact connected to four OD regions and a deep through-hole, where the deep through-hole can be part of one of the filler structures or part of another structure, and the dorsal contact 160i is a U-shaped dorsal contact connected to three OD regions. The dorsal contact 160j is a T-shaped dorsal contact connected to two OD regions and a deep through-hole, where the deep through-hole can be part of one of the filler structures or part of another structure. The dorsal contact 160k is a fork-shaped dorsal contact connected to four OD regions and a deep through-hole using two other OD regions, where the deep through-hole can be part of one of the filler structures or part of another structure. The dorsal contact 160l is a hammer-shaped dorsal contact connected to four OD regions and a deep through-hole using two other OD regions, where the deep through-hole can be part of one of the filler structures or part of another structure, and the dorsal contact 160m is a spoon-shaped dorsal contact connected to two OD regions and a deep through-hole using five other OD regions, where the deep through-hole can be part of one of the filler structures or part of another structure.

[0086] Advantages of the two-dimensional dorsal contacts 160a to 160m include reducing the area of the VFET device, increasing the gate density, and reducing metal layer coupling.

[0087] Figure 14 and Figure 15 FIG. is a diagram schematically showing two-dimensional MD layers 170a to 170k having different shapes according to some embodiments. The MD layers 170a to 170k are conductors that can be used together with VFET devices (such as Figure 1 the VFET device 20 shown and Figure 7 the VFET device 100 shown) and filler structures (such as Figure 5 and Figure 6 the filler structure 62 shown as well as Figure 10 and Figure 11 the filler structure 142 shown). The MD layers 170a to 170k connect the VFET to other structures at the MD layer and connect the VFET and the other structures to the gate material (MP) through the via material (MP2). All the MD layers 170a to 170k with different shapes can be combined with each other to connect different MD layers to the gate material (MP). In some embodiments, the MD layers 170a to 170k are similar to the MD layers 34 and 42 (shown in Figure 1 ) and the MD layers 112 and 118 (shown in Figure 7 ). In some embodiments, each of the OD regions has a width of 1W and is separated from the next column of OD regions by a width of 1W.

[0088] Figure 14FIG. is a diagram schematically showing two-dimensional MD layers 170a to 170f having an L shape, an H shape, an I shape, a Z shape, a P shape, and an F shape, respectively, according to some embodiments. These MD layers 170a to 170f are connected to the OD region and / or the gate (MP).

[0089] MD layer 170a is an L-shaped MD layer connected to three OD regions. MD layer 170b is an H-shaped MD layer connected to four OD regions, MD layer 170c is an I-shaped MD layer connected to four OD regions, and MD layer 170d is a Z-shaped MD layer connected to four OD regions. MD layer 170e is a P-shaped MD layer connected to five OD regions, and MD layer 170f is an F-shaped MD layer connected to five OD regions.

[0090] Figure 15 FIG. is a diagram schematically showing MD layers 170g to 170k having a U shape, a U shape, a 4 shape, a T shape, and a T-and-L hybrid shape, respectively, according to some embodiments. These MD layers 170g to 170k are connected to the OD region and / or the gate MP.

[0091] MD layer 170g is a U-shaped MD layer connected to three OD regions, and MD layer 170h is a U-shaped MD layer connected to three OD regions. MD layer 170i is a 4-shaped MD layer connected to five OD regions. MD layer 170j is a T-shaped MD layer connected to two OD regions and one gate (MP) passing through the via material (MP2) using two other OD regions. MD layer 170k is a T-and-L hybrid-shaped MD layer connected to three OD regions and one gate (MP) passing through the via material (MP2) using three other OD regions.

[0092] Advantages of the two-dimensional MD layers 170a to 170k include connecting signals at the MD layer instead of at the metal layer, which improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0093] Figure 16FIG. is a diagram schematically showing a complementary metal-oxide semiconductor (CMOS) NAND gate 180 according to some embodiments. The NAND gate 180 includes a first PMOS transistor 182, a second PMOS transistor 184, a first NMOS transistor 186, and a second NMOS transistor 188. One drain / source region of the first PMOS transistor 182 is connected to a power supply voltage contact, and one drain / source region of the second PMOS transistor 184 is connected to the power supply voltage contact. At the output ZN, the other drain / source region of the first PMOS transistor 182 and the other drain / source region of the second PMOS transistor 184 are connected to each other and connected to one drain / source region of the first NMOS transistor 186. The other drain / source region of the first NMOS transistor 186 is connected to one drain / source region of the second NMOS transistor 188, and the other drain / source region of the second NMOS transistor 188 is connected to a reference contact (e.g., ground).

[0094] The gate of the first PMOS transistor 182 and the gate of the first NMOS transistor 186 are connected to the input A1, and the gate of the second PMOS transistor 184 and the gate of the second NMOS transistor 188 are connected to the input A2.

[0095] In operation, the NAND gate 180 performs a NAND gate function on the inputs A1 and A2 and provides an output signal at the output ZN.

[0096] Figure 17 FIG. is a diagram schematically showing a NAND gate 200 according to some embodiments. The NAND gate 200 has a first metal layer (M0) extending in the X direction and a second metal layer (M1) extending in the Y direction. As an example of this type of wiring, in Figure 7 the VFET device 100 shown, the first metal layer (M0) extends in the X direction and the second metal layer (M1) extends in the Y direction.

[0097] The NAND gate 200 includes a first PMOS transistor 190 similar to the first PMOS transistor 182 (shown in Figure 16 FIG.) and a second PMOS transistor 184 similar to the second PMOS transistor 184 (shown in Figure 16a similar second PMOS transistor 192. The NAND gate 200 includes front-side power contacts 202 and 204 each connected to a power supply voltage. The first power contact 202 is connected to a first MD layer 206 connected to the drain / source region of the first OD region 208, and the second power contact 204 is connected to a second MD layer 210 connected to the drain / source region of the second OD region 212. The other drain / source regions of each of the first OD region 208 and the second OD region 212 are connected to an L-shaped back-side contact 214 that serves as the output ZN of the NAND gate 200.

[0098] The L-shaped back-side contact 214 is further connected to a first NMOS transistor 194 similar to the first NMOS transistor 186 (shown in Figure 16 ). The L-shaped back-side contact 214 is connected to the drain / source region of a third OD region 216, and the third OD region 216 has another drain / source region connected to a third MD layer 218, and the third MD layer 218 is connected to a second NMOS transistor 196 similar to the second NMOS transistor 188 (shown in Figure 16 ). The third MD layer 218 is connected to the drain / source region of a fourth OD region 220, and the fourth OD region 220 has another drain / source region connected to a pinned backside contact 222 that serves as a reference (e.g., ground).

[0099] The NAND gate 200 has two inputs A1 and A2. The first input A1 includes a second metal layer 224 connected to a first metal layer 226 through a via V0, and the first metal layer 226 is connected to a gate MP 228 through a via VG and via material MP2. The second input A2 includes a second metal layer 230 connected to a first metal layer 232 through a via V0, and the first metal layer 232 is connected to a gate MP 234 through a via VG and via material MP2.

[0100] The NAND gate 200 includes the L-shaped back-side contact 214 and the MD layer 218 for connecting different OD regions without using the front-side metal layer. Thus, the advantages of the two-dimensional back-side contact 214 and the MD layer 218 include connecting signals at the back-side contact 214 and the MD layer 218 rather than at the front-side metal layer, which improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0101] Figure 18 is a diagram schematically showing a NAND gate 240 according to some embodiments, the NAND gate 240 having a first metal layer (M0) extending in the Y direction and a second metal layer (M1) extending in the X direction. As an example of this type of wiring, inFigure 1 In the VFET device 20 shown, the first metal layer (M0) extends in the Y direction and the second metal layer (M1) extends in the X direction.

[0102] The NAND gate 240 includes a first PMOS transistor 236 similar to the first PMOS transistor 182 (shown in Figure 16 ) and a second PMOS transistor 237 similar to the second PMOS transistor 184 (shown in Figure 16 ). The NAND gate 200 includes front-side power contacts 242 and 244 each connected to a power supply voltage. The first power contact 242 is connected to a first MD layer 246 connected to the drain / source region of the first OD region 248, and the second power contact 244 is connected to a second MD layer 250 connected to the drain / source region of the second OD region 252. The other drain / source regions of each of the first OD region 248 and the second OD region 252 are connected to an L-shaped back-side contact 254 that serves as the output ZN of the NAND gate 240.

[0103] The L-shaped back-side contact 254 is further connected to a first NMOS transistor 238 similar to the first NMOS transistor 186 (shown in Figure 16 ). The L-shaped back-side contact 254 is further connected to the drain / source region of a third OD region 256, and the third OD region 256 has another drain / source region connected to a third MD layer 258, and the third MD layer 258 is connected to a second NMOS transistor 239 similar to the second NMOS transistor 188 (shown in Figure 16 ). The third MD layer 258 is connected to the drain / source region of a fourth OD region 260, and the fourth OD region 260 has another drain / source region connected to a pinned back-side contact 262 that serves as a reference (e.g., ground).

[0104] The NAND gate 240 has two inputs A1 and A2. The first input A1 includes a first metal layer 264 connected to a gate MP 266 through a via VG and a via material MP2. The second input A2 includes a first metal layer 268 connected to a gate MP 270 through a via VG and a via material MP2.

[0105] The NAND gate 240 includes an L-shaped back-side contact 254 and an MD layer 258 for connecting different OD regions without using the front-side metal layer. Thus, the advantages of the two-dimensional back-side contact 254 and the MD layer 258 include connecting signals at the back-side contact 254 and the MD layer 258 rather than at the front-side metal layer, which improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0106] Figure 19Schematically shows according to some embodiments Figure 17 The OD regions, L-shaped back contacts, and pinned back contacts of the NAND gate 200 shown and Figure 18 The NAND gate 240 shown. The first OD region 272 is similar to each of the first OD regions 208 and 248, the second OD region 274 is similar to each of the second OD regions 212 and 252, the third OD region 276 is similar to each of the third OD regions 216 and 256, and the fourth OD region 278 is similar to each of the fourth OD regions 220 and 260. The L-shaped back contact 280 is similar to each of the L-shaped back contacts 214 and 254, and the pinned back contact 282 is similar to each of the pinned back contacts 222 and 262.

[0107] Figure 20 Schematically shows a four input And-Or-Invert (AOI) gate 284 according to some embodiments. The AOI gate 284 includes a first PMOS transistor 286, a second PMOS transistor 287, a third PMOS transistor 288, and a fourth PMOS transistor 289. The AOI gate 284 further includes a first NMOS transistor 290, a second NMOS transistor 291, a third NMOS transistor 292, and a fourth NMOS transistor 293.

[0108] One drain / source region of the first PMOS transistor 286 is connected to a power supply voltage contact, and one drain / source region of the second PMOS transistor 287 is connected to the power supply voltage contact. The other drain / source region of the first PMOS transistor 286 and the other drain / source region of the second PMOS transistor 287 are connected to each other and connected to one drain / source region of the third PMOS transistor 288 and one drain / source region of the fourth PMOS transistor 289. At the output ZN, the other drain / source region of the third PMOS transistor 288 and the other drain / source region of the fourth PMOS transistor 289 are connected to each other and connected to one drain / source region of the first NMOS transistor 290 and one drain / source region of the second NMOS transistor 291. The other drain / source region of the first NMOS transistor 290 is connected to one drain / source region of the third NMOS transistor 292, and the other drain / source region of the second NMOS transistor 291 is connected to one drain / source region of the fourth NMOS transistor 293. The other drain / source regions of the third NMOS transistor 292 and the fourth NMOS transistor 293 are connected to a reference (e.g., ground).

[0109] The gates of the first PMOS transistor 286 and the first NMOS transistor 290 are connected to input B1, the gates of the second PMOS transistor 287 and the third NMOS transistor 292 are connected to input B2, the gates of the third PMOS transistor 288 and the second NMOS transistor 291 are connected to input A1, and the gates of the fourth PMOS transistor 289 and the fourth NMOS transistor 293 are connected to input A2.

[0110] In operation, the AOI gate 284 performs an And-Or-Invert function on inputs A1, A2, B1, and B2 and provides an output signal at output ZN.

[0111] Figure 21 FIG. schematically shows an And-Or-Invert (AOI) gate 300 according to some embodiments. The And-Or-Invert (AOI) gate 300 has a first metal layer (M0) extending in the X direction and a second metal layer (M1) extending in the Y direction. As an example of this type of wiring, in Figure 7 the VFET device 100 shown and in Figure 17 the NAND gate 200 shown, the first metal layer (M0) extends in the X direction and the second metal layer (M1) extends in the Y direction.

[0112] The AOI gate 300 includes a first PMOS transistor 301 similar to the first PMOS transistor 286 (shown in Figure 20 ), a second PMOS transistor 303 similar to the second PMOS transistor 287 (shown in Figure 20 ), a third PMOS transistor 305 similar to the third PMOS transistor 288 (shown in Figure 20 ), and a fourth PMOS transistor 307 similar to the fourth PMOS transistor 289 (shown in Figure 20 ). The AOI gate 300 further includes a first NMOS transistor 309 similar to the first NMOS transistor 290 (shown in Figure 20 ), a second NMOS transistor 311 similar to the second NMOS transistor 291 (shown in Figure 20 ), a third NMOS transistor 313 similar to the third NMOS transistor 292 (shown in Figure 20 ), and a fourth NMOS transistor 315 similar to the fourth NMOS transistor 293 (shown in Figure 20 ).

[0113] The AOI gate 300 includes pinned backside contacts 302, 304, 306, and 308. The pinned backside contacts 302 and 304 are connected to one or more power supply voltage contacts. The pinned backside contact 302 is connected to the drain / source region of the first OD region 310, and the pinned backside contact 304 is connected to the drain / source region of the second OD region 312. The other drain / source region of each of the first OD region 310 and the second OD region 312 is connected to the MD layer 314, which connects the aforementioned drain / source regions to each other and to the third PMOS transistor 305 and the fourth PMOS transistor 307. The MD layer 314 is connected to the drain / source region of each of the third OD region 316 and the fourth OD region 318. The other drain / source region of each of the third OD region 316 and the fourth OD region 318 is connected to the Z-shaped backside contact 320, which is the output ZN of the AOI gate 300.

[0114] The Z-shaped backside contact 320 is further connected to the first NMOS transistor 309 and the second NMOS transistor 311. The Z-shaped backside contact 320 is connected to the drain / source region of each of the fifth OD region 322 and the sixth OD region 324. The other drain / source region of the fifth OD region 322 is connected to the second MD layer 326, which is connected to the fourth NMOS transistor 315 at the drain / source region of the seventh OD region 328, and the other drain / source region of the seventh OD region 328 is connected to the pinned backside contact 306, which is a reference contact. The other drain / source region of the sixth OD region 324 is connected to the third MD layer 330, which is connected to the third NMOS transistor 313 at the drain / source region of the eighth OD region 332, and the other drain / source region of the eighth OD region 332 is connected to the pinned backside contact 308, which is a reference contact.

[0115] The AOI gate 300 has four inputs A1, A2, B1, and B2. The first input A1 is connected to the third PMOS transistor 305 and the second NMOS transistor 311, and includes a second metal layer 334 connected to the first metal layer 336 through a via V0, and the first metal layer 336 is connected to the gate MP 338 through a via (VG) and via material MP2. The second input A2 is connected to the fourth PMOS transistor 307 and the fourth NMOS transistor 315, and includes a second metal layer 340 connected to the first metal layer 342 through a via V0, and the first metal layer 342 is connected to the gate MP 344 through a via VG and via material MP2. The third input B1 is connected to the first PMOS transistor 301 and the first NMOS transistor 309, and includes a second metal layer 346 connected to the first metal layer 348 through a via V0, and the first metal layer 348 is connected to the gate MP 350 through a via VG and via material MP2, and the fourth input B2 is connected to the second PMOS transistor 303 and the third NMOS transistor 313, and includes a second metal layer 352 connected to the first metal layer 354 through a via V0, and the first metal layer 354 is connected to the gate MP 356 through a via VG and via material MP2.

[0116] The AOI gate 300 includes a Z-shaped backside contact 320 and an MD layer for connecting different OD regions without using the front-side metal layer. Thus, the advantages of the two-dimensional backside contact 320 and the MD layer include connecting signals at the backside contact 320 and the MD layer rather than at the front-side metal layer, which improves routing flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0117] Figure 22 FIG. is a diagram schematically showing an AOI gate 370 according to some embodiments. The AOI gate 370 has a first metal layer M0 extending in the Y direction and a second metal layer M1 extending in the X direction. As an example of this type of routing, in Figure 1 the VFET device 20 shown and Figure 18 the NAND gate 240 shown, the first metal layer M0 extends in the Y direction and the second metal layer M1 extends in the X direction.

[0118] The AOI gate 370 includes a first PMOS transistor 371 similar to the first PMOS transistor 286 (shown in Figure 20 ), a second PMOS transistor 373 similar to the second PMOS transistor 287 (shown in Figure 20 ), a third PMOS transistor 375 similar to the third PMOS transistor 288 (shown in Figure 20a third PMOS transistor 375 similar to that (shown in Figure 20 ), and a fourth PMOS transistor 377 similar to the fourth PMOS transistor 289 (shown in Figure 20 ). The AOI gate 370 further includes a first NMOS transistor 379 similar to the first NMOS transistor 290 (shown in Figure 20 ), a second NMOS transistor 381 similar to the second NMOS transistor 291 (shown in Figure 20 ), a third NMOS transistor 383 similar to the third NMOS transistor 292 (shown in Figure 20 ), and a fourth NMOS transistor 385 similar to the fourth NMOS transistor 293 (shown in

[0119] The AOI gate 370 includes pinned backside contacts 372, 374, 376, and 378. The pinned backside contacts 372 and 374 are connected to one or more power supply voltage contacts. The pinned backside contact 372 is connected to the drain / source region of the first OD region 380, and the pinned backside contact 374 is connected to the drain / source region of the second OD region 382. The other drain / source region of each of the first OD region 380 and the second OD region 382 is connected to the MD layer 384, and the MD layer 384 connects the foregoing drain / source regions to each other and to the third PMOS transistor 375 and the fourth PMOS transistor 377. The MD layer 314 is connected to the drain / source region of each of the third OD region 386 and the fourth OD region 388. The other drain / source region of each of the third OD region 386 and the fourth OD region 388 is connected to a Z-shaped backside contact 390 that serves as the output ZN of the AOI gate 370.

[0120] The Z-shaped backside contact 390 is further connected to the first NMOS transistor 379 and the second NMOS transistor 381. The Z-shaped backside contact 390 is connected to the drain / source region of each of the fifth OD region 392 and the sixth OD region 394. The other drain / source region of the fifth OD region 392 is connected to the second MD layer 396, and the second MD layer 396 is connected to the fourth NMOS transistor 385 at the drain / source region of the seventh OD region 398, and the other drain / source region of the seventh OD region 398 is connected to the pinned backside contact 376 that serves as a reference contact. The other drain / source region of the sixth OD region 394 is connected to the third MD layer 400, and the third MD layer 400 is connected to the third NMOS transistor 383 at the drain / source region of the eighth OD region 402, and the other drain / source region of the eighth OD region 402 is connected to the pinned backside contact 378 that serves as a reference contact.

[0121] The AOI gate 370 has four inputs A1, A2, B1, and B2. The first input A1 is connected to the third PMOS transistor 375 and the second NMOS transistor 381, and includes a first metal layer 404 that is connected to the gate MP 406 through a via VG and via material MP2. The second input A2 is connected to the fourth PMOS transistor 377 and the fourth NMOS transistor 385, and includes a first metal layer 408 that is connected to the gate MP 410 through a via VG and via material MP2. The third input B1 is connected to the first PMOS transistor 371 and the first NMOS transistor 379, and includes a first metal layer 412 that is connected to the gate MP 414 through a via VG and via material MP2, and the fourth input B2 is connected to the second PMOS transistor 373 and the third NMOS transistor 383, and includes a first metal layer 416 that is connected to the gate MP 418 through a via VG and via material MP2.

[0122] The AOI gate 370 includes a Z-shaped backside contact 390 and an MD layer for connecting different OD regions without using the front-side metal layer. Thus, the advantages of the two-dimensional backside contact 390 and the MD layer include connecting signals at the backside contact 390 and the MD layer rather than at the front-side metal layer, which improves routing flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0123] Figure 23 is schematically shown according to some embodiments Figure 21 the AOI gate 300 shown and Figure 22 a diagram of the OD regions, Z-shaped backside contacts, and pinned backside contacts of the AOI gate 370 shown. The first OD region 430 is similar to each of the first OD regions 310 and 380, the second OD region 432 is similar to each of the second OD regions 312 and 382, the third OD region 434 is similar to each of the third OD regions 316 and 386, and the fourth OD region 436 is similar to each of the fourth OD regions 318 and 388. In addition, the fifth OD region 438 is similar to each of the fifth OD regions 322 and 392, the sixth OD region 440 is similar to each of the sixth OD regions 324 and 394, the seventh OD region 442 is similar to each of the seventh OD regions 328 and 398, and the eighth OD region 444 is similar to each of the eighth OD regions 332 and 402.

[0124] The Z-shaped back contact 446 is similar to each of the Z-shaped back contacts 320 and 390, and the first pinned back contact 448 is similar to each of the pinned back contacts 302 and 372, the second pinned back contact 450 is similar to each of the pinned back contacts 304 and 374, the third pinned back contact 452 is similar to each of the pinned back contacts 306 and 376, and the fourth pinned back contact 454 is similar to each of the pinned back contacts 308 and 378.

[0125] Figure 24 FIG. schematically shows a flip-flop circuit 500 according to some embodiments. The flip-flop circuit 500 has a U-shaped back contact 502 and two front-side power contacts 504a and 504b. The flip-flop circuit 500 has an area of 22CPP. The first metal layer M0 506 extends in the Y direction and the second metal layer M1 508 extends in the X direction. The flip-flop circuit 500 includes pinned back contacts 510a to 510q, back contacts 512a to 512f, and deep via layers 514a to 514c.

[0126] Figure 25 FIG. schematically shows the U-shaped back contact 502, the pinned back contacts 510a to 510q, the back contacts 512a to 512f, the deep via layers 514a to 514c, and the OD region 516 according to some embodiments.

[0127] Advantages of the U-shaped back contact 502, the front-side power contacts 504a and 504b, the back contacts 512a to 512f, and the deep via layers 514a to 514c include connecting signals at these contacts and layers rather than at the front-side metal layer. This improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0128] Figure 26 FIG. schematically shows a flip-flop circuit 520 according to some embodiments. The flip-flop circuit 520 has two fork-shaped back contacts 522 and 524 and a spoon-shaped back contact 526. The flip-flop circuit 520 has an area of 19CPP. The first metal layer M0 528 extends in the Y direction and the second metal layer M1 530 extends in the X direction. Thus, the flip-flop circuit 520 having the two fork-shaped back contacts 522 and 524 and the spoon-shaped back contact 526 is smaller than Figure 24 and Figure 25 the flip-flop circuit 500 shown. The flip-flop circuit 520 further includes pinned back contacts 532a to 532t, a back contact 534, and deep via layers 536a to 536d. In some embodiments, at least one of the fork-shaped back contacts 522 and 524 is changed to a hammer-shaped back contact.

[0129] Figure 27 A diagram schematically showing the two fork-shaped dorsal contacts 522 and 524, the spoon-shaped dorsal contact 526, the pinned dorsal contacts 532a to 532t, the dorsal contact 534, the deep via layers 536a to 536d, and the OD region 538 according to some embodiments.

[0130] Advantages of the two fork-shaped dorsal contacts 522 and 524, the spoon-shaped dorsal contact 526, the pinned dorsal contacts 532a to 532t, the dorsal contact 534, and the deep via layers 536a to 536d include connecting signals at these contacts and layers rather than at the front-side metal layer. This improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0131] Figure 28 A diagram schematically showing a flip-flop circuit 540 according to some embodiments. The flip-flop circuit 540 has front-side power contacts 542a to 542f, pinned dorsal layers 544a to 544m, dorsal contacts 550a to 550j, and deep via layers 552a to 552c. The flip-flop circuit 540 has an area of 22CPP, with the first metal layer M0 546 extending in the X direction and the second metal layer M1 548 extending in the Y direction.

[0132] Figure 29 A diagram schematically showing the pinned dorsal layers 544a to 544m, the dorsal contacts 550a to 550j, the deep via layers 552a to 552c, and the OD region 554 according to some embodiments.

[0133] Advantages of the front-side power contacts 542a to 542f, the pinned dorsal layers 544a to 544m, the dorsal contacts 550a to 550j, and the deep via layers 552a to 552c include connecting signals at these contacts and layers rather than at the front-side metal layer. This improves wiring flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal layer coupling.

[0134] Figure 30 A diagram schematically showing a flip-flop circuit 560 according to some embodiments. The flip-flop circuit 560 has two fork-shaped dorsal contacts 562 and 564 and a spoon-shaped dorsal contact 566. The flip-flop circuit 560 has an area of 17CPP, with the first metal layer M0 568 extending in the X direction and the second metal layer M1 570 extending in the Y direction. Thus, the flip-flop circuit 560 having the two fork-shaped dorsal contacts 562 and 564 and the spoon-shaped dorsal contact 566 is compared with Figure 28 and Figure 29The flip - flop circuit 540 shown is small. The flip - flop circuit 560 further includes pinned back - side contacts 572a to 572t, a back - side contact 574, deep - via layers 576a to 576d, and an MD layer 578. In some embodiments, at least one of the forked back - side contacts 562 and 564 is changed to a hammer - shaped back - side contact.

[0135] Figure 31 FIG. schematically shows the two forked back - side contacts 562 and 564, the spoon - shaped back - side contact 566, the pinned back - side contacts 572a to 572t, the back - side contact 574, the deep - via layers 576a to 576d, and the OD region 580 according to some embodiments.

[0136] The advantages of the two forked back - side contacts 562 and 564, the spoon - shaped back - side contact 566, the pinned back - side contacts 572a to 572t, the back - side contact 574, and the deep - via layers 576a to 576d include connecting signals at these contacts and layers rather than at the front - side metal layer, which improves routing flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal - layer coupling.

[0137] Figure 32 FIG. schematically shows the MD layer 578 according to some embodiments. The advantages of the various shapes and connections of the MD layer 578 include connecting signals at these layers rather than at the front - side metal layer. This improves routing flexibility, reduces the area of the VFET device, increases the gate density, and reduces metal - layer coupling.

[0138] Figure 33 FIG. schematically shows a method of operating a device. The device can be any of the devices described herein. In some embodiments, the device is similar to Figure 1 the VFET device 20 shown. In some embodiments, the device is similar to Figure 7 the VFET device 100 shown.

[0139] At operation 590, the method includes applying power to a first power contact located on the front - side of the device and connected to the first drain / source region of a first VFET. In some embodiments, the first VFET is similar to the first VFET 26, and the first power contact is similar to the front - side voltage contact 30. In some embodiments, the first VFET is similar to the first VFET 106, and the first power contact is similar to the front - side voltage contact 110. In some embodiments, applying power to the first power contact includes applying power to a first metal layer and a diffused upper - metal layer connected to the first drain / source region of the first VFET.

[0140] At operation 592, the method includes applying a reference voltage to a second power contact connected to a second drain / source region of a second VFET located on a front side of the device. In some embodiments, the second VFET is similar to the second VFET 28, and the second power contact is similar to the front side reference contact 38. In some embodiments, the second VFET is similar to the second VFET 108, and the second power contact is similar to the front side reference contact 116. In some embodiments, applying the reference voltage includes applying the reference voltage via a first metal layer and a diffusion upper metal layer connected to the second drain / source region of the second vertical field effect transistor.

[0141] At operation 594, the method includes applying an input signal to a gate contact located on a front side of the device and connected to a polysilicon layer that is connected to a first gate of a first VFET and a second gate of a second VFET. In some embodiments, the gate contact is similar to the front side input contact 46 (input pin I). In some embodiments, the gate contact is similar to the front side input contact 122 (input pin I).

[0142] At operation 596, the method includes receiving an output signal at a back side contact connected to a third drain / source region of the first VFET and a fourth drain / source region of the second VFET located on a back side of the device. In some embodiments, the back side contact is similar to the back side contact 24. In some embodiments, the back side contact is similar to the back side contact 104. In some embodiments, receiving the output signal includes receiving the output signal at a front side of the device via a filler configured to electrically connect the back side contact located on the back side of the device to the front side of the device.

[0143] Figure 34 is a diagram schematically showing a method of fabricating a device according to some embodiments. The device can be any of the devices set forth herein. In some embodiments, the device is similar to Figure 1 the VFET device 20 shown. In some embodiments, the device is similar to Figure 7 the VFET device 100 shown.

[0144] At operation 660, the method includes forming a first VFET over a substrate, the first VFET having a first drain / source region and a second drain / source region, and at operation 662, the method includes forming a second VFET over the substrate, the second VFET having a third drain / source region and a fourth drain / source region.

[0145] At operation 664, the method includes forming a first power contact coupled to a first drain / source region on a front side of the device, and at operation 666, the method includes forming a second power contact coupled to a third drain / source region on the front side of the device. In some embodiments, forming the first power contact includes forming a first diffusion over metal layer electrically connected to the first drain / source region over the first drain / source region and forming a first metal layer portion electrically connected to the first diffusion over metal layer over the first diffusion over metal layer. In some embodiments, forming the second power contact includes forming a second diffusion over metal layer electrically connected to the third drain / source region over the third drain / source region and forming another first metal layer portion electrically connected to the second diffusion over metal layer over the second diffusion over metal layer.

[0146] At operation 668, the method includes forming a contact coupled to a second drain / source region and a fourth drain / source region on a back side of the device. In some embodiments, forming the contact includes forming the contact to be directly connected to the second drain / source region and the fourth drain / source region.

[0147] In some embodiments, the method includes forming a via fill portion that electrically connects the contact to the front side of the device, wherein forming the via fill portion includes forming a deep via and forming a polysilicon layer, the deep via being configured to electrically connect to the contact and the polysilicon layer being electrically connected to a front side metal layer.

[0148] Figure 35 is a block diagram schematically illustrating an example of a computer system 600 according to some embodiments, the computer system 600 being configured to provide the semiconductor devices and methods of the present disclosure. Some or all of the design, layout, and fabrication of a semiconductor device (also referred to as a semiconductor circuit) may be implemented by or utilize the computer system 600. In some embodiments, the computer system 600 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an integrated circuit (IC).

[0149] In some embodiments, system 600 is a general-purpose computing device including a processor 602 and a non-transitory computer-readable storage medium 604. The computer-readable storage medium 604 may be encoded with (i.e., store) computer code, such as executable instructions 606. Execution of the instructions 606 by the processor 602 provides (at least in part) design tools that implement some or all of the functions of system 600, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final layout for manufacturing. Additionally, fabrication tools 608 are included to further perform layout and physical implementation of the design and fabrication of semiconductor devices. In some embodiments, execution of the instructions 606 by the processor 602 provides design tools that implement some or all of the functions of system 600. In some embodiments, system 600 includes a commercial router. In some embodiments, system 600 includes an automatic placement and routing (APR) system.

[0150] The processor 602 is electrically coupled to the computer-readable storage medium 604 via a bus 610 and is electrically coupled to an input / output (I / O) interface 612 via the bus 610. A network interface 614 is also electrically connected to the processor 602 via the bus 610. The network interface 614 is connected to a network 616 such that the processor 602 and the computer-readable storage medium 604 can be connected to external components using the network 616. The processor 602 is configured to execute computer code or instructions 606 encoded in the computer-readable storage medium 604 to cause the system 600 to perform some or all of the functions of system 600, such as providing the semiconductor devices and methods of the present disclosure and other functions of system 600. In some embodiments, the processor 602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0151] In some embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device. For example, the computer-readable storage medium 604 can include semiconductor or solid state memory, magnetic tape, removable computer diskettes, random-access memory (RAM), read-only memory (ROM), rigid magnetic disks, and / or optical disks. In some embodiments that use optical disks, the computer-readable storage medium 604 can include compact disk read only memory (CD-ROM), compact disk read / write memory (CD-R / W), and / or digital video disc (DVD).

[0152] In some embodiments, the computer-readable storage medium 604 stores computer program code or instructions 606 that are configured to cause the system 600 to perform some or all of the functions of the system 600. In some embodiments, the computer-readable storage medium 604 also stores information that facilitates the performance of some or all of the functions of the system 600. In some embodiments, the computer-readable storage medium 604 stores a database 618 that includes a library of components, a library of digital circuit cells, and / or one or more of the databases.

[0153] The system 600 includes an I / O interface 612 that is coupled to an external circuitry. In some embodiments, the I / O interface 612 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 602.

[0154] The network interface 614 is coupled to the processor 602 and enables the system 600 to communicate with a network 616 to which one or more other computer systems are connected. The network interface 614 may include: a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), worldwide interoperability of microwave access (WIMAX), general packet radio service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as ETHERNET, universal serial bus (USB), or Institute of Electrical and Electronic Engineers (IEEE)-1394. In some embodiments, some or all of the functions of the system 600 may be implemented in two or more systems similar to the system 600.

[0155] The system 600 is configured to receive information via the I / O interface 612. The information received via the I / O interface 612 includes one or more of instructions, data, design rules, component and cell libraries, and / or other parameters for processing by the processor 602. The information is transmitted to the processor 602 via the bus 610. In addition, the system 600 is configured to receive information related to a user interface (UI) via the I / O interface 612. This UI information may be stored as the UI 620 in the computer-readable storage medium 604.

[0156] In some embodiments, some or all of the functions of the system 600 are implemented by independent software applications for execution by the processor. In some embodiments, some or all of the functions of the system 600 are implemented in software applications that are part of an additional software application. In some embodiments, some or all of the functions of the system 600 are implemented as a plug-in of a software application. In some embodiments, at least one of the functions of the system 600 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of the system 600 are implemented by software applications used by the system 600. In some embodiments, a layout is generated using tools such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0157] In some embodiments, the wiring, placement, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units such as one or more optical discs such as digital video discs (DVDs); magnetic disks such as hard disks; semiconductor memories such as ROM and RAM; and memory cards and the like.

[0158] As described above, embodiments of system 600 include fabrication tools 608 for implementing the manufacturing process of system 600. For example, based on the final placement, a photolithographic mask for fabricating a semiconductor device can be generated by fabrication tool 608.

[0159] Combined with Figure 36 disclosing other aspects of device fabrication, Figure 36 is a block diagram of a semiconductor device manufacturing system 622 and an associated semiconductor device manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, manufacturing system 622 is used to fabricate one or more semiconductor masks and / or at least one component in a layer of a semiconductor device.

[0160] In Figure 36In this case, the semiconductor device manufacturing system 622 includes entities such as a design house 624, a mask house 626, and a semiconductor device manufacturer / fabricator (a "Fab") 628, which interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of semiconductor devices such as those described herein. The entities in system 622 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and / or receives services from one or more of the other entities. In some embodiments, two or more of the design house 624, the mask house 626, and the semiconductor device fabricator 628 are owned by a single larger company. In some embodiments, two or more of the design house 624, the mask house 626, and the semiconductor device fabricator 628 coexist in a shared facility and use shared resources.

[0161] The design organization (or design team) 624 generates a semiconductor device design layout 630. The semiconductor device design layout 630 includes various geometric patterns designed for the semiconductor device or the semiconductor device layout. The geometric patterns correspond to the patterns of metal layers, oxide layers, or semiconductor layers of various components that make up the semiconductor structure to be fabricated. The various layers are combined to form various semiconductor device features. For example, a part of the semiconductor device design layout 630 includes various semiconductor device features to be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or active areas, gate electrodes, sources, drains, metal lines, local vias, and openings for bond pads. The design organization 624 implements a design process to form the semiconductor device design layout 630. The semiconductor device design layout 630 exists in one or more data files having information of the geometric patterns. For example, the semiconductor device design layout 630 can be expressed in the Graphic Design System II (GDSII) file format or the Design Framework II (DFII) file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, supply voltage rail design, reference voltage rail design, placement and routing routines, and physical layout design.

[0162] The mask organization 626 includes data preparation 632 and mask fabrication 634. The mask organization 626 uses the semiconductor device design layout 630 to fabricate one or more masks 636 for the various layers to be used in fabricating the semiconductor device or the semiconductor structure. The mask organization 626 performs mask data preparation 632, in which the semiconductor device design layout 630 is translated into a representative data file (RDF). The mask data preparation 632 provides the RDF to the mask fabrication 634. The mask fabrication 634 includes a mask writer that converts the RDF into an image on a substrate (such as a mask (reticle) 636 or a semiconductor wafer 638). The design layout 630 is adjusted through the mask data preparation 632 to comply with the characteristics of the mask writer and / or the standards of the semiconductor device fabrication factory 628. In Figure 36In [the figure], mask data preparation 632 and mask fabrication 634 are shown as separate components. In some embodiments, mask data preparation 632 and mask fabrication 634 may be collectively referred to as mask data preparation.

[0163] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts the semiconductor device design layout 630. In some embodiments, mask data preparation 632 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as an inverse imaging problem, is also used.

[0164] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC), which checks the semiconductor device design layout 630 that has gone through each process in OPC against a set of mask creation rules containing certain geometric and / or connectivity constraints to ensure there is sufficient margin to account for variability in the semiconductor manufacturing process and achieve similar effects. In some embodiments, the MRC modifies the semiconductor device design layout 630 to compensate for limitations during mask fabrication 634, which may undo a portion of the modifications implemented by OPC to meet the mask creation rules.

[0165] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), which simulates the processes to be implemented by semiconductor device fabricator 628. LPC simulates this process based on semiconductor device design layout 630 to create a simulated fabricated device. The process parameters in the LPC simulation may include parameters associated with various processes of the semiconductor device manufacturing cycle, parameters associated with the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors or combinations thereof. In some embodiments, after a simulated fabricated device has been created through LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine semiconductor device design layout 630.

[0166] For clarity, the above description of mask data preparation 632 has been simplified. In some embodiments, data preparation 632 includes additional features, such as logic operation (LOP), to modify semiconductor device design layout 630 according to manufacturing rules. Additionally, the processes applied to semiconductor device design layout 630 during data preparation 632 can be performed in various different orders.

[0167] After mask data preparation 632 and during mask fabrication 634, a mask 636 or a set of masks 636 is fabricated based on the modified semiconductor device design layout 630. In some embodiments, mask fabrication 634 includes performing one or more lithographic exposures based on the semiconductor device design layout 630. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanism is used to pattern the mask (photomask or reticle) 636 based on the modified semiconductor device design layout 630. The mask 636 can be formed using various techniques. In some embodiments, the mask 636 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A laser beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 636 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 636 is formed using phase-shift technology. In the phase shift mask (PSM) version of the mask 636, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 634 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 638, an etching process to form various etched regions in the semiconductor wafer 638, and / or other suitable processes.

[0168] The semiconductor device fabrication plant 628 includes wafer fabrication 640. The semiconductor device fabrication plant 628 is a semiconductor device fabrication enterprise that includes one or more manufacturing facilities for fabricating various different semiconductor device products. In some embodiments, the semiconductor device fabrication plant 628 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) fabrication of multiple semiconductor device products, while a second manufacturing facility may provide back end of line (BEOL) fabrication for the interconnect and packaging of semiconductor device products, and a third manufacturing facility may provide other services for the foundry enterprise.

[0169] The semiconductor device fabrication plant 628 uses a mask 636 fabricated by a mask mechanism 626 to fabricate the semiconductor structures or semiconductor devices 642 of the present disclosure. Thus, the semiconductor device fabrication plant 628 at least indirectly uses the semiconductor device design layout 630 to fabricate the semiconductor structures or semiconductor devices 642 of the present disclosure. Further, the semiconductor wafer 638 includes a silicon substrate or other suitable substrate having material layers formed thereon, and the semiconductor wafer 638 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps). In some embodiments, the semiconductor wafer 638 is fabricated by the semiconductor device fabrication plant 628 using the mask 636 to form the semiconductor structures or semiconductor devices 642 of the present disclosure. In some embodiments, semiconductor device fabrication includes performing one or more photolithographic exposures at least indirectly based on the semiconductor device design layout 630.

[0170] Embodiments provide a VFET device that includes a layout and structure for reducing the area of the VFET device. The layout and structure include a front-side power contact, a back-side contact, a two-dimensional shape of the back-side contact, and a two-dimensional shape of an MD layer. In some embodiments, the front-side power contact includes a power voltage contact and / or a power reference contact (e.g., ground). In some embodiments, at least one of the back-side contacts is connected to the front side of the device using a filler structure that extends between the back-side contact of the VFET device and a front-side metal layer.

[0171] In some embodiments, a VFET device includes a first VFET and a second VFET. The first VFET has a first drain / source region and a second drain / source region, and the second VFET has a third drain / source region and a fourth drain / source region. The VFET device includes a first power contact (e.g., a power voltage contact) and a second power contact (e.g., a reference contact). The first power contact is located on the front side of the device and coupled to the first drain / source region, and the second power contact is located on the front side of the device and coupled to the third drain / source region. The VFET device further includes a backside contact that is located on the back side of the device and coupled to the second drain / source region and the fourth drain / source region. In some embodiments, a two-dimensional backside contact and / or a two-dimensional MD layer connects multiple transistors (e.g., VFETs) together.

[0172] According to some embodiments, a device includes a first VFET and a second VFET. The first VFET has a first drain / source region and a second drain / source region, and the second VFET has a third drain / source region and a fourth drain / source region. The device includes a first power contact, a second power contact, and a contact. The first power contact is located on the front side of the device and coupled to the first drain / source region, the second power contact is located on the front side of the device and coupled to the third drain / source region, and the contact is located on the back side of the device and coupled to the second drain / source region and the fourth drain / source region.

[0173] In some embodiments, the first power contact is electrically coupled to the first drain / source region through a first metal layer and a diffused upper metal layer. In some embodiments, the diffused upper metal layer is L-shaped, H-shaped, I-shaped, Z-shaped, P-shaped, F-shaped, U-shaped, T-shaped, or 4-shaped. In some embodiments, the second power contact is electrically coupled to the third drain / source region through a first metal layer and a diffused upper metal layer. In some embodiments, the contact is directly connected to the second drain / source region and the fourth drain / source region. In some embodiments, the semiconductor device further includes a gate contact that is located on the front side of the device and coupled to a polysilicon layer, and the polysilicon layer is connected to the first gate of the first vertical field effect transistor and the second gate of the second vertical field effect transistor. In some embodiments, the semiconductor device further includes a filler portion that is configured to electrically connect the contact located on the back side of the device to the front side of the device. In some embodiments, the filler portion includes a deep through hole that is electrically connected to the contact and a polysilicon layer coupled to a front side metal layer. In some embodiments, the contact is L-shaped, H-shaped, I-shaped, Z-shaped, P-shaped, F-shaped, U-shaped, or T-shaped. In some embodiments, the contact is fork-shaped, hammer-shaped, or spoon-shaped.

[0174] According to a further embodiment, a device includes a first VFET and a second VFET. The first VFET has a first drain / source region and a second drain / source region. The second VFET has a third drain / source region and a fourth drain / source region. The device includes a first power contact and a backside contact. The first power contact is located on the front side of the device and is connected to a first front-side metal layer portion. The first front-side metal layer portion is connected to a first MD layer portion connected to the first drain / source region. The backside contact is located on the back side of the device and is directly connected to the second drain / source region and the fourth drain / source region.

[0175] In some embodiments, the semiconductor device further includes a second power contact located on the front side of the device and connected to the third drain / source region. In some embodiments, the second power contact is connected to a second front-side metal layer portion, and the second front-side metal layer portion is connected to a second diffusion upper metal layer portion connected to the third drain / source region. In some embodiments, the semiconductor device further includes a gate contact located on the front side of the device and connected to a polysilicon layer connected to the first gate of the first vertical field-effect transistor and the second gate of the second vertical field-effect transistor. In some embodiments, the semiconductor device further includes a filler configured to electrically connect the backside contact located on the back side of the device to the front side of the device. In some embodiments, the filler includes a deep through hole that electrically connects to the backside contact and the polysilicon layer connected to the second front-side metal layer portion.

[0176] According to a further disclosed aspect, a method of fabricating a device includes: forming a first vertical field-effect transistor having a first drain / source region and a second drain / source region over a substrate; forming a second vertical field-effect transistor having a third drain / source region and a fourth drain / source region over the substrate; forming a first power contact coupled to the first drain / source region on the front side of the device; forming a second power contact coupled to the third drain / source region on the front side of the device; and forming a contact coupled to the second drain / source region and the fourth drain / source region on the back side of the device.

[0177] In some embodiments, forming the first power contact includes forming a first diffusion upper metal layer electrically connected to the first drain / source region over the first drain / source region and forming a first metal layer portion electrically connected to the first diffusion upper metal layer over the first diffusion upper metal layer. Forming the second power contact includes forming a second diffusion upper metal layer electrically connected to the third drain / source region over the third drain / source region and forming another first metal layer portion electrically connected to the second diffusion upper metal layer over the second diffusion upper metal layer. In some embodiments, forming the contact includes forming the contact to be directly connected to the second drain / source region and the fourth drain / source region. In some embodiments, the method further includes forming a filler portion that electrically connects the contact to the front side of the device, wherein forming the filler portion includes forming a deep through hole and forming a polysilicon layer, the deep through hole being configured to be electrically connected to the contact and the polysilicon layer being electrically connected to a front side metal layer.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them; although the embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A first vertical field effect transistor having a first drain / source region and a second drain / source region; A second vertical field effect transistor having a third drain / source region and a fourth drain / source region; a first power contact located on the front side of the device and coupled to the first drain / source region; a second power contact located on the front side of the device and coupled to the third drain / source region; as well as A contact is located on a back side of the device and is coupled to the second drain / source region and the fourth drain / source region.

2. The semiconductor device according to claim 1, wherein: The first power contact is electrically coupled to the first drain / source region through the first metal layer and the diffused upper metal layer.

3. The semiconductor device according to claim 1, wherein: The second power contact is electrically coupled to the third drain / source region through the first metal layer and the diffused upper metal layer.

4. The semiconductor device according to claim 1, wherein: The contact is directly connected to the second drain / source region and the fourth drain / source region.

5. The semiconductor device according to claim 1, wherein: Also includes: A gate contact is located on the front side of the device and is coupled to a polysilicon layer connected to a first gate of the first vertical field effect transistor and a second gate of the second vertical field effect transistor.

6. The semiconductor device according to claim 1, wherein: Also includes: A filler portion is configured to electrically connect the contacts on the back side of the device to the front side of the device.

7. A semiconductor device, characterized in that: include: A first vertical field effect transistor having a first drain / source region and a second drain / source region; A second vertical field effect transistor having a third drain / source region and a fourth drain / source region; a first power contact located on the front side of the device and connected to a first front side metal layer portion connected to a first diffused upper metal layer portion connected to the first drain / source region; as well as A backside contact is located on the backside of the device and is directly connected to the second drain / source region and the fourth drain / source region.

8. The semiconductor device according to claim 7, wherein: Also includes: A second power contact is located on the front side of the device and is connected to the third drain / source region.

9. The semiconductor device according to claim 7, wherein: Also includes: A gate contact is located on the front side of the device and is connected to the polysilicon layer connected to the first gate of the first vertical field effect transistor and the second gate of the second vertical field effect transistor.

10. The semiconductor device according to claim 7, wherein: Also includes: A filler is configured to electrically connect the backside contact on the backside of the device to the frontside of the device.

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