Wiring structure of semiconductor device and semiconductor device
By designing the second opening of rounded corners in the aluminum wiring of the semiconductor device, the stress concentration problem caused by sharp corners of the side wall after wet etching is solved, improving the reliability of the device and simplifying the production process.
Patent Information
- Application Number
- CN202421939119.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-09
AI Technical Summary
In high-voltage, high-power devices and integrated circuits, aluminum wiring is difficult to ensure reliability in harsh environments. The sharp corners of the open side wall formed after wet etching cause stress concentration, reducing device reliability.
A wiring structure of a semiconductor device is designed, including a substrate, an oxide layer, a barrier layer and a metal layer, and a second opening is formed in the metal layer, and the side wall of the second opening is a rounded corner, and the rounded corner is a rounded transition connection between the side wall and the top surface of the metal layer.
Through the rounded corner design, the passivation layer coverage and stress distribution are improved, the reliability of semiconductor devices is improved, additional rounded corner processing steps are avoided, and the production process is simplified.
Smart Images
Figure CN222966138U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a wiring structure of a semiconductor device and a semiconductor device. Background Art
[0002] In high-voltage, high-power devices and integrated circuits, aluminum wiring is required to withstand high voltage and large current, and at the same time, it needs to have good reliability in a harsh environment. Therefore, a thick aluminum layer is often required in semiconductor processes. The etching of the aluminum layer is generally dry etching or wet etching. Among them, when dry etching the aluminum layer, the etching rate is low, the selectivity to photoresist is low, there are many residues on the substrate surface, and the etching chamber is seriously contaminated. While wet etching has the advantages of fast etching rate, low cost, high selectivity, and no substrate damage, so wet etching is widely used.
[0003] As Figure 1 shown, taking the patterned photoresist layer 12 as a mask, wet etching is performed on the aluminum layer 11 on the substrate 10 to form an opening 111 in the aluminum layer 11. Wet etching is isotropic, and the angle between the side wall of the etched opening 111 and the top surface of the aluminum layer 11 is close to a right angle, which is not conducive to the coverage of the passivation layer in the subsequent passivation process, and the sharp corner at the top of the side wall of the opening 111 causes stress concentration here, thereby reducing the reliability of the device.
[0004] Therefore, how to improve the reliability of the device is an urgent problem to be solved. Summary of the Utility Model
[0005] The purpose of the utility model is to provide a wiring structure of a semiconductor device and a semiconductor device, so as to improve the reliability of the semiconductor device.
[0006] To achieve the above purpose, the utility model provides a wiring structure of a semiconductor device, and the semiconductor device includes:
[0007] A substrate;
[0008] An oxide layer, located on the substrate;
[0009] A barrier layer, located on the oxide layer, and a first opening exposing the oxide layer is formed in the barrier layer;
[0010] A metal layer, located on the barrier layer, and the metal layer serves as the wiring structure of the semiconductor device. A second opening exposing the oxide layer is formed in the metal layer. The second opening is located at the top of the first opening, and the top of the side wall of the second opening is a rounded corner, and the rounded corner is a smooth transition connection between the side wall of the second opening and the top surface of the metal layer.
[0011] Optionally, the thickness of the metal layer is
[0012] Optionally, the metal layer is an aluminum layer or a copper layer.
[0013] Optionally, the angle between the side wall of the second opening and the surface of the barrier layer around the second opening is an acute angle.
[0014] Optionally, the range of the acute angle is 50° to 70°.
[0015] Optionally, the range of the acute angle is 58° to 65°.
[0016] Optionally, the bottom width of the second opening is 18 μm to 220 μm, and the top width of the second opening is 22 μm to 230 μm.
[0017] Optionally, the rounded corner protrudes towards the outside of the top of the side wall of the second opening, and the center of the rounded corner is located within the metal layer.
[0018] Optionally, the radius of the rounded corner is 20 μm to 30 μm.
[0019] Optionally, a film layer structure is formed on the substrate of the semiconductor device, and the film layer structure includes at least one of a semiconductor film layer, a metal film layer, and an insulating film layer.
[0020] Optionally, the semiconductor device further includes:
[0021] A passivation layer, located in the first opening and the second opening, and extending onto a part of the metal layer.
[0022] The present utility model further provides a semiconductor device, including the wiring structure of the semiconductor device.
[0023] Optionally, the semiconductor device is a VDMOS device, and the VDMOS device further includes:
[0024] A drift region, located on the substrate, the substrate serving as a drain region, and the drain region having the same doping type as the drift region;
[0025] A body region, extending from the top surface of the drift region into the drift region, and the drift region having a doping type opposite to that of the body region;
[0026] A source region, located within the body region, and the body region having a doping type opposite to that of the source region;
[0027] The gate oxide layer and the gate are stacked on the drift region from bottom to top. The gate oxide layer and the gate extend from the drift region to a part of the source region and a part of the body region. The oxide layer, the barrier layer, and the metal layer extend from the drift region to the gate, a part of the source region, and a part of the body region. A fourth opening exposing a part of the source region and a part of the body region is formed in the oxide layer. The barrier layer and the metal layer extend to the source region and the body region exposed by the fourth opening. The metal layer serves as the source electrode, and the passivation layer exposes a part of the source electrode.
[0028] The drain is located on the bottom surface of the substrate.
[0029] The first opening and the second opening are located in the barrier layer and the metal layer in the voltage dividing ring region.
[0030] Optionally, the semiconductor device is an IGBT device, and the IGBT device further includes:
[0031] A buffer region is located on the substrate. The substrate serves as the collector region, and the doping type of the collector region is opposite to that of the buffer region.
[0032] A drift region is located on the buffer region, and the doping type of the buffer region is the same as that of the drift region.
[0033] A base region extends from the top surface of the drift region into the drift region, and the doping type of the drift region is opposite to that of the base region.
[0034] An emitter region is located in the base region, and the doping type of the base region is opposite to that of the emitter region.
[0035] The gate oxide layer and the gate are stacked on the drift region from bottom to top. The gate oxide layer and the gate extend from the drift region to a part of the emitter region and a part of the base region. The oxide layer, the barrier layer, and the metal layer extend from the drift region to the gate, a part of the emitter region, and a part of the base region. A fourth opening exposing a part of the emitter region and a part of the base region is formed in the oxide layer. The barrier layer and the metal layer extend to the emitter region and the base region exposed by the fourth opening. The metal layer serves as the emitter electrode, and the passivation layer exposes a part of the emitter electrode.
[0036] The collector is located on the bottom surface of the substrate.
[0037] The first opening and the second opening are located in the barrier layer and the metal layer in the voltage dividing ring region.
[0038] Compared with the prior art, in the wiring structure of the semiconductor device and the semiconductor device of the present utility model, since the semiconductor device includes: a substrate; an oxide layer located on the substrate; a barrier layer located on the oxide layer, a first opening exposing the oxide layer is formed in the barrier layer; a metal layer located on the barrier layer, the metal layer serves as the wiring structure of the semiconductor device, a second opening exposing the oxide layer is formed in the metal layer, the second opening is located on top of the first opening, and the top of the side wall of the second opening is rounded, and the rounded corner is a smooth transition connection between the side wall of the second opening and the top surface of the metal layer, the reliability of the semiconductor device can be improved. Description of the Drawings
[0039] Figure 1 is a schematic structural diagram of a semiconductor device;
[0040] Figure 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present utility model;
[0041] Figure 3 is a schematic structural diagram during the manufacturing of a semiconductor device according to an embodiment of the present utility model;
[0042] Figures 4a to 4b is a schematic structural diagram of a VDMOS device according to an embodiment of the present utility model;
[0043] Figures 5a to 5b is a schematic structural diagram of an IGBT device according to another embodiment of the present utility model.
[0044] Among them, the Figures 1 to 5b description of the reference numerals in the attached drawings is as follows:
[0045] 10 - Substrate; 11 - Aluminum layer; 111 - Opening; 12 - Patterned photoresist layer; 20 - Substrate; 21 - Metal layer; 211 - Second opening; 22 - Barrier layer; 221 - First opening; 23 - Oxide layer; 24 - Patterned photoresist layer; 241 - Third opening; 25 - Passivation layer; 261 - Source region; 262 - Body region; 263 - Drift region; 264 - Drain region; 265 - Gate oxide layer; 266 - Gate; 267 - Drain; 271 - Emitter region; 272 - Base region; 273 - Drift region; 274 - Buffer region; 275 - Collector region; 276 - Gate oxide layer; 277 - Gate; 278 - Collector. Detailed Embodiments
[0046] To make the objectives, advantages, and features of the present utility model clearer, the following provides a further detailed description of the wiring structure of the semiconductor device and the semiconductor device proposed by the present utility model. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present utility model.
[0047] An embodiment of the present utility model provides a wiring structure of a semiconductor device. The semiconductor device includes: a substrate; an oxide layer located on the substrate; a barrier layer located on the oxide layer, and a first opening exposing the oxide layer is formed in the barrier layer; a metal layer located on the barrier layer, and the metal layer serves as the wiring structure of the semiconductor device. A second opening exposing the oxide layer is formed in the metal layer. The second opening is located at the top of the first opening, and the top of the sidewall of the second opening is rounded. The rounded corner is a smooth transition connection between the sidewall of the second opening and the top surface of the metal layer.
[0048] The following refers to Figures 2 to 3 a more detailed introduction to the wiring structure of the semiconductor device provided by this embodiment, Figures 2 to 3 which is also a longitudinal sectional view.
[0049] The substrate 20 is one of sapphire, silicon, germanium, silicon carbide, aluminum nitride, gallium arsenide, gallium nitride, and gallium oxide substrates, etc., but not limited thereto.
[0050] Structures such as doping regions may be formed in the substrate 20, and a film layer structure may be formed on the substrate 20. The film layer structure includes, for example, at least one of a semiconductor film layer, a metal film layer, and an insulating film layer, etc.
[0051] The oxide layer 23 is located on the substrate 20. The oxide layer 23 can play an insulating and isolating role.
[0052] As Figure 2 shown, the barrier layer 22 is located on the oxide layer 23, and a first opening 221 exposing the oxide layer 23 is formed in the barrier layer 22.
[0053] In one embodiment, the top width of the first opening 221 is greater than the bottom width of the first opening 221.
[0054] As Figure 2As shown, the metal layer 21 is located on the barrier layer 22. A second opening 211 exposing the oxide layer 23 is formed in the metal layer 21. The second opening 211 is located at the top of the first opening 221. The top of the sidewall of the second opening 211 is rounded. The rounded corner is a smooth transition connection between the sidewall of the second opening 211 and the top surface of the metal layer 21, that is, a section of distance from the sidewall of the second opening 211 to the top surface of the metal layer 21 is an arc.
[0055] Wherein, the rounded corner protrudes towards the outside of the top of the sidewall of the second opening 211, and the center of the rounded corner is located within the metal layer 21.
[0056] The barrier layer 22 is used to prevent etching of the oxide layer 23 when wet-etching the metal layer 21 to form the second opening 211. The oxide layer 23 is used to prevent etching of the substrate 20 when wet-etching the barrier layer 22 to form the first opening 221.
[0057] Since the adhesion between the metal layer 21 and the substrate 20 and the oxide layer 23 is poor (i.e., the bonding force is not good), by providing the barrier layer 22 between the metal layer 21 and the oxide layer 23, the bonding force between the metal layer 21 and the substrate 20 and the oxide layer 23 can be improved; and, during the thermal process, the barrier layer 22 can also be used to block the diffusion of metal atoms in the metal layer 21 into the substrate 20 and the oxide layer 23.
[0058] The barrier layer 22 can be a stacked metal material layer and a metal nitride layer, such as a stacked titanium layer and a titanium nitride layer, but is not limited thereto.
[0059] In one embodiment, the thickness of the metal layer 21 is
[0060] The included angle between the sidewall of the second opening 211 and the surface of the barrier layer 22 outside the second opening 211 is an acute angle, that is, the top width d2 of the second opening 211 is greater than the bottom width d1 of the second opening 211.
[0061] Preferably, the range of the acute angle is 50° to 70°; more preferably, the range of the acute angle is 58° to 65°.
[0062] In one embodiment, the bottom width d1 of the second opening 211 is 18 μm to 220 μm, and the top width d2 of the second opening 211 is 22 μm to 230 μm.
[0063] In one embodiment, the top width of the first opening 221 is equal to the bottom width d1 of the second opening 211.
[0064] In one embodiment, the radius R of the rounded corner is 20 μm to 30 μm.
[0065] The metal layer 21 can be an aluminum layer or a copper layer, but is not limited thereto.
[0066] The metal layer 21 serves as a wiring structure of the semiconductor device, and the wiring structure can be used for electrodes, optimizing the electric field distribution, circuit connection, heat dissipation, voltage regulation, etc.
[0067] In one embodiment, the semiconductor device further includes: a passivation layer 25, located in the first opening 221 and the second opening 211, and extending onto a part of the metal layer 21. Wherein, the passivation layer 25 can fill the first opening 221 and the second opening 211, and the passivation layer 25 can expose a part of the metal layer 21 outside the second opening 211.
[0068] As Figure 3 shown, the manufacturing method of the semiconductor device may include: First, provide a substrate 20, and sequentially form an oxide layer 23 and a barrier layer 22 on the substrate 20; then, form a metal layer 21 on the barrier layer 22; then, form a patterned photoresist layer 24 on the metal layer 21, and the patterned photoresist layer 24 has a third opening 241 exposing a part of the surface of the metal layer 21; then, using the patterned photoresist layer 24 as a mask, etch the metal layer 21 and the barrier layer 22 by a wet etching process to form a second opening 211 penetrating the metal layer 21 and a first opening 221 penetrating the barrier layer 22, and the second opening 211 and the first opening 221 expose the oxide layer 23. Wherein, by adjusting the etching parameters (such as the type and concentration of the etching solution, etching time, and etching temperature, etc.), the top of the sidewall of the second opening 211 is a rounded corner.
[0069] In one embodiment, the etching solution can be a mixed solution of phosphoric acid, nitric acid, and acetic acid.
[0070] Wherein, the bottom width d1 of the second opening 211 is greater than the width d3 of the third opening 241.
[0071] In one embodiment, the width d3 of the third opening 241 is 6 μm to 208 μm.
[0072] As can be seen from the above, since the top of the sidewall of the second opening 211 formed in the metal layer 21 is rounded, and the rounded corner is a smooth transition connection between the sidewall of the second opening 211 and the top surface of the metal layer 21, it is beneficial for the passivation layer 25 to cover the metal layer 21, and it can prevent the passivation layer 25 above the top of the sidewall of the second opening 211 from bulging upward, resulting in an uneven surface of the passivation layer 25. Moreover, it can avoid stress concentration at the top of the sidewall of the second opening 211, thereby preventing the separation between the metal layer 21 and the passivation layer 25 at the top of the sidewall of the second opening 211 during the operation of the semiconductor device. Therefore, the reliability of the semiconductor device can be improved.
[0073] In addition, in this embodiment, when the second opening 211 is formed in the metal layer 21 by using a wet etching process, the top of the sidewall of the second opening 211 is directly etched into a rounded corner, so that there is no need to separately use other processes to round the top of the sidewall of the second opening 211 after wet etching, which simplifies the process and saves production costs.
[0074] In summary, for the wiring structure of the semiconductor device of the present invention, the semiconductor device includes: a substrate; an oxide layer located on the substrate; a barrier layer located on the oxide layer, and a first opening exposing the oxide layer is formed in the barrier layer; a metal layer located on the barrier layer, and the metal layer serves as the wiring structure of the semiconductor device. A second opening exposing the oxide layer is formed in the metal layer, the second opening is located at the top of the first opening, and the top of the sidewall of the second opening is rounded, and the rounded corner is a smooth transition connection between the sidewall of the second opening and the top surface of the metal layer. The present invention enables the improvement of the reliability of the semiconductor device.
[0075] An embodiment of the present invention provides a semiconductor device including the wiring structure of the semiconductor device described above.
[0076] Refer to the following Figures 4a to 5b for a more detailed introduction to the semiconductor device provided in this embodiment, Figures 4a to 5b which is also a longitudinal sectional view.
[0077] The wiring structure of the semiconductor device is as described above and will not be elaborated here.
[0078] In one embodiment, as Figure 4a and Figure 4bAs shown, the semiconductor device is a VDMOS (Vertical DoubleDiffusion Metal Oxide Semiconductor Field Effect Transistor) device. Figure 4a Shown is the structure of the cell region of the VDMOS device. Figure 4b Shown is the structure of the voltage-dividing ring of the VDMOS device. The voltage-dividing ring surrounds and encloses the cell region. The VDMOS device further includes:
[0079] A drift region 263, located on the substrate 20, where the substrate 20 serves as a drain region 264, and the drain region 264 has the same doping type as the drift region 263.
[0080] A body region 262, extending from the top surface of the drift region 263 into the drift region 263, and the drift region 263 has a doping type opposite to that of the body region 262.
[0081] A source region 261, located within the body region 262, and the body region 262 has a doping type opposite to that of the source region 261.
[0082] A gate oxide layer 265 and a gate electrode 266, stacked on the drift region 263 from bottom to top. The gate oxide layer 265 and the gate electrode 266 extend from part of the drift region 263 to part of the source region 261 and part of the body region 262. The oxide layer 23, the barrier layer 22, and the metal layer 21 extend from the drift region 263 to the gate electrode 266, part of the source region 261, and part of the body region 262. A fourth opening (not shown) exposing part of the source region 261 and part of the body region 262 is formed in the oxide layer 23. The barrier layer 22 and the metal layer 21 extend to the source region 261 and the body region 262 exposed by the fourth opening, and the barrier layer 22 and the metal layer 21 are electrically connected to the source region 261. The metal layer 21 serves as the source electrode, and the passivation layer 25 exposes part of the source electrode.
[0083] A drain electrode 267, located on the bottom surface of the substrate 20 (drain region 264).
[0084] Wherein, the first opening 221 and the second opening 211 can be located in the barrier layer 22 and the metal layer 21 in the voltage-dividing ring region.
[0085] In Figure 4a In the shown cell region, the oxide layer 23 can be replaced by other insulating layers, or other insulating layers can be formed between the oxide layer 23, the gate oxide layer 265, the gate electrode 266, and the drift region 263. InFigure 4b In the voltage dividing ring shown, other insulating layers may be formed between the oxide layer 23, the gate oxide layer 265, and the gate 266.
[0086] In one embodiment, the doping type of the source region 261 is N+, the doping type of the body region 262 is P, the doping type of the drift region 263 is N-, and the doping type of the drain region 264 is N+.
[0087] In another embodiment, as Figure 5a and Figure 5b shown, the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) device. Figure 5a Shown is the structure of the cell region of the IGBT device. Figure 5b Shown is the structure of the voltage dividing ring of the IGBT device. The voltage dividing ring surrounds and encloses the cell region. The IGBT device further includes:
[0088] A buffer region 274, located on the substrate 20. The substrate 20 serves as a collector region 275, and the doping type of the collector region 275 is opposite to that of the buffer region 274.
[0089] A drift region 273, located on the buffer region 274. The doping type of the buffer region 274 is the same as that of the drift region 273.
[0090] A base region 272, extending from the top surface of the drift region 273 into the drift region 273. The doping type of the drift region 273 is opposite to that of the base region 272.
[0091] An emitter region 271, located within the base region 272. The doping type of the base region 272 is opposite to that of the emitter region 271.
[0092] A gate oxide layer 276 and a gate 277, stacked on the drift region 273 from bottom to top. The gate oxide layer 276 and the gate 277 extend from part of the drift region 273 to part of the emitter region 271 and part of the base region 272. The oxide layer 23, the barrier layer 22, and the metal layer 21 extend from the drift region 273 to the gate 277, part of the emitter region 271, and part of the base region 272. A fourth opening (not shown) exposing part of the emitter region 271 and part of the base region 272 is formed in the oxide layer 23. The barrier layer 22 and the metal layer 21 extend to the emitter region 271 and the base region 272 exposed by the fourth opening. The barrier layer 22 and the metal layer 21 are electrically connected to the emitter region 271. The metal layer 21 serves as an emitter, and the passivation layer 25 exposes part of the emitter.
[0093] The collector 278 is located at the bottom surface of the substrate 20 (collector region 275).
[0094] Wherein, the first opening 221 and the second opening 211 may be located in the barrier layer 22 and the metal layer 21 of the voltage dividing ring region.
[0095] In Figure 5a the cell region shown, the oxide layer 23 may be replaced by other insulating layers, or other insulating layers may be formed between the oxide layer 23, the gate oxide layer 276, the gate 277, and the drift region 273; in Figure 5b the voltage dividing ring shown, other insulating layers may be formed between the oxide layer 23, the gate oxide layer 276, and the gate 277.
[0096] In an embodiment, the doping type of the emitter region 271 is N+, the doping type of the base region 272 is P, the doping type of the drift region 273 is N-, the doping type of the buffer region 274 is N+, and the doping type of the collector region 275 is P+.
[0097] It should be noted that the structures of the VDMOS device and the IGBT device are not limited to those shown above Figures 4a to 4b and Figures 5a to 5b shown. The VDMOS device and the IGBT device may also include other structures for improving device performance; the types of semiconductor devices are not limited to the VDMOS device and the IGBT device.
[0098] Since the semiconductor device includes the wiring structure of the semiconductor device, the reliability of the semiconductor device can be improved.
[0099] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.
Claims
1. A wiring structure of a semiconductor device, characterized in that: Semiconductor devices include: substrate; an oxide layer, located on the substrate; A barrier layer, located on the oxide layer, wherein a first opening exposing the oxide layer is formed in the barrier layer; A metal layer is located on the barrier layer, and the metal layer serves as a wiring structure of the semiconductor device. A second opening is formed in the metal layer to expose the oxide layer. The second opening is located on the top of the first opening, and the top of the side wall of the second opening is rounded. The rounded corner is a smooth transition connection between the side wall of the second opening and the top surface of the metal layer.
2. The wiring structure of a semiconductor device according to claim 1, wherein: The thickness of the metal layer is 3. The wiring structure of a semiconductor device according to claim 1, wherein: The metal layer is an aluminum layer or a copper layer.
4. The wiring structure of a semiconductor device according to claim 1, wherein: An angle between a side wall of the second opening and a surface of the barrier layer at a periphery of the second opening is an acute angle.
5. The wiring structure of a semiconductor device according to claim 4, characterized in that The acute angle ranges from 50° to 70°.
6. The wiring structure of a semiconductor device according to claim 5, characterized in that The acute angle ranges from 58° to 65°.
7. The wiring structure of a semiconductor device according to claim 1, wherein: A bottom width of the second opening is 18 μm to 220 μm, and a top width of the second opening is 22 μm to 230 μm.
8. The wiring structure of a semiconductor device according to claim 1, wherein: The fillet protrudes toward the outer side of the top of the side wall of the second opening, and the center of the fillet is located in the metal layer.
9. The wiring structure of a semiconductor device according to claim 1, wherein: The radius of the fillet is 20 μm to 30 μm.
10. The wiring structure of a semiconductor device according to claim 1, wherein: A film layer structure is formed on the substrate of the semiconductor device, and the film layer structure includes at least one of a semiconductor film layer, a metal film layer and an insulating film layer.
11. The wiring structure of a semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The passivation layer is located in the first opening and the second opening and extends onto a portion of the metal layer.
12. A semiconductor device, characterized in that: A wiring structure comprising a semiconductor device as claimed in any one of claims 1 to 11.
13. The semiconductor device according to claim 12, wherein: The semiconductor device is a VDMOS device, and the VDMOS device further comprises: A drift region, located on the substrate, the substrate serving as a drain region, the drain region having the same doping type as the drift region; A body region extending from the top surface of the drift region into the drift region, wherein the drift region and the body region have opposite doping types; A source region, located in the body region, the body region and the source region have opposite doping types; A gate oxide layer and a gate are stacked on the drift region from bottom to top, the gate oxide layer and the gate extend from the drift region to a portion of the source region and a portion of the body region, the oxide layer, the barrier layer and the metal layer extend from the drift region to the gate, a portion of the source region and a portion of the body region, a fourth opening is formed in the oxide layer to expose a portion of the source region and a portion of the body region, the barrier layer and the metal layer extend to the source region and the body region exposed by the fourth opening; the metal layer serves as a source electrode, and the passivation layer exposes a portion of the source electrode; A drain electrode, located on the bottom surface of the substrate; The first opening and the second opening are located in the barrier layer and the metal layer in a voltage divider ring region.
14. The semiconductor device according to claim 12, wherein: The semiconductor device is an IGBT device, and the IGBT device further includes: A buffer zone, located on the substrate, the substrate serving as a collector zone, the collector zone having a doping type opposite to that of the buffer zone; A drift region, located on the buffer region, the buffer region and the drift region have the same doping type; A base region extending from the top surface of the drift region into the drift region, wherein the drift region and the base region have opposite doping types; An emitter region, located in the base region, the base region and the emitter region have opposite doping types; A gate oxide layer and a gate are stacked on the drift region from bottom to top, the gate oxide layer and the gate extend from the drift region to a portion of the emitter region and a portion of the base region, the oxide layer, the barrier layer and the metal layer extend from the drift region to the gate, a portion of the emitter region and a portion of the base region, a fourth opening exposing a portion of the emitter region and a portion of the base region is formed in the oxide layer, the barrier layer and the metal layer extend to the emitter region and the base region exposed by the fourth opening; the metal layer serves as an emitter, and the passivation layer exposes a portion of the emitter; A collector electrode, located on the bottom surface of the substrate; The first opening and the second opening are located in the barrier layer and the metal layer in a voltage divider ring region.