Characteristic current generating system of square wave envelope

Abstract

The utility model discloses a square wave envelope characteristic current generation system, comprising an overvoltage protection unit, a power MOS tube and current limiting protection unit, a rectification unit, an MOS tube driving unit, a signal conditioning and isolation unit, a processor unit and a communication unit. The rectification unit is electrically connected with a power distribution network alternating current system, a power MOS tube and a current limiting protection unit through wires. The rectification unit is in electrical input connection with an MOS tube driving unit and an overvoltage protection unit through wires. The overvoltage protection unit is in electrical input connection with the power MOS tube and the current-limiting protection unit through wires. The communication unit, the processor unit, the signal conditioning and isolating unit, the MOS tube driving unit and the power MOS tube and current-limiting protection unit are electrically connected in sequence through wires. According to the utility model, the technical problems of high heat productivity and difficult heat dissipation caused by weak high-voltage impact resistance and complex circuit structure of the existing circuit are solved.

Description

Technical Field

[0001] The utility model relates to the technical field of distribution network topology identification, in particular to a characteristic current generating system with a square wave envelope. Background Art

[0002] Topology identification technology is a necessary technical basis for promoting the construction of digital distribution networks. Topology identification technology includes the big data method and the signal injection method. The big data method has high requirements for the power grid, requiring that each user load cannot be too light, the line topology cannot be too complex, and the identification result needs to be iterated multiple times, often taking several days or even weeks to output the correct result; the signal injection method has low requirements for the power grid, fast identification speed, and high accuracy. In the power frequency distortion method of the signal injection method, a characteristic current of dozens of amperes is generated by controlling the switching of loads on the power frequency power line, which has a large impact on the power grid and is rarely used. Currently, the commonly used method is to inject a tiny characteristic current with a square wave envelope. However, the existing installation mode determines that the characteristic current generating circuit needs to withstand a lightning strike residual voltage of 1.2 kV to 1.4 kV, as well as a working environment with very poor heat dissipation conditions, resulting in a high damage rate during on-site use; for the circuit involved in topology identification using the injection of a tiny characteristic current with a square wave envelope, the lightning strike residual voltage falls on the current limiting resistor and the power MOS transistor. If the power MOS transistor is in the conducting state, it will withstand a peak current of hundreds of amperes, far exceeding its rated parameters and being extremely easy to damage; secondly, the existing power MOS transistor drive circuit requires dual-transistor drive, as well as a stable power supply voltage and a reverse discharge circuit. The circuit design is complex, with many components, and the peak power of the circuit itself reaches more than 60 watts. With many circuit components, a large amount of heat is generated, and combined with limited installation space and poor heat dissipation environment, the damage rate is relatively high in practical applications. Therefore, there is an urgent need to propose a characteristic current generating system with a square wave envelope to solve the technical problems of the existing circuit's weak ability to withstand high-voltage impacts, as well as the large amount of heat generated and difficult heat dissipation caused by the complex circuit structure. Summary of the Utility Model

[0003] The main purpose of the utility model is to propose a characteristic current generating system with a square wave envelope, aiming to solve the technical problems of the existing circuit's weak ability to withstand high-voltage impacts, as well as the large amount of heat generated and difficult heat dissipation caused by the complex circuit structure.

[0004] To achieve the above object, the utility model provides a characteristic current generating system with a square wave envelope, wherein the characteristic current generating system with a square wave envelope includes: an overvoltage protection unit, a power MOS transistor and a current limiting protection unit, a rectification unit, a MOS transistor drive unit, a signal conditioning and isolation unit, a processor unit, and a communication unit;

[0005] The rectification unit is electrically connected to the AC system of the distribution network, the power MOS transistor, and the current limiting protection unit through wires respectively, and the rectification unit is electrically connected to the MOS transistor driving unit and the overvoltage protection unit through wires respectively; the overvoltage protection unit is electrically connected to the power MOS transistor and the current limiting protection unit through wires; the communication unit, the processor unit, the signal conditioning and isolation unit, the MOS transistor driving unit, the power MOS transistor, and the current limiting protection unit are electrically connected in sequence through wires.

[0006] One of the preferred solutions is that the rectification unit is electrically connected to the AC system of the distribution network through an AC line interface; the AC line interface includes two contacts, namely the live wire and the neutral wire.

[0007] One of the preferred solutions is that the rectification unit includes a resistor R1 and a rectifier bridge BR1;

[0008] One end of the resistor R1 is connected to the live wire of the AC line interface, the other end of the resistor R1 is connected to the 2-pin of the rectifier bridge BR1, the 1-pin of the rectifier bridge BR1 is connected to the neutral wire of the AC line interface, the 3-pin of the rectifier bridge BR1 is connected to the power MOS transistor, the current limiting protection unit, the MOS transistor driving unit, and the overvoltage protection unit respectively, and the 4-pin of the rectifier bridge BR1 is grounded.

[0009] One of the preferred solutions is that the rectifier bridge BR1 includes a diode E1, a diode E2, a diode E3, and a diode E4;

[0010] The positive electrode of the diode E1 is connected to the neutral wire of the AC line interface and the negative electrode of the diode E2 respectively, the negative electrode of the diode E1 is connected to the power MOS transistor, the current limiting protection unit, the MOS transistor driving unit, the overvoltage protection unit, and the negative electrode of the diode E2 respectively, the positive electrode of the diode E2 is connected to the negative electrode of the diode E3 and the resistor R1 respectively, and the positive electrode of the diode E3 is connected to the positive electrode of the diode E4 and the ground terminal respectively.

[0011] One of the preferred solutions is that the signal conditioning and isolation unit includes a capacitor C2, a MOS transistor V1, an opto-isolator D2, a resistor R9, and a resistor R10; the gate of the MOS transistor V1 is connected to the capacitor C2 and the resistor R10 respectively, the other end of the capacitor C2 is connected to the processor unit; the source of the MOS transistor V1 and the other end of the resistor R10 are grounded; the drain of the MOS transistor V1 is connected to the 2-pin of the opto-isolator D2, the 1-pin of the opto-isolator D2 is connected to the power supply terminal through the resistor R9, the 3-pin of the opto-isolator D2 is grounded, and the 4-pin of the opto-isolator D2 is connected to the MOS transistor driving unit.

[0012] One of the preferred solutions, the MOS transistor driving unit includes a switching chip D3, a resistor R7, a capacitor C1, a voltage stabilizing diode VD1, a resistor R3 and a resistor R2;

[0013] Pins 1, 2, and 4 of the switching chip D3 are grounded;

[0014] Pins 3 and 8 of the switching chip D3 are connected to the resistor R7. The other end of the resistor R7 is respectively connected to the signal conditioning and isolation unit, the power MOS transistor and the current limiting and protection unit, and the capacitor C1. The other end of the capacitor C1 is respectively connected to the voltage stabilizing diode VD1 and the ground terminal. The other end of the voltage stabilizing diode VD1 is respectively connected to the power MOS transistor and the current limiting and protection unit, and the resistor R3. The other end of the resistor R3 is connected to the rectification unit through the resistor R2;

[0015] Pins 6 and 7 of the switching chip D3 are connected to the power MOS transistor and the current limiting and protection unit;

[0016] Pin 5 of the switching chip D3 is connected to the signal conditioning and isolation unit.

[0017] One of the preferred solutions, the power MOS transistor and the current limiting and protection unit includes a MOS transistor Q1 and a resistor R6;

[0018] The drain of the MOS transistor Q1 is connected to the rectification unit. The source of the MOS transistor Q1 is respectively connected to the signal conditioning and isolation unit, the resistor R7, the resistor R6 and the capacitor C1. The other end of the resistor R6 is connected to pins 6 and 7 of the switching chip D3. The gate of the MOS transistor Q1 is respectively connected to the MOS transistor driving unit and the overvoltage protection unit.

[0019] One of the preferred solutions, the overvoltage protection unit includes a voltage regulator U1, a resistor R4 and a resistor R5. Pin 1 of the voltage regulator U1 is connected to the power MOS transistor and the current limiting and protection unit. Pin 2 of the voltage regulator U1 is respectively connected to the resistor R4 and the resistor R5. The other end of the resistor R4 is connected to the rectification unit. Pin 3 of the voltage regulator U1 and the other end of the resistor R5 are grounded.

[0020] One of the preferred solutions, the processor unit includes a processor D1;

[0021] Pin 11 of the processor D1 is connected to the signal conditioning and isolation unit;

[0022] Pin 13 of the processor D1 is connected to the power supply terminal;

[0023] Pins 33 and 34 of the processor D1 are connected to the clock circuit;

[0024] Pin 53 of the processor D1 is grounded.

[0025] One of the preferred solutions is that the clock circuit includes a crystal oscillator XL1, a capacitor C3, and a capacitor C4;

[0026] Pin 1 of the crystal oscillator XL1 is respectively connected to pin 34 of the processor D1 and the capacitor C4. Pin 2 of the crystal oscillator XL1 is respectively connected to pin 33 of the processor D1 and the capacitor C3. The other ends of pin 3 of the crystal oscillator XL1, the capacitor C4, and the capacitor C3 are grounded, and pin 4 of the crystal oscillator XL1 is grounded.

[0027] In the above technical solution of the present utility model, the characteristic current generation system of the square wave envelope includes: an overvoltage protection unit, a power MOS transistor and a current limiting protection unit, a rectification unit, a MOS transistor driving unit, a signal conditioning and isolation unit, a processor unit, and a communication unit; the rectification unit is electrically connected to the AC power distribution system, the power MOS transistor and the current limiting protection unit through wires respectively, and the rectification unit is electrically connected to the MOS transistor driving unit and the overvoltage protection unit through wires respectively for input; the overvoltage protection unit is electrically connected to the power MOS transistor and the current limiting protection unit through wires for input; the communication unit, the processor unit, the signal conditioning and isolation unit, the MOS transistor driving unit, and the power MOS transistor and the current limiting protection unit are electrically connected in sequence through wires. The structure of the present utility model is concise, small-package devices are selected, which can reduce the space required for installation, and at the same time improve the specific heat capacity of the module, solving the technical problems of the weak high-voltage impact resistance of the existing circuit and the large heat generation and difficult heat dissipation caused by the complex circuit structure.

[0028] In the present utility model, when the AC line is struck by lightning, the residual voltage of the varistor is usually between 1.2 kV and 1.4 kV. If the power MOS transistor is in the on state, the current passing through it far exceeds its rated parameters and it is extremely easy to be burned out. Through the overvoltage protection circuit, when it is detected that the power supply voltage exceeds the normal level, the power MOS transistor is quickly turned off, which can avoid its burnout. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0030] Figure 1 FIG. is a schematic structural diagram of a characteristic current generation system of a square wave envelope according to an embodiment of the present utility model;

[0031] Figure 2 FIG. is a schematic circuit diagram of a characteristic current generation system of a square wave envelope according to an embodiment of the present utility model.

[0032] The realization, functional features and advantages of the purpose of the present utility model will be further described in conjunction with the embodiments with reference to the accompanying drawings. Specific embodiments

[0033] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0034] In addition, in the present utility model, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0035] Moreover, the technical solutions between the various embodiments of the present utility model can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present utility model.

[0036] See Figure 1 - Figure 2 , according to one aspect of the present utility model, the present utility model provides a characteristic current generating system with a square-wave envelope. Among them, the characteristic current generating system with a square-wave envelope includes: an overvoltage protection unit, a power MOS transistor and a current-limiting protection unit, a rectification unit, a MOS transistor driving unit, a signal conditioning and isolation unit, a processor unit and a communication unit; the rectification unit is electrically connected to the distribution network AC system, the power MOS transistor and the current-limiting protection unit through wires respectively, and the rectification unit is electrically connected to the MOS transistor driving unit and the overvoltage protection unit through wires respectively for input; the overvoltage protection unit is electrically connected to the power MOS transistor and the current-limiting protection unit through wires for input; the communication unit, the processor unit, the signal conditioning and isolation unit, the MOS transistor driving unit and the power MOS transistor and the current-limiting protection unit are electrically connected in sequence through wires.

[0037] Specifically, in this embodiment, the rectification unit is electrically connected to the distribution network AC system through an AC line interface; the AC line interface includes two contacts, a live wire and a neutral wire; the AC line interface is a 220V power supply interface of the distribution network AC system, and the AC line interface is the power input interface of the characteristic current generating system with a square-wave envelope and also the characteristic current output interface.

[0038] Specifically, in this embodiment, the rectification unit includes a resistor R1 and a rectifier bridge BR1; one end of the resistor R1 is connected to the live wire of the AC line interface, the other end of the resistor R1 is connected to the pin 2 of the rectifier bridge BR1, the pin 1 of the rectifier bridge BR1 is connected to the neutral wire of the AC line interface, the pin 3 of the rectifier bridge BR1 is respectively connected to the power MOS transistor, the current limiting protection unit, the MOS transistor driving unit and the overvoltage protection unit, and the pin 4 of the rectifier bridge BR1 is grounded; the resistor R1 is connected in series on the high-voltage line to provide preliminary current limiting function and protect the subsequent circuit; the rectifier bridge BR1 realizes the conversion between the AC voltage and the pulsating DC voltage and the transmission of current; the rectification unit converts the AC 220V power supply into a pulsating DC and supplies it to the power MOS transistor, the current limiting protection unit, the overvoltage protection unit and the MOS transistor driving unit, and at the same time converts the DC characteristic current generated by the power MOS transistor and the current limiting protection unit into the 220V distribution network AC system.

[0039] Specifically, in this embodiment, the rectifier bridge BR1 includes diodes E1, E2, E3 and E4; the positive electrode of the diode E1 is respectively connected to the neutral wire of the AC line interface and the negative electrode of the diode E2, the negative electrode of the diode E1 is respectively connected to the power MOS transistor, the current limiting protection unit, the MOS transistor driving unit, the overvoltage protection unit and the negative electrode of the diode E2, the positive electrode of the diode E2 is respectively connected to the negative electrode of the diode E3 and the resistor R1, and the positive electrode of the diode E3 is respectively connected to the positive electrode of the diode E4 and the ground terminal.

[0040] Specifically, in this embodiment, the signal conditioning and isolation unit includes a capacitor C2, a MOS transistor V1, an opto-isolator D2, a resistor R8, a resistor R9, and a resistor R10; the gate of the MOS transistor V1 is respectively connected to the capacitor C2 and the resistor R10, and the other end of the capacitor C2 is connected to the processor unit; the source of the MOS transistor V1 and the other end of the resistor R10 are grounded; the drain of the MOS transistor V1 is connected to the 2-pin of the opto-isolator D2, the 1-pin of the opto-isolator D2 is connected to the power supply terminal through the resistor R9, the 3-pin of the opto-isolator D2 is grounded, the 4-pin of the opto-isolator D2 is connected to the MOS transistor driving unit, and the 4-pin of the opto-isolator D2 is respectively connected to the power MOS transistor, the current limiting protection unit, and the MOS transistor driving unit through the resistor R8; the signal conditioning and isolation unit realizes the function of isolating DC signals through the capacitor C2, the resistor R10, and the MOS transistor V1, and the resistor R9, the opto-isolator D2, and the resistor R8 transfer the PWM signal generated by the weak electrical system to the strong electrical system in the form of opto-coupling, meeting the electrical isolation between the weak electrical system and the strong electrical system; the signal conditioning and isolation unit conditions the PWM signal output by the processor unit, that is, the modulation signal, and electrically isolates the weak electrical system where the processor unit is located from the strong electrical system where the AC line interface, the rectification unit, the MOS transistor driving unit, the power MOS transistor, the current limiting protection unit, and the overvoltage protection unit are located; when the PWM signal output by the processor D1 changes from low level to high level, the capacitor C2 charges, the gate voltage of the MOS transistor V1 rises, and when the voltage difference between the gate and the source of the MOS transistor V1 is greater than the conduction voltage of the MOS transistor V1, the drain and the source of the MOS transistor V1 conduct, and then the voltage across both sides of the light-emitting diode inside the opto-isolator D2 is greater than the conduction voltage, the light-emitting diode inside the opto-isolator D2 emits light, and the collector and the emitter of the phototransistor inside the opto-isolator D2 conduct; when the PWM signal is already at a stable high level, due to the existence of the bleeder resistor R10, the voltage between the gate and the source of the MOS transistor V1 will slowly drop below the conduction voltage of the MOS transistor V1, the light-emitting diode inside the opto-isolator D2 turns off, avoiding the burnout of the subsequent power MOS transistor Q1 and the current limiting resistor R6 when the PWM signal remains high for a long time due to abnormal operation of the processor; when the PWM signal output by the processor D1 changes from high level to low level, the capacitor C2 discharges, the gate voltage of the MOS transistor V1 drops, and when the voltage difference between the gate and the source of the MOS transistor V1 is less than the conduction voltage of the MOS transistor V1, the drain and the source of the MOS transistor V1 turn off, and then the voltage across both sides of the light-emitting diode inside the opto-isolator D2 is less than the conduction voltage, the light-emitting diode inside the opto-isolator D2 stops emitting light, and the collector and the emitter of the phototransistor inside the opto-isolator D2 are open.

[0041] Specifically, in this embodiment, the MOS transistor driving unit includes a switching chip D3, a resistor R7, a capacitor C1, a zener diode VD1, a resistor R3, and a resistor R2; pins 1, 2, and 4 of the switching chip D3 are grounded; pins 3 and 8 of the switching chip D3 are connected to the resistor R7, and the other end of the resistor R7 is respectively connected to the signal conditioning and isolation unit, the power MOS transistor, and the current limiting and protection unit, and the capacitor C1. The other end of the capacitor C1 is respectively connected to the zener diode VD1 and the ground terminal, the other end of the zener diode VD1 is respectively connected to the power MOS transistor and the current limiting and protection unit and the resistor R3, and the other end of the resistor R3 is connected to the rectifying unit through the resistor R2; pins 6 and 7 of the switching chip D3 are connected to the power MOS transistor and the current limiting and protection unit; pin 5 of the switching chip D3 is connected to the signal conditioning and isolation unit; in the present invention, the switching chip D3 uses a switching chip of model ETA7000, which is not specifically limited in the present invention and can be specifically set according to needs; the MOS transistor driving circuit drives the on and off of the power MOS transistor according to the PWM signal output by the signal conditioning and isolation unit; pins 1, 2, and 4 of the switching chip D3 are the same network inside and are connected to the reference ground of the high-voltage system; pins 3 and 8 of the switching chip D3 are the same network inside and are connected to one end of the current limiting resistor R7; pin 5 of the switching chip D3 is the switch control pin; pins 6 and 7 of the switching chip D3 are the same network inside and are connected to one end of the current limiting resistor R6; an internal switch is built in between pins 1, 2, 4 and 6, 7 of the switching chip D3, and the internal switch is controlled by the level of pin 5 of the switching chip D3; when the voltage between pin 5 of the switching chip D3 and its pins 1, 2, 4 is less than the threshold, the internal switch presents a low resistance; when the voltage between pin 5 of the switching chip D3 and its pins 1, 2, 4 is greater than the threshold, the internal switch presents a high resistance; the resistors R2 and R3 are current limiting resistors, and the resistors R2, R3, and the zener diode VD1 provide a gate voltage for the power MOS transistor Q1. The internal switch of the switching chip D3 cooperates with the gate voltage of the power MOS transistor Q1 to control the on and off between the source and drain of the power MOS transistor Q1.

[0042] Specifically, in this embodiment, the power MOS transistor and the current limiting protection unit include MOS transistor Q1 and resistor R6; the drain of MOS transistor Q1 is connected to the rectification unit, the source of MOS transistor Q1 is respectively connected to the signal conditioning and isolation unit, resistor R7, resistor R6 and capacitor C1. Capacitor C1 is a filtering and energy storage capacitor. The other end of resistor R6 is connected to pins 6 and 7 of switch chip D3, that is, connected to the built-in switch of switch chip D3. The gate of MOS transistor Q1 is respectively connected to the MOS transistor driving unit and the overvoltage protection unit; the power MOS transistor and the current limiting protection unit perform on-off operations on the pulsating direct current converted from AC 220V according to the control signal output by the MOS transistor driving unit, and limit the current passing through power MOS transistor Q1 through the series-connected resistor R6; Resistor R6 is a current limiting resistor, and resistor R6 and the built-in switch of switch chip D3 form a series circuit; when the built-in switch is closed, the pulsating direct current forms a current through the drain and source of power MOS transistor Q1, resistor R6 and the built-in switch of switch chip D3; when the built-in switch is opened, power MOS transistor Q1 and resistor R6 cannot form a loop, and the pulsating direct current will not form a current; during the period when the pulsating direct current forms a current, the magnitude of the current between the drain and source of power MOS transistor Q1 is related to the magnitude of the voltage difference between the gate and the source. The gate voltage is determined by VD1, and the source voltage is determined by the magnitude of the current flowing through resistor R6. In the actual operation process, the device parameters can be selected to accurately control the magnitude of the current between the drain and source of power MOS transistor Q1, so as to achieve the effect of constant current.

[0043] Specifically, in this embodiment, the overvoltage protection unit is used to monitor the instantaneous voltage value of the pulsating direct current in real time. When the instantaneous voltage value exceeds the preset level, the power MOS transistor is immediately turned off. The overvoltage protection unit includes a voltage regulator U1, a resistor R4, and a resistor R5. The pin 1 of the voltage regulator U1 is connected to the power MOS transistor and the current limiting protection unit. The pin 2 of the voltage regulator U1 is respectively connected to the resistor R4 and the resistor R5. The other end of the resistor R4 is connected to the resistor R2. The other end of the resistor R2 is connected to the rectification unit. The pin 3 of the voltage regulator U1 and the other end of the resistor R5 are grounded. The resistor R4 and the resistor R5 are voltage dividing resistors. The voltage regulator U1 is a three-terminal adjustable shunt voltage regulator. The pin 1 of the voltage regulator U1 is the cathode of the built-in Zener diode. When the reference voltage is higher than the threshold, the built-in Zener diode conducts reversely, and the voltage difference between the anode and the cathode is very small. When the reference voltage is lower than the threshold, the built-in Zener diode is reversely cut off, and the impedance of the cathode to the anode is very large, equivalent to an open circuit. The pin 2 of the voltage regulator U1 is the enable pin. The pin 3 of the voltage regulator U1 is the anode of the built-in Zener diode, which is connected to the strong electrical system ground. The resistor R5, the resistor R4, and the resistor R2 of the MOS transistor driving unit form a voltage dividing network, and its resistance value satisfies that when the strong electrical input is overvoltage, the voltage input to the enable pin of the voltage regulator U1 is higher than the reverse conduction starting threshold of the built-in Zener diode of the voltage regulator U1. When the strong electrical input voltage is within the normal range, the voltage input to the enable pin of the voltage regulator U1 is lower than the reverse conduction starting threshold of the built-in Zener diode of the voltage regulator U1. When the voltage of the enable pin of the voltage regulator U1 is lower than its starting threshold, the resistance value between the two ends of the built-in Zener diode of the voltage regulator U1 is very large, which does not affect the normal on-off operation of the power MOS transistor Q1. When the voltage of the enable pin of the voltage regulator U1 is higher than its starting threshold, the current passing through the two ends of the built-in Zener diode of the voltage regulator U1 is very large, and the voltage between the drain and the source of the power MOS transistor Q1 is pulled down below the level of turning off the drain and the source, achieving the purpose of turning off the power MOS transistor Q1. By selecting the resistance values of the resistor R2, the resistor R4, and the resistor R5, and the voltage regulator U1 with a suitable starting threshold, overvoltage protection of the power MOS transistor is achieved, and further protection of the current limiting resistor and the rectification circuit unit is achieved. The parameters of each circuit component of the present utility model are not specifically limited and can be set according to needs. Through the overvoltage protection unit, the power MOS transistor can be timely turned off, avoiding the burnout of the power MOS transistor and / or the resistor R6 due to the weak high-voltage impact resistance of the power MOS transistor and the current limiting protection unit.

[0044] Specifically, in this embodiment, the processor unit is used to output a pulse width modulation signal, that is, a PWM signal, with a specific frequency, duty cycle, and duration at a specific moment according to a prefabricated program or an instruction sent by the communication unit; the processor unit includes a processor D1, a crystal oscillator XL1, a capacitor C3, and a capacitor C4; the 11th pin of the processor D1 is connected to the signal conditioning and isolation unit to output the PWM signal, with the high level close to the DC power supply voltage and the low level close to the reference ground voltage of the weak power system; the 13th pin of the processor D1 is connected to the power supply terminal; the 33rd pin of the processor D1 is respectively connected to the capacitor C3 and the 2nd pin of the crystal oscillator XL1, the 1st pin of the crystal oscillator XL1 is respectively connected to the capacitor C4 and the 34th pin of the processor D1, and the 3rd and 4th pins of the crystal oscillator XL1 and the other ends of the capacitor C3 and the capacitor C4 are grounded; the 53rd pin of the processor D1 is grounded; in the present utility model, the processor D1 uses a processor chip of model WTZ13 with an in-built power line carrier communication function, which is not specifically limited in the present utility model and can be specifically set according to needs; the 13th pin of the processor D1 is connected to the 3.3V DC input of the weak power system, and the crystal oscillator XL1, the capacitor C3, and the capacitor C4 form a clock circuit, and the clock circuit provides an external clock for the processor unit. After frequency division processing, it becomes a control signal for the coordinated operation of each unit of the processor. Without the clock circuit generating a clock to drive the processor D1, the work cannot be completed.

[0045] Specifically, in this embodiment, the communication unit is an optional unit, and the communication unit is used to receive the characteristic current parameters and the sending moment sent by the master station and transmit the characteristic current parameters and the sending moment to the processor unit.

[0046] Specifically, in this embodiment, the method for generating the characteristic current system of the square wave envelope is specifically as follows:

[0047] S1. The processor unit outputs a modulation signal with a specific frequency, duty cycle, and duration according to an instruction; the instruction is a control instruction for outputting a modulation signal sent by a pre-set program or the communication unit;

[0048] S2. The signal conditioning and isolation unit receives the modulation signal and performs a conversion from weak electricity to strong electricity, and outputs a converted modulation signal;

[0049] S3. The MOS transistor driving unit transmits the converted modulation signal to the power MOS transistor and the current limiting and protection unit, and drives the power MOS transistor of the power MOS transistor and the current limiting and protection unit;

[0050] S4. The power MOS transistor and the current limiting and protection unit process the converted modulation signal and generate a characteristic current signal with a square wave envelope that can change periodically on the power distribution network power line;

[0051] S5. The rectifying unit converts the AC 220V power supply of the distribution network AC system into pulsating DC power supply for the power MOS transistor, current limiting protection unit, overvoltage protection unit and MOS transistor driving unit; and converts and transmits the characteristic current signal generated by the power MOS transistor and current limiting protection unit to the distribution network AC system.

[0052] S6. The overvoltage protection unit monitors the instantaneous voltage value of the pulsating DC output by the rectifying unit in real time and regulates the turn-off of the power MOS transistor in real time; if the instantaneous voltage value of the pulsating DC exceeds the preset level, the power MOS transistor is immediately turned off; if the instantaneous voltage value of the pulsating DC does not exceed the preset level, it has no effect on the characteristic current signal.

[0053] Specifically, in this embodiment, the processor unit outputs a modulation signal, which is a PWM pulse weak electrical signal. When the PWM pulse weak electrical signal rises to a high level, the DC blocking capacitor C2 of the signal conditioning and isolation unit is charged, the MOS transistor V1 is turned on, the built-in light-emitting diode of the optocoupler D2 emits light, and the collector and emitter of the built-in photosensitive triode are turned on. The voltage of pin 5 of the switch chip D3, that is, the enable pin, drops, and the built-in switch presents a low resistance state, and the drain and source of the power MOS transistor Q1 are turned on, generating a current signal in the distribution network through the rectifying unit; when the PWM pulse weak electrical signal drops from a high level to a low level, the DC blocking capacitor C2 of the signal conditioning and isolation unit discharges, the MOS transistor V1 is turned off, the built-in light-emitting diode of the optocoupler D2 stops emitting light, and the collector and emitter of the built-in photosensitive triode are turned off. The voltage of pin 5 of the switch chip D3, that is, the enable pin, rises, and the built-in switch presents a high resistance state, and the drain and source of the power MOS transistor Q1 are turned off, stopping the generation of the current signal; the voltage regulator U1 monitors the pulsating DC power supply voltage in real time through the voltage dividing network composed of the resistor R2, resistor R4 and resistor R5. If the instantaneous voltage value of the pulsating DC exceeds the preset level, the built-in Zener diode of the voltage regulator U1 conducts reversely, reducing the voltage difference between the gate and source of the power MOS transistor Q1 below the conduction threshold, and the power MOS transistor Q1 is turned off, thereby preventing the power MOS transistor Q1 and the current limiting resistor R6 from being damaged; if the instantaneous voltage value of the pulsating DC is lower than the preset level, the built-in Zener diode of the voltage regulator U1 is reversely cut off, and the impedance of the cathode to the anode is very large, that is, equivalent to an open circuit, and it has no effect on the generation of the characteristic current signal.

[0054] The above is only the preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structural transformation made under the inventive concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied to other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A characteristic current generating system of a square wave envelope, characterized in that: include: Overvoltage protection unit, power MOS tube and current limiting protection unit, rectifier unit, MOS tube drive unit, signal conditioning and isolation unit, processor unit and communication unit; The rectifier unit is electrically connected to the AC system of the distribution network, the power MOS tube and the current limiting protection unit through wires, and the rectifier unit is electrically connected to the MOS tube drive unit and the overvoltage protection unit through wires; the overvoltage protection unit is electrically connected to the power MOS tube and the current limiting protection unit through wires; the communication unit, the processor unit, the signal conditioning and isolation unit, the MOS tube drive unit, the power MOS tube and the current limiting protection unit are electrically connected in sequence through wires.

2. A characteristic current generating system of a square wave envelope according to claim 1, characterized in that: The rectifier unit is electrically connected to the AC system of the power distribution network through an AC line interface; the AC line interface includes two contacts, a live wire and a neutral wire.

3. A square wave envelope characteristic current generating system according to claim 2, characterized in that: The rectifier unit includes a resistor R1 and a rectifier bridge BR1; One end of the resistor R1 is connected to the live wire of the AC line interface, the other end of the resistor R1 is connected to pin 2 of the rectifier bridge stack BR1, pin 1 of the rectifier bridge stack BR1 is connected to the neutral wire of the AC line interface, pin 3 of the rectifier bridge stack BR1 is respectively connected to the power MOS tube and the current limiting protection unit, the MOS tube driving unit and the overvoltage protection unit, and pin 4 of the rectifier bridge stack BR1 is grounded.

4. The characteristic current generating system of a square wave envelope according to claim 3, characterized in that: The rectifier bridge stack BR1 includes a diode E1, a diode E2, a diode E3 and a diode E4; The anode of the diode E1 is respectively connected to the neutral line of the AC line interface and the cathode of the diode E2, the cathode of the diode E1 is respectively connected to the power MOS tube and the current limiting protection unit, the MOS tube driving unit, the overvoltage protection unit and the cathode of the diode E2, the anode of the diode E2 is respectively connected to the cathode of the diode E3 and the resistor R1, and the anode of the diode E3 is respectively connected to the anode of the diode E4 and the ground.

5. A square wave envelope characteristic current generating system according to any one of claims 1 to 4, characterized in that: The signal conditioning and isolation unit includes a capacitor C2, a MOS tube V1, a photoelectric isolator D2, a resistor R9 and a resistor R10; the gate of the MOS tube V1 is connected to the capacitor C2 and the resistor R10 respectively, and the other end of the capacitor C2 is connected to the processor unit; the source of the MOS tube V1 and the other end of the resistor R10 are grounded; the drain of the MOS tube V1 is connected to the 2nd pin of the photoelectric isolator D2, the 1st pin of the photoelectric isolator D2 is connected to the power supply terminal through the resistor R9, the 3rd pin of the photoelectric isolator D2 is grounded, and the 4th pin of the photoelectric isolator D2 is connected to the MOS tube driving unit.

6. A square wave envelope characteristic current generating system according to any one of claims 1 to 4, characterized in that: The MOS tube driving unit includes a switch chip D3, a resistor R7, a capacitor C1, a voltage regulator tube VD1, a resistor R3 and a resistor R2; Pins 1, 2, and 4 of the switch chip D3 are grounded; Pins 3 and 8 of the switch chip D3 are connected to the resistor R7, the other end of the resistor R7 is respectively connected to the signal conditioning and isolation unit, the power MOS tube, the current limiting protection unit and the capacitor C1, the other end of the capacitor C1 is respectively connected to the voltage regulator tube VD1 and the ground, the other end of the voltage regulator tube VD1 is respectively connected to the power MOS tube, the current limiting protection unit and the resistor R3, and the other end of the resistor R3 is connected to the rectifier unit through the resistor R2; Pins 6 and 7 of the switch chip D3 are connected to the power MOS tube and the current limiting protection unit; Pin 5 of the switch chip D3 is connected to the signal conditioning and isolation unit.

7. A square wave envelope characteristic current generating system according to claim 6, characterized in that: The power MOS tube and current limiting protection unit includes a MOS tube Q1 and a resistor R6; The drain of the MOS tube Q1 is connected to the rectifying unit, the source of the MOS tube Q1 is respectively connected to the signal conditioning and isolation unit, the resistor R7, the resistor R6 and the capacitor C1, the other end of the resistor R6 is connected to the 6th and 7th pins of the switch chip D3, and the gate of the MOS tube Q1 is respectively connected to the MOS tube driving unit and the overvoltage protection unit.

8. A square wave envelope characteristic current generating system according to any one of claims 1 to 4, characterized in that: The overvoltage protection unit includes a voltage regulator U1, a resistor R4 and a resistor R5; pin 1 of the voltage regulator U1 is connected to the power MOS tube and the current limiting protection unit, pin 2 of the voltage regulator U1 is connected to the resistor R4 and the resistor R5 respectively, the other end of the resistor R4 is connected to the rectifier unit, and pin 3 of the voltage regulator U1 and the other end of the resistor R5 are grounded.

9. A square wave envelope characteristic current generating system according to any one of claims 1 to 4, characterized in that: The processor unit includes a processor D1; Pin 11 of the processor D1 is connected to the signal conditioning and isolation unit; Pin 13 of the processor D1 is connected to the power supply terminal; Pins 33 and 34 of the processor D1 are connected to a clock circuit; Pin 53 of the processor D1 is grounded.

10. A square wave envelope characteristic current generating system according to claim 9, characterized in that: The clock circuit includes a crystal oscillator XL1, a capacitor C3 and a capacitor C4; Pin 1 of the crystal oscillator XL1 is connected to pin 34 of the processor D1 and capacitor C4 respectively, pin 2 of the crystal oscillator XL1 is connected to pin 33 of the processor D1 and capacitor C3 respectively, pin 3 of the crystal oscillator XL1, capacitor C4 and the other end of capacitor C3 are grounded, and pin 4 of the crystal oscillator XL1 is grounded.

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