SiC UMOSFET device capable of improving reverse follow current
By integrating diodes and introducing trench structures in SiC MOSFET devices, and using the design of Schottky metal layer and ohmic contact alloy layer, the shortcomings of traditional SiC MOSFET devices in reverse freewheeling function are solved, achieving better reverse recovery characteristics and lower freewheeling losses.
Patent Information
- Application Number
- CN202422072682.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-26
AI Technical Summary
Traditional SiC MOSFET devices have bipolar degradation effects and high turn-on voltages in reverse freewheeling function, resulting in high freewheeling losses and making it difficult to meet the needs of high-performance power management systems.
A dual-trench SiC UMOSFET device is designed to improve the reverse free flow capability by integrating diodes and introducing trench structures within the SiC MOSFET, and reduce free flow loss through the design of Schottky metal layer and ohmic contact alloy layer.
It achieves better reverse recovery characteristics, avoids bipolar degradation effects, and reduces the freewheeling loss of the device, and is suitable for high-performance power management systems.
Smart Images
Figure CN222967300U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC UMOSFET device for improving reverse freewheeling. Background Art
[0002] Due to the outstanding characteristics of SiC material, such as wide bandgap, high critical breakdown electric field strength, high thermal conductivity, and high saturated electron drift velocity, compared with Si material, it has better development prospects in the fields of high voltage, high power, high temperature, and high frequency. Compared with the planar gate structure, the trench-gate SiC MOSFET has a larger on-state current and is more popular in the power application field.
[0003] Since SiC MOSFET devices are often used in power management systems such as bridge circuits and inverter applications, there is a need for reverse freewheeling function. Therefore, its reverse recovery characteristic is an important index to evaluate its performance. However, in the application of traditional SiC MOSFETs, there is a bipolar degradation effect when using the parasitic PN junction body diode for freewheeling, and its relatively high turn-on voltage also leads to high freewheeling loss. Therefore, developing a double-trench SiC MOSFET device that can obtain better reverse recovery characteristics and avoid the bipolar degradation effect at the same time is an urgent technical problem to be solved in the current industry. Summary of the Utility Model
[0004] Aiming at the above problems, the utility model provides a double-trench SiC MOSFET device that can obtain better reverse recovery characteristics and avoid the bipolar degradation effect at the same time.
[0005] A SiC UMOSFET device for improving reverse freewheeling includes an N+ substrate layer, an N- epitaxial layer, and a front electrode metal layer arranged in sequence from bottom to top;
[0006] The N-epitaxial layer is provided with:
[0007] A PW region that extends downward from the top surface of the N-epitaxial layer and has a spacing from the bottom surface of the N-epitaxial layer; the PW region is divided into a middle PW region and several side PW regions by a plurality of gate trench regions; the bottom of the gate trench region is lower than the bottom surface of the PW region;
[0008] A P+ region, including a first P+ region and a second P+ region;
[0009] Among them, the first P+ region extends downward from the middle of the top surface of the middle PW region and has a spacing from the side of the middle PW region;
[0010] Among them, the second P+ region extends downward from the side of the top surface of the side PW region;
[0011] The N+ region includes a first N+ region and a second N+ region;
[0012] Among them, the first N+ region extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region; there is a spacing between the bottom surface of the first N+ region and the bottom surface of the middle PW region;
[0013] Among them, the second N+ region extends downward from the middle of the top surface of the side PW region;
[0014] The ohmic contact alloy is disposed on the side wall of the source trench region in the middle of the first P+ region;
[0015] The gate oxide layer is formed on the side wall and the bottom of the gate trench region;
[0016] The Poly layer is filled in the gate trench region and is connected to the gate oxide layer;
[0017] An isolation dielectric layer, an ohmic contact alloy layer, a Schottky metal layer, and a front electrode metal layer are provided on the N-epitaxial layer.
[0018] The isolation dielectric layer is formed on the N-epitaxial layer; the bottom surface of the isolation dielectric layer in the middle region is respectively connected to the Poly layer, the gate oxide layer, the first N+ region, and the second P+ region; the bottom surface of the isolation dielectric layer near the edge region is respectively connected to the Poly layer, the gate oxide layer, and the second P+ region.
[0019] Specifically, the ohmic contact alloy layer is formed on the top surfaces of the first P+ region and the first N+ region, and its side is connected to the isolation dielectric layer.
[0020] Specifically, the Schottky metal layer is formed on the top surfaces of the second P+ region and the second N+ region, and its side is connected to the isolation dielectric layer.
[0021] Specifically, the thickness of the Schottky metal layer is 60 nm.
[0022] Specifically, the implantation depths of the first P+ region and the second P+ region are respectively 0.8 - 1.5 μm.
[0023] Advantages of the present utility model:
[0024] By means of the technology of integrating a diode inside the SiC MOSFET, the reverse freewheeling ability of the device is improved. By introducing a trench structure in the source region, the peak electric field at the gate oxide layer is suppressed, and the reliability problem of the trench MOSFET gate oxide layer can be improved. Description of the Drawings
[0025] Figure 1 is the structural diagram of step S100 of the present utility model;
[0026] Figure 2 It is the structural diagram of step S200 of the present utility model;
[0027] Figure 3 It is the structural diagram of step S300 of the present utility model;
[0028] Figure 4 It is the structural diagram of step S400 of the present utility model;
[0029] Figure 5 It is the structural diagram of step S500 of the present utility model;
[0030] Figure 6 It is the structural diagram of step S600 of the present utility model;
[0031] Figure 7 It is the structural diagram of step S700 of the present utility model;
[0032] Figure 8 It is the structural diagram of step S800 of the present utility model;
[0033] Figure 9 It is the structural diagram of step S900 of the present utility model;
[0034] Figure 10 It is the structural diagram of step S1000 of the present utility model;
[0035] Figure 11 It is the structural diagram of step S1100 of the present utility model;
[0036] Figure 12 It is the structural diagram of step S1200 of the present utility model;
[0037] Figure 13 It is the structural diagram of step S1300 of the present utility model;
[0038] In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the PW region, 4 is the gate trench region, 5 and 5' are the P+ regions, 6 and 6' are the N+ regions, 7 is the source trench region, 8 is the ohmic contact alloy, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the ohmic contact alloy layer, 13 is the Schottky metal layer, and 14 is the front electrode metal layer. Detailed implementation manners
[0039] The present utility model will be described in detail below in combination with specific implementation cases. The examples of the embodiments are shown in the drawings, and the illustrative implementation manners and descriptions of the present utility model are only used to explain the present utility model and do not constitute a limitation to the present utility model.
[0040] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation and positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "plurality" is two or more.
[0041] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0042] A preparation method of a SiC UMOSFET device for improving reverse freewheeling includes the following steps:
[0043] S100, referring to Figure 1 as shown, an N-epitaxial layer 2 is epitaxially grown on an N+ substrate layer 1 and then cleaned and dried;
[0044] S200, referring to Figure 2 as shown, using SiO 2 as a mask for ion implantation, a PW region 3 is formed in the N-epitaxial layer 2 by implanting Al ions; the concentration range of the PW region 3 is 1E 17 cm -2 -1E 18 cm -2 , and the implantation depth is 0.8 - 1.5 um.
[0045] S300, referring to Figure 3 as shown, using plasma etching technology to etch the N-epitaxial layer 2 to form a plurality of gate trench regions 4, and the etching depth is 1 - 1.8 um;
[0046] S400, as Figure 4 shown, using SiO 2 as a mask, implanting Al ions into the PW region 3 multiple times to form a first P+ region 5 and a second P+ region 5'; it can simultaneously serve as a reverse voltage withstand shielding layer and a source contact P+ region. The concentration range of the first P+ region 5 and the second P+ region 5' is 1E 18 cm -2 -1E 19 cm -2, the implantation depth is 0.8 - 1.5 um, and the mask is removed after implantation; the implantation depths of the first P+ region 5 and the second P+ region 5' are the same as that of the PW region 3.
[0047] S500, as Figure 5 shown, using SiO 2 as a mask, N ions are implanted multiple times in the PW region 3 to form the first N+ region 6 and the second N+ region 6', which serve as the source contact N+ region and the N+ region for Schottky contact during reverse freewheeling respectively, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , and the mask is removed after implantation; subsequently, a thin graphite layer is deposited on the device surface for protection, and annealing is performed at a high temperature of 1650 °C - 1690 °C for 15 min to activate the implanted ions;
[0048] Among them, the implantation depth of the first N+ region 6 is 0.4 - 0.8 um, and the implantation depth of the second N+ region 6' is 0.8 - 1.5 um. The PW region 3, the P+ region 5, and the first N+ region 6 are at the same potential, which can enhance the breakdown voltage and short - circuit tolerance of the device.
[0049] The N+ region in step S500 is divided into two parts: one part is the first N+ region 6 above the inversion layer, which is in contact with the source electrode and is used for forward conduction of current. The implantation depth of the N+ region in this part is only half of that of the PW region 3; the other part is the second N+ region 6' below the Schottky metal layer 13, which is used for reverse freewheeling, and the implantation depth of the N+ region in this part is the same as that of the PW region 3.
[0050] S600, as Figure 6 shown, etch the source trench region 7 on the first P+ region 5, and the etching depth is 0.4 - 0.9 um;
[0051] The depth of the source trench region 7 in step S600 is 0.5 - 0.6 times the implantation depth of the PW region 3, which can reduce the on - resistance while enhancing the breakdown voltage performance of the device.
[0052] S700, as Figure 7 shown, deposit ohmic metal on the sidewalls of the source trench region 7 by Ni metal sputtering, and then anneal at a high temperature of 1000 °C for 5 min to form the ohmic contact alloy 8, which forms an ohmic contact with the P+ regions on both sides of the source trench;
[0053] S800, as Figure 8 shown, deposit a layer of gate oxide layer 9 on the sidewalls and bottom of the gate trench region 4 using the LPCVD method;
[0054] The thickness of the gate oxide layer 9 in step S800 is 60 nm - 70 nm, further improving the robustness of the gate oxide layer.
[0055] S900, refer to Figure 9 As shown, deposit polysilicon in the gate trench region 4 by LPCVD method to form the Poly layer 10 as the gate electrode lead-out.
[0056] S1000, refer to Figure 10 As shown, form the isolation dielectric layer 11 on the N-epitaxial layer 2 by depositing an oxide.
[0057] Both ends of the isolation dielectric layer 11 in step S1000 are respectively placed on the upper ends of the second P+ region 5' and the first N+ region 6. The overlapping distance is not set and is adjusted according to the actual process conditions.
[0058] S1100, refer to Figure 11 As shown, form the ohmic metal layer by Ni metal sputtering deposition on the N-epitaxial layer 2, and then anneal at a high temperature of 1000 °C for 5 min to form the ohmic contact alloy layer 12, forming an ohmic contact with the upper parts of the first P+ region 5 and the first N+ region 6.
[0059] S1200, refer to Figure 12 As shown, deposit high-barrier Schottky metal particles with a thickness of 1 - 2 layers of particles on the N-epitaxial layer 2. The particles are relatively evenly dispersed on the SiC surface; then deposit a low-barrier Schottky metal layer, and then perform rapid annealing at a high temperature of 950 °C - 1050 °C for 5 min to form a Schottky metal layer 13 with a high and low barrier thickness of 60 nm, forming a Schottky contact with the upper parts of the second P+ region 5' and the second N+ region 6'.
[0060] The metal material of the high-barrier Schottky metal particle layer in step S1200 includes any one or any combination of Au, Ni, Pt, and Pd. The diameter of the nano-scale particles, and the deposition of the metal particles can be carried out by aerosol or sputtering. The metal of the low-barrier Schottky metal layer includes any one or any combination of Ti, Mo, and W. After rapid annealing treatment, it can not only improve the uniformity of the Schottky contact, but also make the high-barrier metal particles better embed in the low-barrier Schottky metal layer.
[0061] S1300, refer to Figure 13 As shown, form the front electrode metal layer 14 by Al metal sputtering above the isolation dielectric layer 11, the ohmic contact alloy layer 12, the Schottky metal layer 13 and in the source trench region 7 as the source electrode lead-out.
[0062] In step S1300, the front electrode metal layer 14 needs to fill the entire source trench region 7, and the ohmic contact alloy 8 on both side walls of the source trench region 7 is in contact with the front electrode metal layer 14Al.
[0063] Two metals with different high and low barriers form a Schottky metal contact layer. The high doping of the contact surface can increase the highest electric field on the semiconductor surface, thereby enhancing the mirror force and further reducing the metal barrier, reducing the forward conduction voltage drop of the diode, making it easier to achieve forward conduction in circuit applications, and reducing the freewheeling loss of the device.
[0064] A SiC UMOSFET device for improving reverse freewheeling includes an N+ substrate layer 1, an N- epitaxial layer 2, and a front electrode metal layer 14 arranged in sequence from bottom to top;
[0065] The N- epitaxial layer 2 is provided with:
[0066] A PW region 3, extending downward from the top surface of the N- epitaxial layer 2, having a spacing from the bottom surface of the N- epitaxial layer 2; the PW region 3 is divided into a middle PW region and several side PW regions by several gate trench regions 4; the bottom of the gate trench region 4 is lower than the bottom surface of the PW region 3;
[0067] A P+ region, including a first P+ region 5 and a second P+ region 5';
[0068] Among them, the first P+ region 5 extends downward from the middle of the top surface of the middle PW region, with a spacing from the side of the middle PW region;
[0069] Among them, the second P+ region 5' extends downward from the side of the top surface of the side PW region;
[0070] An N+ region, including a first N+ region 6 and a second N+ region 6';
[0071] Among them, the first N+ region 6 extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region 5; there is a spacing between the bottom surface of the first N+ region 6 and the bottom surface of the middle PW region;
[0072] Among them, the second N+ region 6' extends downward from the middle of the top surface of the side PW region;
[0073] An ohmic contact alloy 8 is arranged on the side wall of the source trench region 7 in the middle of the first P+ region 5;
[0074] A gate oxide layer 9 is formed on the side wall and the bottom of the gate trench region 4;
[0075] A Poly layer 10 is filled in the gate trench region 4 and is connected to the gate oxide layer 9;
[0076] An isolation dielectric layer 11, an ohmic contact alloy layer 12, a Schottky metal layer 13, and a front electrode metal layer 14 are provided on the N-epitaxial layer 2.
[0077] The isolation dielectric layer 11 is formed on the N-epitaxial layer 2; the bottom surface of the isolation dielectric layer 11 in the middle region is respectively connected to the Poly layer 10, the gate oxide layer 9, the first N+ region 6, and the second P+ region 5'; the bottom surface of the isolation dielectric layer 11 near the edge region is respectively connected to the Poly layer 10, the gate oxide layer 9, and the second P+ region 5'.
[0078] The ohmic contact alloy layer 12 is formed on the top surfaces of the first P+ region 5 and the first N+ region 6, and its side is connected to the isolation dielectric layer 11.
[0079] The Schottky metal layer 13 is formed on the top surfaces of the second P+ region 5' and the second N+ region 6', and its side is connected to the isolation dielectric layer 11.
[0080] The bottom of the front electrode metal layer 14 is respectively connected to the isolation dielectric layer 11, the Schottky metal layer 13, the ohmic contact alloy layer 12, the first P+ region 5, and the ohmic contact alloy 8.
[0081] The present utility model forms a Schottky metal contact layer by using two metals with different high and low barriers. The high doping of the contact surface increases the highest electric field on the semiconductor surface, thereby enhancing the mirror force and further reducing the metal barrier, reducing the forward conduction voltage drop of the diode, making it easier to achieve forward conduction in circuit applications, and reducing the freewheeling loss of the device. In addition, the trench structure in the source region can relieve the electric field concentrated at the gate oxide layer, improving the reliability of the gate oxide. Compared with externally connecting a fast recovery diode in parallel, the number of devices is reduced, and the packaging space in module applications is saved.
[0082] Regarding the content disclosed in this case, the following points need to be explained:
[0083] (1) The attached drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case, and other structures can be referred to as usual;
[0084] (2) Without conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments;
[0085] (3) The above is only the specific implementation manners disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.
Claims
1. A SiC UMOSFET device with improved reverse freewheeling, characterized in that: It comprises an N+ substrate layer (1), an N- epitaxial layer (2) and a front electrode metal layer (14) which are arranged in sequence from bottom to top; The N-epitaxial layer (2) is provided with: A PW region (3) extending downward from the top surface of the N-epitaxial layer (2); the PW region (3) is divided into a middle PW region and a plurality of side PW regions by a plurality of gate trench regions (4); P+ region, including a first P+ region (5) and a second P+ region (5'); The first P+ region (5) extends downward from the middle of the top surface of the middle PW region, and a gap is provided between the side and the side of the middle PW region; Wherein, the second P+ region (5') extends downward from the top side of the side PW region; N+ region, including a first N+ region (6) and a second N+ region (6'); The first N+ region (6) extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region (5); a gap is provided between the bottom surface of the first N+ region (6) and the bottom surface of the middle PW region; Wherein, the second N+ region (6') extends downward from the middle of the top surface of the side PW region; An ohmic contact alloy (8) is arranged on the side wall of the source trench region (7) in the middle of the first P+ region (5); A gate oxide layer (9) formed on the sidewalls and bottom of the gate trench region (4); A Poly layer (10) filled in the gate trench region (4) and connected to the gate oxide layer (9); An isolation dielectric layer (11), an ohmic contact alloy layer (12), a Schottky metal layer (13) and a front electrode metal layer (14) are provided on the N-epitaxial layer (2).
2. A SiC UMOSFET device with improved reverse freewheeling according to claim 1, characterized in that: The isolation dielectric layer (11) is formed on the N-epitaxial layer (2); the bottom surface of the isolation dielectric layer (11) in the middle region is respectively connected to the Poly layer (10), the gate oxide layer (9), the first N+ region (6) and the second P+ region (5'); and the bottom surface of the isolation dielectric layer (11) near the edge region is respectively connected to the Poly layer (10), the gate oxide layer (9) and the second P+ region (5').
3. A SiC UMOSFET device with improved reverse freewheeling according to claim 1, characterized in that: The ohmic contact alloy layer (12) is formed on the top surfaces of the first P+ region (5) and the first N+ region (6), and its side is connected to the isolation dielectric layer (11).
4. A SiC UMOSFET device with improved reverse freewheeling according to claim 1, characterized in that: The Schottky metal layer (13) is formed on the top surfaces of the second P+ region (5') and the second N+ region (6'), and the side portions are connected to the isolation dielectric layer (11).
5. A SiC UMOSFET device with improved reverse freewheeling according to claim 1, characterized in that: The Schottky metal layer (13) has a thickness of 60 nm.
6. A SiC UMOSFET device with improved reverse freewheeling according to claim 1, characterized in that: The implantation depths of the first P+ region (5) and the second P+ region (5') are respectively 0.8-1.5 um.