SiCUMOSFET device capable of improving short-circuit voltage resistance
By introducing the trench structure and injecting the P+ and N+ regions into the source region of the SiCUMOSFET device, a PN junction is formed to deplete the current channel and suppressing the peak electric field of the gate oxide layer, the voltage withstand the SiCMOSFET device during short circuit is solved, and the device's short-circuit withstandability and avalanche ability are improved.
Patent Information
- Application Number
- CN202422072734.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-26
AI Technical Summary
SiCMOSFET devices are prone to short-circuit failure when short-circuited. The instantaneous high voltage and high current lead to the short-circuit failure of the device, and it is easy to overshoot the drain-source voltage during the shutdown process, resulting in avalanche breakdown and performance degradation.
A SiCUMOSFET device that improves the short-circuit withstand voltage is designed. By introducing a trench structure in the source region, multiple gate trench regions are arranged, and P+ and N+ regions are injected to form a PN junction to deplete the current channel and suppress the peak electric field at the gate oxide layer.
It effectively reduces the saturation current during short circuit of the device, improves the short circuit withstandability and avalanche ability, improves the reliability of the gate oxide layer, and extends the service life of the device.
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Figure CN222967309U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC UMOSFET device with improved short-circuit breakdown voltage resistance. Background Art
[0002] As a representative of the third-generation semiconductor materials, silicon carbide devices have gradually become an indispensable mainstream product in the field of power electronics. Their characteristics such as wide bandgap and high thermal conductivity play an important role in reducing the thermal resistance of power devices, increasing the breakdown voltage, and increasing the current density of devices.
[0003] The extremely fast switching speed of SiC MOSFET makes it extremely easy to generate overshoot of drain-source voltage during the turn-off process of the device. Especially in applications such as 800V electric drive systems, it is easy to cause short-term avalanche breakdown of SiC MOSFET devices, forming extremely large electrothermal stress near the gate oxide of SiC MOSFET. During long-term use, it is easy to cause device performance degradation or even damage; in addition, when a short circuit occurs in the electric drive system, SiC MOSFET will have a short-circuit fault, and the instantaneous high voltage and large current are extremely likely to cause the device to short-circuit and fail. Summary of the Utility Model
[0004] The utility model designs a SiC UMOSFET device with improved short-circuit breakdown voltage resistance, effectively reducing the saturation current during device short-circuit, improving the short-circuit tolerance and avalanche ability, and suppressing the peak electric field at the gate oxide layer by introducing a trench structure in the source region, which can improve the reliability problem of the trench MOSFET gate oxide layer.
[0005] The technical solution of the utility model is as follows:
[0006] A SiC UMOSFET device with improved short-circuit breakdown voltage resistance, including an N+ substrate layer, an N- epitaxial layer, a PW region, and a front electrode metal layer arranged in sequence from bottom to top;
[0007] The PW region is divided into several regions by the arrangement of a plurality of gate trench regions;
[0008] On each region of the PW region, there are provided:
[0009] A P+ region extending downward from the middle of the top surface of the PW region;
[0010] An N+ region extending downward from the top surface of the PW region along the side of the P+ region;
[0011] An ohmic contact alloy provided on the inner sidewall of the source trench region in the P+ region;
[0012] An oxide layer is provided on the inner sidewall and the bottom of the gate trench region; the bottom surface of the oxide layer is lower than the bottom surface of the PW region; the gate trench region is filled with a Poly layer on the oxide layer;
[0013] A plurality of spaced isolation dielectric layers are provided on the PW region; the bottom surfaces of the isolation dielectric layers are respectively connected to the N+ region, the oxide layer and the Poly layer;
[0014] An ohmic contact alloy layer is provided on the side of the isolation dielectric layer and is connected thereto; the bottom surface of the ohmic contact alloy layer is respectively connected to the N+ region and the P+ region.
[0015] Specifically, the depth of the gate trench region is 1 - 1.8 um.
[0016] Specifically, the depth of the P+ region is the same as the depth of the PW region (3).
[0017] Specifically, the depth of the N+ region is 0.4 - 0.8 um.
[0018] Specifically, the depth of the source trench region is 0.4 - 0.9 um.
[0019] Advantages of the present utility model:
[0020] Improve the short - circuit tolerance of the device:
[0021] 1. When a short - circuit occurs in the SiCMOSFET, a higher drain - source voltage will cause a large saturation current to flow through the device, resulting in heat accumulation, and then leading to performance degradation or even failure of the device. The PN junction of the P+ region and the N+ region implanted in the epitaxial layer in the structure of the present utility model can deplete the current channel to a great extent, greatly reduce the saturation current when the device has a short - circuit, thereby effectively reducing the internal heat generation and heat accumulation when the device has a short - circuit, and improving the short - circuit tolerance of the device.
[0022] 2. Reduce the on - resistance of the device:
[0023] The on - resistance between the drain and the source of the SiCMOSFET in the on - state directly affects the power consumption and temperature of the device; the smaller the on - resistance, the smaller the power loss when the device is working. Therefore, reducing the on - loss is a research hotspot in the development of power devices. The PW regions on both sides of the gate of the present utility model are lightly doped, which can reduce the channel resistance of the device and reduce the device loss. At the same time, the P+ implanted in the PW region as a shielding structure can further improve the avalanche ability of the device.
[0024] 3. Improve the gate oxide reliability of the device:
[0025] When fabricating a trench MOSFET structure, a stronger breakdown electric field will lead to a reduction in the breakdown voltage withstand performance of the gate oxide at the bottom of the trench. By introducing a trench structure into the source region in the present utility model, the peak electric field at the gate oxide layer is suppressed, and the reliability problem of the trench MOSFET gate oxide layer is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a cross-sectional schematic view of the preparation of the N-epitaxial layer;
[0027] Figure 2 is a cross-sectional schematic view of the preparation of the PW region;
[0028] Figure 3 is a cross-sectional schematic view of the preparation of the gate trench region;
[0029] Figure 4 is a cross-sectional schematic view of the preparation of the P+ region;
[0030] Figure 5 is a cross-sectional schematic view of the preparation of the N+ region;
[0031] Figure 6 is a cross-sectional schematic view of the preparation of the source trench region;
[0032] Figure 7 is a cross-sectional schematic view of the preparation of the ohmic contact alloy;
[0033] Figure 8 is a cross-sectional schematic view of the preparation of the gate oxide layer;
[0034] Figure 9 is a cross-sectional schematic view of the preparation of the Poly layer;
[0035] Figure 10 is a cross-sectional schematic view of the preparation of the isolation dielectric layer;
[0036] Figure 11 is a cross-sectional schematic view of the preparation of the ohmic contact alloy layer;
[0037] Figure 12 is a cross-sectional schematic view of the preparation of the front electrode metal;
[0038] In the figure, 1 is the N+ substrate layer, 2 is the N-epitaxial layer, 3 is the PW region, 4 is the gate trench region, 5 is the P+ region, 6 is the N+ region, 7 is the source trench region, 8 is the ohmic contact alloy, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the ohmic contact alloy layer, and 13 is the front electrode metal layer. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0039] The present utility model will be described in detail below in conjunction with specific implementation cases. Examples of the embodiments are shown in the accompanying drawings. The schematic embodiments and descriptions thereof of the present utility model are only used to explain the present utility model and are not intended to limit the present utility model.
[0040] A method for fabricating a SiC UMOSFET device with improved short-circuit withstand voltage includes the following steps:
[0041] S100, referring to Figure 1 as shown, an N-epitaxial layer 2 is epitaxially grown on an N+ substrate layer 1; and a lightly doped PW region 3 is formed on the N-epitaxial layer 2 by Al ion implantation, as Figure 2 shown;
[0042] The doping concentration range of the PW region 3 is 1E 17 cm -2 -1E 18 cm -2 , and the doping depth is 0.8 - 1.5 um.
[0043] S200, referring to Figure 3 as shown, a gate trench region 4 extending below the PW region 3 is formed on the PW region 3 by etching;
[0044] Specifically, the depth of the gate trench region 4 is 1 - 1.8 um.
[0045] S300, referring to Figure 4 as shown, a P+ region 5 is formed by multiple Al ion implantations in the middle of the top surface of the PW region 3;
[0046] The concentration range of the P+ region 5 is 1E 18 cm -2 -1E 19 cm -2 ; the implantation depth of the P+ region 5 is the same as that of the PW region 3, that is, the implantation depth of the P+ region 5 is 0.8 - 1.5 um.
[0047] S400, referring to Figure 5 as shown, in the PW region 3, N+ regions 6 are formed by multiple N ion implantations on both sides of the P+ region 5;
[0048] The concentration range of the N+ regions 6 is 1E 18 cm -2 -5E 18 cm -2 , the implantation depth is 0.4 - 0.8 um, then a carbon film is deposited on the surface of the device, annealed at a high temperature of 1650 °C - 1690 °C for 15 min to activate the implanted ions, and then the carbon film is removed; wherein the side parts of the N+ regions 6 are connected to the P+ region 5, and the implantation depth is less than that of the P+ region 5.
[0049] S500, as shown in the reference Figure 6 As shown, a source trench region 7 is formed by etching on the P+ region 5;
[0050] The bottom of the source trench region 7 is higher than the bottom surface of the P+ region 5. In this case, the depth of the source trench region 7 is 0.4 - 0.9 um.
[0051] The depth of the source trench region 7 in step S500 is 0.5 - 0.6 times the implantation depth of the P+ region 5, which can reduce the on-resistance and improve the breakdown voltage of the device at the same time.
[0052] S600, as shown in the reference Figure 7 As shown, an ohmic metal is deposited on the inner sidewalls of the source trench region 7 by Ni metal sputtering, and then annealed at a high temperature of 1000 °C for 5 minutes to form an ohmic contact alloy 8, which forms an ohmic contact with the P+ region 5;
[0053] The ohmic contact alloy 8 in step S600 is only deposited on the two sidewalls of the source trench region 7, which is beneficial to the freewheeling of the device.
[0054] S700, as shown in the reference Figure 8 As shown, a gate oxide layer 9 is deposited on the sidewalls and bottom of the gate trench region 4 by LPCVD method;
[0055] The thickness of the gate oxide layer 9 in step S700 is 60 nm - 70 nm, which further improves the robustness of the gate oxide layer.
[0056] S800, as shown in the reference Figure 9 As shown, polysilicon is deposited in the gate trench region 4 by LPCVD method to form a Poly layer 10 as the gate electrode lead-out;
[0057] S900, as shown in the reference Figure 10 As shown, an isolation dielectric layer 11 is formed on the N-epitaxial layer 2 by depositing an oxide;
[0058] Both sides of the isolation dielectric layer 11 in the middle region are respectively placed on the upper ends of the two N+ regions 6, and the overlapping distance is not set and adjusted according to the actual process conditions.
[0059] S1000, as shown in the reference Figure 11 As shown, an ohmic metal layer is deposited on the side of the isolation dielectric layer 11 by Ni metal sputtering, and then annealed at a high temperature of 1000 °C for 5 minutes to form an ohmic contact alloy layer 12, which forms an ohmic contact with the upper parts of the P+ region 5 and the N+ region 6;
[0060] S1100, as shown in the reference Figure 12As shown, a front electrode metal layer 13 is formed above the isolation dielectric layer 11 and the ohmic contact alloy layer 12 and within the source trench region 7 by means of Al metal sputtering, serving as the lead-out of the source electrode;
[0061] The front electrode metal layer 13 needs to fill the entire source trench region 7, and the ohmic contact alloy 8 on both side walls of the source trench region 7 is in contact with the front electrode metal layer 13Al.
[0062] The PW region 3, the P+ region 5, and the N+ region 6 are at the same potential, enhancing the breakdown voltage and short-circuit withstand ability of the device.
[0063] A SiC UMOSFET device for improving the short-circuit breakdown voltage includes an N+ substrate layer 1, an N- epitaxial layer 2, a PW region 3, and a front electrode metal layer 13 arranged successively from bottom to top;
[0064] The PW region 3 is divided into several regions by the arrangement of a plurality of gate trench regions 4;
[0065] On each region of the PW region 3, there are provided:
[0066] A P+ region 5 extending downward from the middle of the top surface of the PW region 3;
[0067] An N+ region 6 extending downward from the top surface of the PW region 3 along the side of the P+ region 5; there is a spacing between the bottom surface of the N+ region 6 and the bottom surface of the PW region 3;
[0068] An ohmic contact alloy 8 is arranged on the inner side wall of the source trench region 7 in the P+ region 5;
[0069] A gate oxide layer 9 is provided on the inner side wall and the bottom of the gate trench region 4 respectively; the bottom surface of the gate oxide layer 9 is lower than the bottom surface of the PW region 3; the gate trench region 4 is filled with a Poly layer 10 on the gate oxide layer 9;
[0070] A plurality of spaced isolation dielectric layers 11 are provided on the PW region 3; the bottom surfaces of the isolation dielectric layers 11 are connected to the N+ region 6, the gate oxide layer 9, and the Poly layer 10 respectively;
[0071] An ohmic contact alloy layer 12 is provided on the side of the isolation dielectric layer 11 and is connected thereto; the bottom surface of the ohmic contact alloy layer 12 is connected to the N+ region 6 and the P+ region 5 respectively;
[0072] The bottom of the front electrode metal layer 13 extends into the source trench region 7 and is connected to the isolation dielectric layer 11, the ohmic contact alloy layer 12, the P+ region 5, and the ohmic contact alloy 8 respectively.
[0073] Regarding the content disclosed in this case, the following points need to be explained:
[0074] (1)The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case, and other structures can be referred to as commonly involved;
[0075] (2)Without conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments;
[0076] (3)The above is only the specific implementation manners disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.
Claims
1. A SiCUMOSFET device with improved short-circuit withstand voltage, characterized in that: It comprises, from bottom to top, an N+ substrate layer (1), an N- epitaxial layer (2), a PW region (3) and a front electrode metal layer (13); The PW region (3) is divided into a plurality of regions by providing a plurality of gate trench regions (4); The PW area (3) of each region is provided with: A P+ region (5) extending downward from the middle of the top surface of the PW region (3); An N+ region (6) extending downward from the top surface of the PW region (3) along the side of the P+ region (5); An ohmic contact alloy (8) is arranged on the inner side wall of the source trench region (7) in the P+ region (5); The inner sidewalls and the bottom of the gate trench region (4) are respectively provided with a gate oxide layer (9); the bottom surface of the gate oxide layer (9) is lower than the bottom surface of the PW region (3); and the gate trench region (4) is filled with a Poly layer (10) on the gate oxide layer (9); A plurality of isolation dielectric layers (11) are arranged at intervals on the PW region (3); the bottom surfaces of the isolation dielectric layers (11) are respectively connected to the N+ region (6), the gate oxide layer (9) and the Poly layer (10); An ohmic contact alloy layer (12) connected to the side of the isolation dielectric layer (11) is provided; the bottom surface of the ohmic contact alloy layer (12) is respectively connected to the N+ region (6) and the P+ region (5).
2. The SiCUMOSFET device with improved short-circuit withstand voltage according to claim 1, characterized in that: The gate trench region (4) has a depth of 1-1.8 um.
3. The SiCUMOSFET device with improved short-circuit withstand voltage according to claim 1, characterized in that: The depth of the P+ region (5) is the same as the depth of the PW region (3).
4. The SiCUMOSFET device with improved short-circuit withstand voltage according to claim 1, characterized in that: The depth of the N+ region (6) is 0.4-0.8 um.
5. The SiCUMOSFET device with improved short-circuit withstand voltage according to claim 1, characterized in that: The depth of the source trench region (7) is 0.4-0.9 um.