Contact structure, transistor and semiconductor device
By using a composite curved contact structure between the conductive plug and the dielectric layer in the transistor device, the problems of increasing contact resistance and degradation of device performance due to the reduction of contact area are solved, and effective reduction of contact resistance and improvement of device performance are achieved.
Patent Information
- Application Number
- CN202421947894.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-12
AI Technical Summary
With the improvement of chip integration, the characteristic size of the transistor device decreases, resulting in a decrease in the contact area between the metal plug and the diffusion region, an increase in contact resistance, and reliability problems caused by high electric fields lead to degradation of device performance.
The composite curved surface contact structure between the conductive plug and the dielectric layer is adopted to expand the contact area by presenting the composite curved surface morphology on the contact surface, reduce the contact resistance, and form a condensed area on the contact surface between the metal silicide layer and the conductive plug to further reduce the Schottky barrier.
It effectively reduces contact resistance, improves device performance, alleviates the constraints on contact resistance by the degree of metallization and doping concentration, and reduces the risk of leakage.
Smart Images
Figure CN222967311U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor manufacturing, and particularly relates to a contact structure, a transistor and a semiconductor device. Background Art
[0002] With the continuous improvement of chip integration, the feature size of transistor devices continues to be scaled down proportionally, and the contact hole size of metal interconnections also decreases accordingly, resulting in a smaller contact area between the metal plug and the diffusion region and an increase in contact resistance. Moreover, since the operating voltage of transistor devices remains unchanged or only slightly decreases, the reduction of the contact hole size will also lead to an increase in the actual electric field strength inside the transistor devices, and the high electric field will bring a series of reliability problems, easily causing performance degradation of the transistor devices. In this regard, the prior art uses the self-aligned silicide (salicide) technology to first form metal silicide on the contact surface, then perform ion doping on the metal silicide, and after the rapid thermal annealing process, these doped ions will form a segregation region, and the segregation region can effectively reduce the Schottky barrier, thereby reducing the contact resistance and improving the device performance.
[0003] However, the degree of metallization of the metal silicide and the ion doping concentration will restrict the further reduction of the contact resistance. If the contact hole size continues to be reduced, the metal silicide and doped ions will increase the leakage risk of the device.
[0004] Therefore, there is an urgent need for a new contact structure to solve the above technical problems. Summary of the Utility Model
[0005] The purpose of the utility model is to provide a contact structure, a transistor and a semiconductor device to solve the problem of how to reduce the contact resistance of the device.
[0006] To solve the above technical problems, the utility model provides a contact structure, including:
[0007] A contact area, on which a dielectric layer is formed;
[0008] A conductive plug; the conductive plug penetrates through the dielectric layer and is connected to the contact area; wherein, the contact surface between the contact area and the conductive plug is a composite curved surface, and the composite curved surface includes at least two surfaces that are joined at an angle.
[0009] Optionally, in the contact structure, the top surface of the contact area is covered with a metal silicide layer, so that the conductive plug is connected to the metal silicide layer, and the contact surface between the metal silicide layer and the conductive plug is the composite curved surface.
[0010] Optionally, in the contact structure, the cross-sectional profile of the composite surface includes a V shape, a W shape, a sigma groove shape, or a wavy shape.
[0011] Optionally, in the contact structure, an adhesion layer and a barrier layer are sequentially coated on the side wall and part of the bottom wall of the conductive plug from the inside to the outside.
[0012] Based on the same concept, the present invention also provides a transistor, including:
[0013] A substrate, on which a gate structure is formed, and a source electrode and a drain electrode are respectively formed in the substrate on both sides of the gate structure;
[0014] A dielectric layer, which covers the surface of the substrate and the gate structure;
[0015] A plurality of conductive plugs, which penetrate the dielectric layer and are respectively connected to the gate structure, the source electrode, and the drain electrode; wherein, at least one of the contact surfaces of the gate structure, the source electrode, and the drain electrode with the corresponding conductive plug is a composite surface, and the composite surface includes at least two surfaces that are joined at an angle.
[0016] Optionally, in the transistor, a metal silicide layer is coated on the top surface of at least one of the gate structure, the source electrode, and the drain electrode, so that the conductive plug is connected to the metal silicide layer, and the contact surface of the metal silicide layer with the conductive plug is the composite surface.
[0017] Optionally, in the transistor, the cross-sectional profile of the composite surface includes a V shape, a W shape, a sigma groove shape, or a wavy shape.
[0018] Optionally, in the transistor, an adhesion layer and a barrier layer are sequentially coated on the side wall and part of the bottom wall of the conductive plug from the inside to the outside.
[0019] Based on the same concept, the present invention also provides a semiconductor device including the contact structure.
[0020] Based on the same concept, the present invention also provides a semiconductor device including the transistor.
[0021] In summary, the present utility model provides a contact structure, a transistor, and a semiconductor device. Compared with the prior art, the contact structure provided by the present utility model uses a conductive plug to lead out the electrode of the contact area, and the contact surface between the contact area and the conductive plug is a composite curved surface. The composite curved surface includes at least two surfaces that are joined at an angle, which can expand the contact area between the contact area and the conductive plug, enabling the current to disperse and flow through more paths on the contact surface, thereby reducing the contact resistance. Moreover, at least one of the contact surfaces between each conductive plug in the transistor provided by the present utility model and the gate structure, the source, and the drain is the composite curved surface, which is also used to increase the contact area and effectively reduce the contact resistance, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present utility model and do not constitute any limitation to the scope of the present utility model.
[0023] Figure 1 FIG. is a schematic diagram of the contact structure with a wavy contact cross-section in Embodiment 1 of the present utility model.
[0024] Figure 2 FIG. is a physical diagram of the contact structure with a wavy contact cross-section in Embodiment 1 of the present utility model.
[0025] Figure 3 FIG. is a schematic diagram of the contact structure with a V-shaped contact cross-section in Embodiment 1 of the present utility model.
[0026] Figure 4 FIG. is a schematic diagram of the contact structure with a sigma-groove-shaped contact cross-section in Embodiment 1 of the present utility model.
[0027] Figure 5 FIG. is a schematic diagram of the structure of the transistor in Embodiment 2 of the present utility model.
[0028] Figure 6 FIG. is a schematic diagram of the positions of the gate structure, the source, and the drain in Embodiment 2 of the present utility model.
[0029] Figure 7 FIG. is a schematic diagram of the position of the metal silicide layer in Embodiment 2 of the present utility model.
[0030] Figure 8 FIG. is a schematic diagram of the position of the dielectric layer in Embodiment 2 of the present utility model.
[0031] Figure 9 FIG. is a schematic diagram of the structure of the contact hole in Embodiment 2 of the present utility model.
[0032] Moreover, in the drawings:
[0033] 100 - Substrate; 101 - Dielectric layer; 102 - Conductive plug; 103 - Metal silicide layer;
[0034] 200 - Substrate; 201 - Gate structure; 2010 - Oxide layer; 2011 - Polysilicon layer; 2012 - Spacer structure; 202 - Source; 203 - Drain; 204 - Dielectric layer; 205 - Conductive plug; 206 - Shallow trench isolation structure; M - Metal silicide layer; C - Contact surface; T - Contact hole. Detailed implementation manners
[0035] To make the objectives, advantages and features of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes different scales will be adopted. It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.
[0036] <Example 1>
[0037] Please refer to Figure 1 and Figure 2 , this embodiment provides a contact structure, including: a contact area 100, on which a dielectric layer 101 is formed; a conductive plug 102; the conductive plug 102 penetrates through the dielectric layer 101 and is in contact with the contact area 100. Wherein, the contact surface C between the contact area 100 and the conductive plug 102 is a composite curved surface to expand the contact area between the contact area 100 and the conductive plug 102, so that current can be dispersed and flow on the contact surface C through more paths, thereby reducing the contact resistance.
[0038] It should be noted that the composite curved surface referred to in this embodiment includes at least two surfaces joined at an angle, and the surfaces can be curved surfaces or flat surfaces. In other words, the composite curved surface can be formed by splicing two or more curved surfaces, or by splicing two or more non - coplanar flat surfaces, or by splicing one or more curved surfaces and one or more flat surfaces. Wherein, the angle between two adjacent surfaces is greater than 0°, that is, two adjacent surfaces are non - coplanar. And the specific morphology of the composite curved surface is not limited in this embodiment. Exemplarily, the cross - sectional morphology of the composite curved surface can be Figure 1 and Figure 2 the wavy shape shown, or can beFigure 3 the V shape shown, or Figure 4 the sigma groove shape shown.
[0039] Based on this, compared with the relatively flat contact surface, at the same radial dimension, the contact surface C of the composite curved surface morphology enables a larger contact area between the contact region 100 and the conductive plug 102. Based on the current dispersion effect, when the contact surface C increases, the current can flow within the contact surface C through more contact paths, thereby reducing the collision frequency and energy loss of electrons on the contact surface C and achieving a reduction in contact resistance.
[0040] To further reduce the contact resistance, the top surface of the contact region 100 in the contact structure provided in this embodiment is covered with a metal silicide layer 103, and the conductive plug 102 is in contact with the metal silicide layer 103. Among them, the contact surface C between the metal silicide layer 103 and the conductive plug 102 is in the form of the composite curved surface. Specifically, during the process of manufacturing the contact structure, a self-aligned metal silicide process is first performed on the contact region 100 to form a metal silicide layer 103 on its surface. The material of the metal silicide layer 103 includes but is not limited to the reaction product of titanium, cobalt or nickel and silicon. Then, an ion implantation process is performed on the metal silicide layer 103, and the doping ions include but are not limited to nitrogen, phosphorus, boron or arsenic. Finally, a rapid thermal annealing process is performed on the metal silicide layer 103 to enable the doping ions in the metal silicide layer 103 to form a segregation region. The segregation region can effectively reduce the Schottky barrier, so directly contacting the metal silicide layer 103 with the conductive plug 102 can further reduce the contact resistance.
[0041] It should be noted that both the contact area 100 and the conductive plug 102 are conductive, and their materials include but are not limited to metals or semiconductor materials doped with ions. Exemplarily, the material of the contact area 100 is silicon material doped with phosphorus ions, and the material of the conductive plug 102 is tungsten metal. Also, the material of the dielectric layer 101 includes but is not limited to silicon nitride or silicon dioxide, which has better insulation and thermal stability to ensure stable electrode extraction between the contact area 100 and the conductive plug 102. Preferably, an adhesion layer and a barrier layer are sequentially covered on the side wall and part of the bottom wall of the conductive plug 102 from the inside to the outside. That is, an adhesion layer and a barrier layer are also laminated between the conductive plug 102 and the dielectric layer 101, and the adhesion layer is arranged close to the conductive plug 102, and the barrier layer is arranged close to the dielectric layer 101. Among them, the material of the adhesion layer includes but is not limited to titanium, titanium nitride, tantalum or tantalum nitride, which is used to improve the adhesion of the conductive plug 102 and enhance the reliability of the contact structure. The material of the barrier layer includes but is not limited to cobalt tungsten alloy, cobalt tungsten phosphorus alloy or cobalt tungsten boron alloy materials, which are used to prevent the expansion of metal ions, avoid interference, and improve the reliability of the contact structure.
[0042] Based on the same concept, this embodiment also provides a semiconductor device, including the above contact structure. Among them, the specific type of the semiconductor device in this embodiment is not limited, and it can be a transistor, a capacitor, or a metal interconnection structure, etc., and all can use the contact structure to achieve electrode extraction.
[0043] In summary, the contact surface C between the contact area 100 and the conductive plug 102 in the contact structure and the semiconductor device provided in this embodiment is a composite curved surface. Compared with the planar contact, the morphological characteristics of the composite curved surface can increase the contact area and reduce the contact resistance. And the contact structure can alleviate the restriction of the metallization degree and doping concentration on reducing the contact resistance on the basis of the self-aligned metal silicide process, which is beneficial to further reducing the contact resistance and improving the device performance.
[0044] <Embodiment 2>
[0045] Please refer to Figure 5, this embodiment provides a transistor, comprising: a substrate 200, on which a gate structure 201 is formed, and a source electrode 202 and a drain electrode 203 are respectively formed in the substrate 200 on both sides of the gate structure 201; a dielectric layer 204, which covers the surface of the substrate 200 and the gate structure 201; a plurality of conductive plugs 205, which penetrate through the dielectric layer 204 and are respectively connected to the gate structure 201, the source electrode 202 and the drain electrode 203; wherein, at least one of the contact surfaces C between the gate structure 201, the source electrode 202 and the drain electrode 203 and the corresponding conductive plugs 205 is a composite curved surface, and the composite curved surface comprises at least two surfaces that are joined at an angle.
[0046] It can be seen that the transistor provided in this embodiment uses the contact surface C with a composite curved surface to increase the contact area, effectively reduce the contact resistance, and thus improve the device performance.
[0047] The following combines Figures 5 to 9 , and specifically describes the transistor provided in this embodiment.
[0048] Please continue to refer to Figure 5 , the transistor provided in this embodiment includes but is not limited to a metal-oxide-semiconductor field-effect transistor, a junction field-effect transistor, a metal-semiconductor field-effect transistor or a high electron mobility field-effect transistor. Among them, the transistor includes a substrate 200, a gate structure 201, a source electrode 202, a drain electrode 203, a dielectric layer 204, a plurality of conductive plugs 205 and a shallow trench isolation structure 206. The gate structure 201 is located on the substrate 200; the source electrode 202 and the drain electrode 203 are respectively located in the substrate 200 on both sides of the gate structure 201; the dielectric layer 204 covers the surface of the substrate 200 and the gate structure 201. A plurality of the conductive plugs 205 penetrate through the dielectric layer 204 and are respectively connected to the gate structure 201, the source electrode 202 and the drain electrode 203 for electrode lead-out. And, the shallow trench isolation structure 206 is used to achieve electrical isolation and is disposed in the active region of the substrate 200.
[0049] Specifically, the substrate 200 is any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, and can be a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate or a germanium-on-insulator substrate, etc. And in view of different types of transistors, different types of ion-doped well regions are distributed in the substrate 200.
[0050] The gate structure 201 includes an oxide layer 2010 and a polysilicon layer 2011 formed in sequence on the surface of the substrate 200, and a sidewall structure 2012 covering the sidewalls of the oxide layer 2010 and the polysilicon layer 2011. The material of the oxide layer 2010 includes but is not limited to silicon dioxide, which is used to achieve electrical isolation, suppress the short-channel effect, and protect the polysilicon layer 2011, etc. The polysilicon layer 2011 serves as the main material layer of the gate structure 201 and is used to achieve charge transfer and control of the channel current. The material of the sidewall structure 2012 can be an ONO film and / or silicon nitride, which is used to protect the lightly doped drain structure in the substrate 200 and limit the lateral current to improve device performance.
[0051] The source electrode 202 and the drain electrode 203 are the current input / output terminals of the transistor and can be formed in the substrate 200 on both sides of the gate structure 201 through processes such as ion implantation. According to different transistor models, the types and concentrations of ions doped in the source electrode 202 and the drain electrode 203 are also different. Exemplarily, if the transistor is a PMOS, then the source electrode 202 and the drain electrode 203 are doped with P-type ions; or, if the transistor is an NMOS, then the source electrode 202 and the drain electrode 203 are doped with N-type ions.
[0052] The dielectric layer 204 mainly plays a role of electrical isolation, and its material includes but is not limited to silicon nitride or silicon dioxide. The conductive plug 205 is used to lead out the electrodes of the gate structure 201, the source electrode 202, and the drain electrode 203. Therefore, the conductive plug 205 generally uses a metal material with better conductivity, such as tungsten wire, aluminum wire, or copper wire, etc. And to improve the conductivity of the conductive plug 205, an adhesion layer and a barrier layer are also stacked between the conductive plug 205 and the dielectric layer 204. The material of the adhesion layer includes but is not limited to titanium, titanium nitride, tantalum, or tantalum nitride, which is used to improve the adhesion and reliability of the conductive plug 205. The material of the barrier layer includes but is not limited to cobalt tungsten alloy, cobalt tungsten phosphorus alloy, or cobalt tungsten boron alloy material, which is used to prevent the expansion of metal ions, avoid interference, and improve the reliability of the device.
[0053] Furthermore, at least one of the contact surfaces C between the gate structure 201, the source electrode 202, and the drain electrode 203 and the corresponding conductive plug 205 is a composite curved surface. That is, part or all of the contact surface C is a composite curved surface. Preferably, as Figure 5As shown, the contact surfaces C between the gate structure 201, the source 202, the drain 203 and the corresponding conductive plugs 205 are all composite curved surfaces. It should be noted that the composite curved surfaces referred to in this embodiment include at least two surfaces joined at an angle, and the surfaces can be curved surfaces or flat surfaces. In other words, the composite curved surface can be formed by splicing two or more curved surfaces, or by splicing two or more non-coplanar flat surfaces, or by splicing one or more curved surfaces and one or more flat surfaces. Among them, the angle between two adjacent surfaces is greater than 0°, that is, two adjacent surfaces are non-coplanar. And the specific morphology of the composite curved surface is not limited in this embodiment. Optionally, the cross-sectional morphology of the composite curved surface includes but is not limited to V-shaped, sigma groove-shaped or wavy-shaped.
[0054] It can be understood that the contact surface C with a composite curved surface morphology can make the contact areas between the gate structure 201, the source 202 and / or the drain 203 and the corresponding conductive plugs 205 larger, so that current can flow through more contact paths within the contact surface C, thereby reducing the collision frequency and energy loss of electrons on the contact surface C and realizing the reduction of contact resistance.
[0055] To further reduce the contact resistance, in the transistor provided in this embodiment, the top surfaces of at least one of the gate structure 201, the source 202 and the drain 203 are covered with a metal silicide layer M, so that the conductive plug 205 is in contact with the metal silicide layer M. Preferably, the top surfaces of the gate structure 201, the source 202 and the drain 203 in the transistor are all covered with a metal silicide layer M. That is, a self-aligned metal silicide process is used to form the metal silicide layer M on the polysilicon layer 2011, the source 202 and the drain 203. The material of the metal silicide layer M includes but is not limited to the reaction product of titanium, cobalt or nickel and silicon. Then, an ion implantation process and a rapid thermal annealing process are sequentially performed on the metal silicide layer M, so that the doped ions in the metal silicide layer M form a segregation region. The segregation region can effectively reduce the Schottky barrier. Therefore, directly contacting the metal silicide layer M with the conductive plug 205 and making the contact surface C between the metal silicide layer M and the conductive plug 205 be the composite curved surface can greatly reduce the contact resistance and improve the device performance. Optionally, the doped ions include but are not limited to nitrogen, phosphorus, boron or arsenic.
[0056] To fully illustrate the transistor provided in this embodiment, this embodiment also provides a method for manufacturing a transistor, including:
[0057] Step 1: Please refer to Figure 6, a substrate 200 is provided, on which a gate structure 201 is formed, and a source electrode 202 and a drain electrode 203 are respectively formed in the substrate 200 on both sides of the gate structure 201.
[0058] Step two: Please refer to Figure 7 , a metal silicide layer M is formed on the surfaces of the gate structure 201, the source electrode 202, and the drain electrode 203. That is, the metal silicide layer M is formed by using a self-aligned metal silicide technology to reduce the contact resistance and improve the device performance.
[0059] Step three: Please refer to Figure 8 , a dielectric layer 204 is formed on the surface of the substrate 200 and the surface of the gate structure 201. Optionally, the dielectric layer 204 is formed by using a chemical vapor deposition process.
[0060] Step four: Please refer to Figure 9 , a plurality of contact holes T are formed in the dielectric layer 204, and partial surfaces of the metal silicide layer M on the gate structure 201, the source electrode 202, and the drain electrode 203 are exposed; wherein, the bottom surface of the contact hole T is a composite curved surface.
[0061] Optionally, a patterned hard mask layer is first formed on the surface of the dielectric layer 204, and then, using the patterned hard mask layer as a barrier, the exposed dielectric layer 204 is etched by using a dry etching process until partial surfaces of the metal silicide layer M on the gate structure 201, the source electrode 202, and the drain electrode 203 are exposed. Then, the through holes etched in the dielectric layer 204 are processed by using a wet cleaning process or a wet etching process to make the bottom surface of the through holes a composite curved surface. Finally, the through holes are cleaned by using a wet cleaning process and the patterned hard mask layer is removed to form the contact holes T.
[0062] Step five: Please refer to Figure 5 , the contact holes T are filled to form conductive plugs 205.
[0063] Optionally, a barrier layer and an adhesion layer are sequentially formed on the inner wall and the bottom wall of the contact hole T, and then a part of the barrier layer and the adhesion layer on the bottom wall are etched away to expose the metal silicide layer M. Finally, the contact holes T are filled with a conductive material to form the conductive plugs 205.
[0064] Based on the same concept, this embodiment also provides a semiconductor device, including the above transistor.
[0065] In summary, for the transistor and semiconductor device provided in this embodiment, at least one contact surface C between the conductive plug 205 and the gate structure 201, the source 202, and the drain 203 is set as a composite curved surface to increase the contact area, so that the current is dispersed and flows on the contact surface C through more contact paths, thereby reducing the contact resistance. Moreover, the contact surface C with a composite curved surface morphology can alleviate the restriction of the metallization degree and doping concentration involved in the metal silicide layer M on the reduction of the contact resistance, so as to further reduce the contact resistance and improve the device performance.
[0066] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.
Claims
1. A contact structure, characterized in that: include: a contact region, on which a dielectric layer is formed; a conductive plug; The conductive plug penetrates the dielectric layer and is connected to the contact region; wherein the contact surface between the contact region and the conductive plug is a composite curved surface, and the composite curved surface includes at least two surfaces connected at an angle.
2. The contact structure according to claim 1, characterized in that: The top surface of the contact region is covered with a metal silicide layer, so that the conductive plug is in contact with the metal silicide layer, and the contact surface between the metal silicide layer and the conductive plug presents the composite curved surface.
3. The contact structure according to claim 1 or 2, characterized in that: The cross-sectional morphology of the composite curved surface includes a V-shape, a W-shape, a sigma groove shape or a wave shape.
4. The contact structure according to claim 1 or 2, characterized in that: The side wall and part of the bottom wall of the conductive plug are sequentially covered with an adhesion layer and a barrier layer from inside to outside.
5. A transistor, characterized in that: include: a substrate, on which a gate structure is formed, and in which a source and a drain are respectively formed on both sides of the gate structure; a dielectric layer, the dielectric layer covering the surface of the substrate and the gate structure; A plurality of conductive plugs are provided, wherein the plurality of conductive plugs penetrate the dielectric layer and are respectively connected to the gate structure, the source and the drain; wherein at least one of the contact surfaces of the gate structure, the source and the drain with the corresponding conductive plug is a composite curved surface, and the composite curved surface includes at least two surfaces connected at an angle.
6. The transistor according to claim 5, characterized in that The top surface of at least one of the gate structure, the source and the drain is covered with a metal silicide layer, so that the conductive plug is connected to the metal silicide layer, and the contact surface between the metal silicide layer and the conductive plug presents the composite curved surface.
7. The transistor according to claim 5 or 6, characterized in that: The cross-sectional morphology of the composite curved surface includes a V-shape, a W-shape, a sigma groove shape or a wave shape.
8. The transistor according to claim 5 or 6, characterized in that: The side wall and part of the bottom wall of the conductive plug are sequentially covered with an adhesion layer and a barrier layer from inside to outside.
9. A semiconductor device, characterized in that: The method comprises the contact structure as claimed in any one of claims 1 to 4.
10. A semiconductor device, characterized in that: Comprising a transistor as claimed in any one of claims 5 to 8.