Solar cell, photovoltaic module and photovoltaic system
By designing doped layers to form contact areas in solar cells, the problem of heat spot risk caused by local shadows of photovoltaic modules is solved, efficient current transmission and heat generation control are achieved, and the reliability and power generation capacity of the module are improved.
Patent Information
- Application Number
- CN202421900074.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-06
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-06
AI Technical Summary
Existing photovoltaic modules are susceptible to occlusions during long-term use, resulting in local shadow formation, increasing the risk of heat spots and reducing component power.
By designing the first doped layer and the second doped layer in the solar cell to form contact areas, these doped layers generate a composite leakage current when the reverse voltage is applied across the solar cell, thereby achieving efficient current transmission and control of heat generation.
It effectively reduces the risk of heat spots, improves the reliability and power generation capacity of solar cells, and extends the service life and maintains high power output.
Smart Images
Figure CN222967342U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of photovoltaic, and particularly relates to a solar cell, a photovoltaic module and a photovoltaic system. Background Art
[0002] Photovoltaic modules composed of multiple cells are usually installed in open areas with sufficient sunlight. During long-term use, it is inevitable that they will be covered by obstacles such as birds, dust, and fallen leaves. These obstacles form shadows on the photovoltaic modules. In a large photovoltaic module array, inappropriate row spacing can also cause mutual shading. Due to the existence of local shadows, the current and voltage of some single solar cells in the photovoltaic module change. Conventional solar cells have diode characteristics. The shaded cell has a reverse bias characteristic, which increases the product of the local current and voltage of the photovoltaic module, and its power consumption is extremely high, resulting in a phenomenon of local temperature rise on these photovoltaic modules. Defects in some single cells of the photovoltaic module itself may also cause local heating during operation. This phenomenon is called the "hot spot effect". Therefore, existing photovoltaic modules with such cells have a relatively high hot spot risk during actual operation. After being encapsulated into a photovoltaic module, the hot spot effect may reduce the module power and pose a safety problem of local temperature rise at the same time. In related technologies, the hot spot risk of photovoltaic modules is often avoided by setting bypass diodes, but this method will significantly reduce the module power. Therefore, it is urgent to reduce the "hot spot effect" through other technical means while maintaining the high power output of the module. Content of the Utility Model
[0003] The utility model provides a solar cell, a photovoltaic module and a photovoltaic system, aiming to solve the problem of how to reduce the "hot spot effect" while maintaining the high power output of the module.
[0004] The utility model is implemented as follows. A solar cell includes:
[0005] A silicon substrate having a first surface and a second surface disposed opposite to each other;
[0006] A first doping layer disposed on the first surface;
[0007] A second doping layer disposed on the second surface, and the second doping layer has a polarity opposite to that of the first doping layer;
[0008] Wherein, at least one of the first doping layer and the second doping layer extends along the side surface of the silicon substrate and makes conductive contact with the other of the first doping layer and the second doping layer to form a contact area;
[0009] A metal grid line and / or a solder strip are disposed on the surface of the first doping layer and / or the second doping layer, and the contact area is not electrically connected to the metal grid line and is not electrically connected to the solder strip.
[0010] Optionally, the contact area is disposed along a side surface of at least one side of the silicon substrate, and the contact area partially or completely covers the side surface.
[0011] Optionally, the contact area extends from the first surface along the side surface of at least one side of the silicon substrate to at least a partial area of the second surface, or the contact area extends from the second surface along the side surface of at least one side of the silicon substrate to at least a partial area of the first surface.
[0012] Optionally, the contact area is disposed along a side surface of at least one side of the silicon substrate, forming a strip extending along the thickness direction of the silicon substrate and covering a partial side surface of the silicon substrate.
[0013] Optionally, the contact area extends from the first surface along the side surface of at least one side of the silicon substrate to at least a partial area of the second surface, or the contact area extends from the second surface along the side surface of at least one side of the silicon substrate to at least a partial area of the first surface.
[0014] Optionally, the contact area is disposed along at least one side edge of the first surface or the second surface of the silicon substrate.
[0015] Optionally, at least a partial contact area extends from the side edge to the opposite side of the surface of the silicon substrate where the contact area is located.
[0016] Optionally, the contact area extends to the side surface on the opposite side of the silicon substrate.
[0017] Optionally, the solar cell further includes:
[0018] A first passivation layer disposed between the first doping layer and the silicon substrate, and the first doping layer is in indirect conductive contact with the second doping layer through the first passivation layer; and / or
[0019] A second passivation layer disposed between the second doping layer and the silicon substrate, and the second doping layer is in indirect conductive contact with the first doping layer through the second passivation layer.
[0020] The present utility model further provides a photovoltaic module including the above-mentioned solar cell.
[0021] The present utility model further provides a photovoltaic system including the above-mentioned photovoltaic module.
[0022] The beneficial effects achieved by the present utility model are as follows. By optimizing the structural design of the solar cell, especially by forming a contact region through the first doping layer and the second doping layer, when a reverse voltage is applied across the two ends of the solar cell, a composite leakage current of appropriate magnitude can be generated, realizing efficient current transmission and effective control of heat generation. While ensuring that the conversion efficiency of the solar cell is basically not lost, the risk of hot spots is reduced, and the reliability, power generation capacity, and service life of the solar cell are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 1 ;
[0024] Figure 2 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 2 ;
[0025] Figure 3 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 3 ;
[0026] Figure 4 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 4 ;
[0027] Figure 5 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 5 ;
[0028] Figure 6 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 6 ;
[0029] Figure 7 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 7 ;
[0030] Figure 8 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 8 ;
[0031] Figure 9 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 9 ;
[0032] Figure 10 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 10 ;
[0033] Figure 11 is the cross-sectional view of the solar cell structure provided by an embodiment of the present application Figure 11 One;
[0034] Figure 12is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 12 Two;
[0035] Figure 13 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 13 Three;
[0036] Figure 14 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 14 Four;
[0037] Figure 15 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 15 Five;
[0038] Figure 16 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 16 Six;
[0039] Figure 17 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 17 Seven;
[0040] Figure 18 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 18 Eight;
[0041] Figure 19 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 19 Nine;
[0042] Figure 20 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 20 Ten;
[0043] Figure 21 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 21 Eleven;
[0044] Figure 22 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 22 Twelve;
[0045] Figure 23 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 23 Thirteen;
[0046] Figure 24 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 24 Fourteen;
[0047] Figure 25 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 25 Fifteen;
[0048] Figure 26 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 26 Sixteen;
[0049] Figure 27 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 27 Seventeen;
[0050] Figure 28 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 28 Eighteen;
[0051] Figure 29 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 29 Nineteen;
[0052] Figure 30 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 30 Ten;
[0053] Figure 31 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 31 Eleven;
[0054] Figure 32 is the cross-section of the solar cell structure provided by the embodiments of the present application Figure 32 Twelve;
[0055] Figure 33 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 1 ;
[0056] Figure 34 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 2 ;
[0057] Figure 35 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 3 ;
[0058] Figure 36 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 4 ;
[0059] Figure 37 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 5 ;
[0060] Figure 38 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present application Figure 6 ;
[0061] Figure 39 is the partial three-dimensional schematic of the solar cell structure provided by the embodiments of the present applicationFigure 7 ;
[0062] Figure 40 is a partial three-dimensional schematic diagram of the solar cell structure provided by the embodiments of the present application Figure 8 .
[0063] Description of the reference numerals:
[0064] 100, solar cell; 111, first surface; 112, second surface; 113, side surface; 110, metal grid line / solder ribbon; 10, silicon substrate; 20, first doping layer; 30, second doping layer; 40, first passivation layer; 50, first extension part; 60, second extension part; 70, third extension part; 80, second passivation layer; 90, fourth extension part. Detailed implementation manners
[0065] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present utility model and cannot be construed as a limitation to the present utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0066] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present utility model.
[0067] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.
[0068] In the description of the present utility model, it should be noted that, unless otherwise clearly defined and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or a connection that allows mutual communication; it may be a direct connection, or an indirect connection through an intermediate medium, and it may be the internal communication between two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0069] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but being in contact through other features therebetween. Moreover, the first feature being "above", "over", and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath", and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.
[0070] The following disclosure provides many different embodiments or examples for implementing different structures of the present utility model. To simplify the disclosure of the present utility model, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present utility model. In addition, the present utility model may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present utility model provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.
[0071] By optimizing the structural design of the solar cell, especially by forming a contact region through the first doping layer and the second doping layer, when a reverse voltage is applied across the two ends of the solar cell, a composite leakage current of appropriate magnitude can be generated, achieving efficient current transmission and effective control of heat generation, ensuring that the conversion efficiency of the solar cell is basically not lost while reducing the risk of hot spots, and improving the reliability, power generation capacity, and service life of the solar cell.
[0072] Example 1
[0073] As Figures 33 to 40 shown, this embodiment provides a solar cell, comprising: a silicon substrate 10, the silicon substrate 10 having a first surface and a second surface disposed opposite to each other;
[0074] A first doping layer 20 is disposed on the first surface;
[0075] A second doping layer 30 is disposed on the second surface, and the second doping layer 30 has a polarity opposite to that of the first doping layer 20;
[0076] Wherein, at least one of the first doping layer 20 and the second doping layer 30 extends along the side surface of the silicon substrate 10 and makes electrical contact with the other of the first doping layer 20 and the second doping layer 30 to form a contact region;
[0077] A metal grid line and / or a solder strip 110 are disposed on the surface of the first doping layer 20 and / or the second doping layer 30, and the contact region is not electrically connected to the metal grid line 110, and the contact region is not electrically connected to the solder strip 110.
[0078] The first doping layer 20 is disposed on the first surface of the silicon substrate 10, and the second doping layer 30 is disposed on the second surface of the silicon substrate 10. The first doping layer 20, the silicon substrate 10, and the second doping layer 30 form a pn junction structure to realize the separation and collection process of photo-generated carriers of the solar cell. At least one of the first doping layer 20 and the second doping layer 30 contacts the other of the second doping layer 30 and the first doping layer 20 via the side surface of the silicon substrate 10 to realize the electrical connection between the first doping layer 20 and the second doping layer 30.
[0079] Usually, multiple solar cells in a photovoltaic module can be connected in series in sequence to form a battery string, and each battery string can be connected in series, in parallel, or in a series-parallel combination to realize the current confluence output. For example, the connection between each solar cell can be realized by welding a solder strip, and the connection between each battery string can be realized by a bus bar.
[0080] When the solar cell is generating electricity normally, the contact region between the first doping layer 20 and the second doping layer 30 also performs photoelectric conversion to generate electricity, thereby improving the power generation efficiency of the solar cell. When the solar cell is shaded, insufficient light will cause the current output of the shaded part to decrease, resulting in an increase in the voltage of this part. However, the contact region forms an electrical conduction path, and other solar cells connected in series with it provide reverse current for the shaded solar cell. A suitable composite leakage current can be generated between the first doping layer 20 and the second doping layer 30 of the solar cell, reducing the voltage across the shaded solar cell (the voltage is less than the sum of the voltages of other solar cells connected in series with this solar cell and not shaded), and the heating power of the solar cell will decrease, thereby reducing the high heat risk of the hot spot effect.
[0081] Secondly, by deliberately introducing a conductive contact structure in the solar cell, it has a protective effect on the hot spot effect caused by the defects of the silicon substrate 10 itself (i.e., it can reduce the heat generation caused by the defects), can reduce or even cancel the control requirements for the defects of the silicon substrate 10, and improves the manufacturing capacity of the solar cell while reducing the hot spot risk caused by the defects of the silicon substrate 10.
[0082] In addition, the design of the metal grid lines and the solder ribbons 110 is also to maximize the power generation efficiency and reliability of the solar cell. The metal grid lines and / or the solder ribbons 110 are arranged on the surface of the first doping layer 20 and / or the second doping layer 30 according to actual connection requirements. The metal grid lines are arranged on the surface of the doping layer, which can effectively collect and conduct the photo-generated current and reduce the current loss. The solder ribbons are used to connect multiple solar cells to form a stable battery string. Since the contact area is not electrically connected to the metal grid lines and the solder ribbons, unnecessary current leakage is avoided, ensuring the current transmission efficiency of the battery string. The metal grid lines can specifically be fine grids or main grids, which are not limited herein.
[0083] It should be specifically noted that the thickness of the first doping layer 20 can be uniform, that is, the overall thickness of the first doping layer 20 is consistent, or the thickness of the first doping layer 20 can be non-uniform, that is, the overall thickness of the first doping layer 20 is inconsistent, and the thickness of a part of the first doping layer 20 is greater than that of another part of the first doping layer 20. The situation of the thickness of the second doping layer 30 is the same as that of the first doping layer 20, which will not be elaborated herein, and the present application does not limit this.
[0084] In some embodiments, the material of the silicon substrate 10 can be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, for example, it can be silicon or germanium. Among them, the elemental semiconductor material can be in single crystal state, polycrystalline state, amorphous state or microcrystalline state. For example, silicon can be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.
[0085] In some embodiments, the silicon substrate 10 can be an N-type semiconductor substrate, a P-type semiconductor substrate or an intrinsic semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, and the N-type doping element can be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, and the P-type doping element can be any one of group III elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In).
[0086] Preferably, in this embodiment, the silicon substrate 10 is a silicon substrate 10 made of single crystal silicon. The ordered crystal structure helps to reduce the scattering and recombination probability of carriers during migration. In this way, less recombination occurs between the silicon substrate 10 and the first doping layer 20, increasing the number and mobility of carriers.
[0087] In some embodiments, the silicon substrate 10 has a first surface 111 and a second surface 112 that are oppositely disposed. Among them, the first surface 111 can be the front surface, and the second surface 112 can be the back surface. The "front" and "back" in the front surface and the back surface are relative. That is, the "front" refers to the side facing the sunlight along the vertical direction, and the "back" refers to the side facing away from the sunlight along the vertical direction.
[0088] Specifically, in the embodiments of the present application, the first doping layer 20 is disposed on the first surface 111 of the silicon substrate 10, and the second doping layer 30 is disposed on the second surface 112 of the silicon substrate 10. The first doping layer 20 can be an N-type doping layer, and the second doping layer 30 can be a P-type doping layer. Of course, it can also be that the first doping layer 20 is a P-type doping layer and the second doping layer 30 is an N-type doping layer, and the polarities of the two are opposite.
[0089] It should be noted that in the present application, "one of the first doping layer 20 and the second doping layer 30 extends along the side surface of the silicon substrate 10 and makes conductive contact with the other of the first doping layer 20 and the second doping layer 30 to form a contact region" means that there is no insulation between the two. It can be that the two are in direct conductive contact or indirect conductive contact is achieved through other passivation layers. For example, the two can be in indirect conductive contact through the first passivation layer 40 or the second passivation layer 80 mentioned below.
[0090] In this embodiment, by optimizing the structural design of the solar cell, especially by forming a contact region through the first doping layer 20 and the second doping layer 30, when a reverse voltage is applied across the solar cell, a suitable recombination leakage current can be generated, achieving efficient current transmission and effective control of heat generation, ensuring that the conversion efficiency of the solar cell is basically not lost while reducing the risk of hot spots, and improving the reliability, power generation capacity, and service life of the solar cell.
[0091] Example 2
[0092] As Figure 33 shown, on the basis of Embodiment 1, the contact region is disposed along at least one side surface of the silicon substrate 10, and the contact region partially or completely covers the side surface.
[0093] Specifically, it can be, as Figure 1As shown, a first doping layer 20 covers the first surface 111 of the silicon substrate 10. A first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. A second doping layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 covers the outside of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0094] Alternatively, a first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10. The first doping layer 20 is in indirect conductive contact with the second doping layer 30 through the first passivation layer 40. A second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10. The second doping layer 30 is in indirect conductive contact with the first doping layer 20 through the second passivation layer 80. By providing the first passivation layer 40 and the second passivation layer 80, the recombination of photo-generated electrons and holes can be prevented, the energy loss during the photoelectric conversion process can be reduced, the passivation layer can form a good ohmic contact with the metal electrode, and the fill factor and short-circuit current of the battery can be improved, thereby further enhancing the photoelectric conversion efficiency.
[0095] When the first doping layer 20 and the second doping layer 30 are in contact on the side surface of the silicon substrate 10, the manner in which the first doping layer 20 and the second doping layer 30 form a conductive contact on the side surface of the silicon substrate 10 is as follows:
[0096] As Figure 1 shown, a first doping layer 20 covers the first surface 111 of the silicon substrate 10. A first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. A second doping layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 covers the outside of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0097] As Figure 2 shown, a first doping layer 20 covers the first surface 111 of the silicon substrate 10. A first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. A first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10. A second doping layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 covers the outside of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0098] As shown Figure 3 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10. The first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. A first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10. The second doping layer 30 covers the second surface 112 of the silicon substrate 10. The second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. The first passivation layer 40 is located between the first extension portion 50 and the second extension portion 60. The first extension portion 50 and the first passivation layer 40 cover the outside of the second extension portion 60. The first extension portion 50 forms an indirect conductive contact with the second extension portion 60 on the side surface 113 of the silicon substrate 10 through the first passivation layer 40.
[0099] As shown Figure 4 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10. The first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. The second doping layer 30 covers the second surface 112 of the silicon substrate 10. The second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. A second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10. The second doping layer 30 and the second passivation layer 80 cover the outside of the first extension portion 50. The second passivation layer 80 is located between the first extension portion 50 and the second extension portion 60. The second extension portion 60 forms an indirect conductive contact with the first extension portion 50 on the side surface 113 of the silicon substrate 10 through the second passivation layer 80.
[0100] As shown Figure 5 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10. The first extension portion 50 of the first doping layer 20 extends along the side surface 113 of the silicon substrate 10. The second doping layer 30 covers the second surface 112 of the silicon substrate 10. The second extension portion 60 of the second doping layer 30 extends along the side surface 113 of the silicon substrate 10. A first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10. A second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10. The second extension portion 60 and the second passivation layer 80 cover the outside of the first extension portion 50 and the first passivation layer 40. The second extension portion 60 forms an indirect conductive contact with the first extension portion 50 on the side surface 113 of the silicon substrate 10 through the second passivation layer 80.
[0101] As shown Figure 6As shown, a first doped layer 20 covers the first surface 111 of a silicon substrate 10. A first extension portion 50 of the first doped layer 20 extends along a side surface 113 of the silicon substrate 10. A second doped layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doped layer 30 extends along the side surface 113 of the silicon substrate 10. A first passivation layer 40 is disposed between the first doped layer 20 and the silicon substrate 10. A second passivation layer 80 is disposed between the second doped layer 30 and the silicon substrate 10. The first extension portion 50 and the first passivation layer 40 cover the outside of the second extension portion 60 and the second passivation layer 80. The first extension portion 50 forms an indirect conductive contact with the second extension portion 60 on the side surface 113 of the silicon substrate 10 through the first passivation layer 40 and the second passivation layer 80.
[0102] As Figure 7 shown, a first doped layer 20 covers the first surface 111 of a silicon substrate 10. A first extension portion 50 of the first doped layer 20 extends along a side surface 113 of the silicon substrate 10. The first extension portion 50 partially covers the side surface of the silicon substrate 10. A second doped layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doped layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 covers the outside of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0103] As Figure 8 shown, a first doped layer 20 covers the first surface 111 of a silicon substrate 10. A first extension portion 50 of the first doped layer 20 extends along a side surface 113 of the silicon substrate 10. A second doped layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doped layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 partially covers the outside of the first extension portion 50. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0104] As Figure 9 shown, a first doped layer 20 covers the first surface 111 of a silicon substrate 10. A first extension portion 50 of the first doped layer 20 extends along a side surface 113 of the silicon substrate 10. A second doped layer 30 covers the second surface 112 of the silicon substrate 10. A second extension portion 60 of the second doped layer 30 extends along the side surface 113 of the silicon substrate 10. The second extension portion 60 partially covers the side surface of the silicon substrate 10. The first extension portion 50 covers the outside of the second extension portion 60. The first extension portion 50 and the second extension portion 60 form a direct conductive contact on the side surface 113 of the silicon substrate 10.
[0105] Example 3
[0106] As Figure 34 shown, based on the first embodiment, the contact area extends from the first surface along the side surface of at least one side of the silicon substrate 10 to at least a partial area of the second surface, or the contact area extends from the second surface along the side surface of at least one side of the silicon substrate 10 to at least a partial area of the first surface.
[0107] When the contact area covers all the side surfaces, the contact area continues to extend to a partial area of the first surface or the second surface. It can be that the first doping layer 20 extends towards the second surface, or the second doping layer 30 extends towards the first surface. The specific extension scheme can be obtained based on the second embodiment and will not be elaborated here. The shape extended by the contact area can be strip-shaped, triangular, or other shapes, which are not limited herein.
[0108] Example 4
[0109] As Figure 35 shown, based on the first embodiment, the contact area is arranged along the side surface of at least one side of the silicon substrate 10, forming a strip extending along the thickness direction of the silicon substrate 10 and covering a partial side surface of the silicon substrate 10.
[0110] The specific setting structures of the first doping layer 20 and the second doping layer 30 are similar to those in the second embodiment. The difference is that in the second embodiment, the first extension part 50 and the second extension part 60 entirely cover the whole side surface, while in this embodiment, at least one of the first extension part 50 of the first doping layer 20 and the second extension part 60 of the second doping layer 30 is strip-shaped extending along the thickness direction of the silicon substrate 10 and can only cover a partial side surface.
[0111] Example 5
[0112] As Figure 36 shown, based on the fourth embodiment, the contact area extends from the first surface along the side surface of at least one side of the silicon substrate 10 to at least a partial area of the second surface, or the contact area extends from the second surface along the side surface of at least one side of the silicon substrate 10 to at least a partial area of the first surface.
[0113] The contact area continues to extend to a partial area of the first surface or the second surface. It can be that the first doping layer 20 extends towards the second surface, or the second doping layer 30 extends towards the first surface. The specific extension scheme can be obtained based on the fourth embodiment and will not be elaborated here. The shape extended by the contact area can be strip-shaped, triangular, or other shapes, which are not limited herein.
[0114] Example 6
[0115] AsFigure 37 As shown, on the basis of the first embodiment, the contact region is disposed along at least one side edge of the first surface or the second surface of the silicon substrate 10.
[0116] In actual operation, it may be only one side edge, or two adjacent side edges, or two opposite side edges, as well as other quantities or setting manners. Specifically, the formation of the contact region may be that the first doping layer 20 and the second doping layer 30 form a conductive contact region on the first surface of the silicon substrate 10, or the second doping layer 30 and the first doping layer 20 form a conductive contact region on the second surface of the silicon substrate 10.
[0117] When the first doping layer 20 and the second doping layer 30 are in contact on the first surface of the silicon substrate 10, the second doping layer 30 has a fourth extension portion 90 extending to the first surface along the side surface 113 of the silicon substrate 10. The fourth extension portion 90 is disposed in at least a partial region of the side surface 113 and the first surface of the silicon substrate 10, and the fourth extension portion 90 and the first doping layer 20 are in direct conductive contact on the first surface 111. In some embodiments, such as Figure 12 , while the first doping layer 20 and the second doping layer 30 are in direct conductive contact on the first surface 111, a first passivation layer 40 is further disposed between the first doping layer 20 and the silicon substrate 10.
[0118] Specifically, the manner in which the first doping layer 20 and the second doping layer 30 form a conductive contact region on the first surface of the silicon substrate 10 is as follows:
[0119] Figure 10 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a part of the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the fourth extension portion 90 of the second doping layer 30 covers at least a partial region of the first surface 111 of the silicon substrate 10, the fourth extension portion 90 covers the outside of the first doping layer 20, and the fourth extension portion 9050 and the first doping layer 20 form direct conductive contact on the first surface 111 of the silicon substrate 10.
[0120] Such as Figure 11 As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a part of the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the fourth extension portion 90 of the second doping layer 30 covers at least a partial region of the first surface 111 of the silicon substrate 10, a second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10, the fourth extension portion 90 and the second passivation layer 80 cover the outside of the first doping layer 20, and the fourth extension portion 9050 forms indirect conductive contact with the first doping layer 20 through the second passivation layer 80 on the first surface 111 of the silicon substrate 10.
[0121] Such asFigure 12 As shown, a first doping layer 20 covers the first surface 111 of a silicon substrate 10, a part of a second doping layer 30 covers the second surface 112 of the silicon substrate 10, a fourth extension part 90 of the second doping layer 30 covers at least a partial area of the first surface 111 of the silicon substrate 10, a first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10, the fourth extension part 90 covers the outside of the first doping layer 20, and a direct conductive contact is formed between the fourth extension part 9050 and the first doping layer 20 on the first surface 111 of the silicon substrate 10.
[0122] As Figure 13 As shown, a first doping layer 20 covers the first surface 111 of a silicon substrate 10, a part of a second doping layer 30 covers the second surface 112 of the silicon substrate 10, a fourth extension part 90 of the second doping layer 30 covers at least a partial area of the first surface 111 of the silicon substrate 10, a first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10, the first doping layer 20 and the first passivation layer 40 cover the outside of the fourth extension part 90, and an indirect conductive contact is formed between the first doping layer 20 and the fourth extension part 90 on the first surface 111 of the silicon substrate 10 through the first passivation layer 40.
[0123] As Figure 14 As shown, a first doping layer 20 covers the first surface 111 of a silicon substrate 10, a part of a second doping layer 30 covers the second surface 112 of the silicon substrate 10, a fourth extension part 90 of the second doping layer 30 covers at least a partial area of the first surface 111 of the silicon substrate 10, a second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10, the first doping layer 20 covers the outside of the fourth extension part 90, and a direct conductive contact is formed between the first doping layer 20 and the fourth extension part 90 on the first surface 111 of the silicon substrate 10.
[0124] As Figure 15 As shown, a first doping layer 20 covers the first surface 111 of a silicon substrate 10, a part of a second doping layer 30 covers the second surface 112 of the silicon substrate 10, a fourth extension part 90 of the second doping layer 30 covers at least a partial area of the first surface 111 of the silicon substrate 10, a first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10, a second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10, the first doping layer 20 and the first passivation layer 40 cover the outside of the fourth extension part 90, and an indirect conductive contact is formed between the first doping layer 20 and the fourth extension part 90 on the first surface 111 of the silicon substrate 10 through the first passivation layer 40.
[0125] As Figure 16As shown, the first doping layer 20 covers the first surface 111 of the silicon substrate 10, a part of the second doping layer 30 covers the second surface 112 of the silicon substrate 10, the fourth extension part 90 of the second doping layer 30 covers at least a partial area of the first surface 111 of the silicon substrate 10, a first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10, a second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10, the fourth extension part 90 and the second passivation layer 80 cover the outside of the first doping layer 20, and the second doping layer 30 forms an indirect conductive contact with the first doping layer 20 on the first surface 111 of the silicon substrate 10 through the second passivation layer 80.
[0126] When the first doping layer 20 and the second doping layer 30 are in contact on the second surface of the silicon substrate 10, the first doping layer 20 has a third extension part 70 extending along the side surface 113 of the silicon substrate 10 to the second surface 112, and the third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10, and the third extension part 70 is in contact with the second doping layer 30 on the second surface 112.
[0127] Specifically, the first doping layer 20 and the second doping layer 30 form a conductive contact area on the second surface of the silicon substrate 10 in the following manner:
[0128] As Figure 17 shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, another part of the first doping layer 20, i.e., the third extension part 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, the third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10, the second doping layer 30 covers the outside of the third extension part 70, and the third extension part 70 forms a direct conductive contact with the second doping layer 30 on the second surface 112.
[0129] As Figure 18 shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, another part of the first doping layer 20, i.e., the third extension part 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112, the third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10, a second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10, the second doping layer 30 and the second passivation layer 80 cover the outside of the third extension part 70, and the second doping layer 30 forms an indirect conductive contact with the third extension part 70 through the second passivation layer 80.
[0130] As Figure 19As shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part, the third extension part 70 of the first doping layer 20, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer 40 is provided between the first doping layer 20 and the silicon substrate 10. The second doping layer covers the outside of the third extension part 70, and the second doping layer 30 and the third extension part 70 form a direct conductive contact on the second surface 112.
[0131] As Figure 20 As shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part, the third extension part 70 of the first doping layer 20, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer 40 is provided between the first doping layer 20 and the silicon substrate 10. A second passivation layer 80 is provided between the second doping layer 30 and the silicon substrate 10. The second doping layer 30 and the second passivation layer 80 cover the outside of the third extension part 70, and the second doping layer 30 forms an indirect conductive contact with the third extension part 70 through the second passivation layer 80.
[0132] As Figure 21 As shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part, the third extension part 70 of the first doping layer 20, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. The third extension part 70 covers the outside of the second doping layer 30, and the third extension part 70 and the second doping layer 30 form a direct conductive contact on the second surface 112.
[0133] As Figure 22 As shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part, the third extension part 70 of the first doping layer 20, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer 40 is provided between the first doping layer 20 and the silicon substrate 10. The third extension part 70 and the first passivation layer 40 cover the outside of the second doping layer 30, and the third extension part 70 forms an indirect conductive contact with the second doping layer 30 through the first passivation layer 40 on the second surface 112.
[0134] As Figure 23As shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part of the first doping layer 20, i.e., the third extension part 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. A second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10. The third extension part 70 covers the outside of the second doping layer 30, and the third extension part 70 forms a direct conductive contact with the second doping layer 30 on the second surface 112.
[0135] As Figure 24 shown, a part of the first doping layer 20 covers the first surface 111 of the silicon substrate 10, and another part of the first doping layer 20, i.e., the third extension part 70, extends along the side surface 113 of the silicon substrate 10 to the second surface 112. The third extension part 70 covers at least a partial area of the side surface 113 and the second surface 112 of the silicon substrate 10. A first passivation layer 40 is disposed between the first doping layer 20 and the silicon substrate 10. A second passivation layer 80 is disposed between the second doping layer 30 and the silicon substrate 10. The third extension part 70 and the first passivation layer 40 cover the outside of the second doping layer 30, and the third extension part 70 forms an indirect conductive contact with the second doping layer 30 through the first passivation layer 40 on the second surface 112.
[0136] Furthermore, when the first doping layer 20 and the second doping layer 30 form a conductive contact on the second surface of the silicon substrate 10, the second doping layer 30 is deposited on the edge of the silicon substrate 10 to form a convex structure. The specific contact form of the first doping layer 20 and the second doping layer 30 is Figures 17 to 24 the same as the case described above, and will not be elaborated here. The form of the direct conductive contact between the first doping layer 20 and the second doping layer 30 is as Figure 25 and Figure 29 , and the form of the indirect conductive contact between the first doping layer 20 and the second doping layer 30 through the passivation layer is as Figure 26 , Figure 27 , Figure 28 , Figure 30 , Figure 31 and Figure 32 .
[0137] In this embodiment, the specific setting method of the contact area is exemplified. The contact area constitutes a bypass circuit of the solar cell, which can generate a composite leakage current with an appropriate magnitude, avoiding the high thermal risk of the hot spot effect and the potential safety hazard caused by the high heat accumulation of the hot spot effect.
[0138] Example 7
[0139] As Figure 38 and Figure 39As shown, on the basis of Embodiment 4, at least part of the contact area extends from the side to the opposite side of the surface of the silicon substrate 10 where the contact area is located.
[0140] The contact area continues to extend to a partial area of the first surface or the second surface. It can be that the first doping layer 20 extends towards the second surface, or the second doping layer 30 extends towards the first surface. The specific extension scheme can be obtained on the basis of Embodiment 6 and will not be elaborated here. The shape extended by the contact area can be strip-shaped, triangular, or other shapes, which are not limited here.
[0141] Example 8
[0142] As Figure 40 shown, on the basis of Embodiment 3, Embodiment 5, and Embodiment 7, the contact area extends to the side opposite to the silicon substrate 10.
[0143] The contact area traverses the entire first surface or the second surface, extending from one side of the first surface or the second surface to the opposite side.
[0144] Example 9
[0145] This embodiment provides a photovoltaic module, including the solar cell of the above embodiment.
[0146] The beneficial effects of the photovoltaic module in this embodiment are equivalent to those of the above solar cell and will not be elaborated here.
[0147] Example 10
[0148] This embodiment provides a photovoltaic system, including the photovoltaic module of the above embodiment.
[0149] The beneficial effects of the photovoltaic system in this embodiment are equivalent to those of the above solar cell and will not be elaborated here.
[0150] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface disposed opposite to each other; a first doped layer, the first doped layer being disposed on the first surface; A second doping layer, wherein the second doping layer is disposed on the second surface, and the second doping layer has a polarity opposite to that of the first doping layer; Wherein, at least one of the first doping layer and the second doping layer extends along the side of the silicon substrate and is in conductive contact with the other of the first doping layer and the second doping layer to form a contact region; Metal grid lines and / or welding strips are disposed on the surface of the first doping layer and / or the second doping layer, and the contact area is not electrically connected to the metal grid lines, and the contact area is not electrically connected to the welding strips.
2. The solar cell according to claim 1, characterized in that The contact region is arranged along a side surface of at least one side of the silicon substrate, and the contact region partially or completely covers the side surface.
3. The solar cell according to claim 2, characterized in that The contact region extends from the first surface along at least one side of the silicon substrate to at least a portion of the second surface, or the contact region extends from the second surface along at least one side of the silicon substrate to at least a portion of the first surface.
4. The solar cell according to claim 1, characterized in that The contact area is arranged along at least one side of the silicon substrate to form a strip extending along the thickness direction of the silicon substrate and covering part of the side of the silicon substrate.
5. The solar cell according to claim 4, characterized in that: The contact region extends from the first surface along at least one side of the silicon substrate to at least a portion of the second surface, or the contact region extends from the second surface along at least one side of the silicon substrate to at least a portion of the first surface.
6. The solar cell according to claim 1, characterized in that: The contact region is arranged along at least one side of the first surface or the second surface of the silicon substrate.
7. The solar cell according to claim 6, characterized in that At least a portion of the contact region extends from the side edge to an opposite side of the surface of the silicon substrate where the contact region is located.
8. The solar cell according to any one of claims 3, 5 or 7, characterized in that: The contact region extends to the side surfaces opposite to the silicon substrate.
9. The solar cell according to claim 1, characterized in that: The solar cell also includes: a first passivation layer, wherein the first passivation layer is disposed between the first doped layer and the silicon substrate, and the first doped layer is indirectly conductively contacted with the second doped layer via the first passivation layer; and / or A second passivation layer is disposed between the second doped layer and the silicon substrate, and the second doped layer is indirectly conductively contacted with the first doped layer through the second passivation layer.
10. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 9.
11. A photovoltaic system, characterized in that: The photovoltaic module according to claim 10 is included.