Array substrate, display panel, display device and electronic device

Abstract

The utility model provides an array substrate. The array substrate comprises a substrate; the stacking structure is arranged on the substrate; and a plurality of first substrate spacers. The array substrate further comprises a plurality of pixel opening areas and spacer areas located between the adjacent pixel opening areas, and the height of the stacking structures arranged in the spacer areas is larger than that of the stacking structures arranged in the pixel opening areas. The plurality of first substrate spacers are arranged in the spacer regions, and the stacked structures of the spacer regions comprise metal spacer layers located at the upper parts at the positions where the first substrate spacers are arranged; and the plurality of first substrate spacers comprise a part of the stacked structure of the metal spacer layer in the orthographic projection area on the substrate, which is higher than the stacked structure in the pixel opening area. The utility model further provides a display panel, a display device, an electronic device, a manufacturing method of the array substrate and a manufacturing method of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof, a display device, and an electronic device. Background Art

[0002] A liquid crystal display panel generally includes an array substrate and a color film (CF) substrate that are paired together, and liquid crystal is filled between the array substrate and the color film substrate. To maintain the stability of the liquid crystal display panel and the uniformity of the cell thickness, a plurality of photospacers (PS) for supporting the array substrate and the color film substrate are usually provided between the array substrate and the color film substrate. By providing a plurality of photospacers, the uniformity of the overall thickness of the liquid crystal display panel and the tolerance of the liquid crystal display panel to liquid crystal fluctuations can be improved, thereby improving the yield of the liquid crystal display panel.

[0003] In the manufacturing process of a liquid crystal display panel, an organic layer (ORG) coating process is adopted. Due to the leveling effect of the organic film layer, the position occupied by the photospacer in the conventional photospacer design is relatively flat. When the display panel is pressed, the photospacer on the color film substrate side will slide into the opening area of the thin film transistor (TFT), scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus forming light leakage, resulting in photospacer-related non-uniformity (PS Mura). In addition, in the existing solutions, the photospacers on both the array substrate side and the color film substrate side are completed by the factory manufacturing the color film substrate, which greatly affects the production capacity. Summary of the Utility Model

[0004] The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a manufacturing method thereof, a display device, and an electronic device to ensure that the photospacer on the color film substrate side is not easily slid when the display panel is pressed, thereby avoiding the generation of PS Mura.

[0005] An embodiment of the present disclosure provides an array substrate, including: a substrate; a stacked structure disposed on the substrate; and a plurality of first substrate photospacers, wherein the array substrate further includes a plurality of pixel opening areas and a spacer area between adjacent pixel opening areas, the height of the stacked structure disposed in the spacer area is greater than the height of the stacked structure disposed in the pixel opening area, the plurality of first substrate photospacers are disposed in the spacer area, the stacked structure in the spacer area at the position where the first substrate photospacers are disposed includes a metal spacer layer at the upper part, and the plurality of first substrate photospacers include the part where the stacked structure in the positive projection area of the metal spacer layer on the substrate is higher than the stacked structure in the pixel opening area.

[0006] According to an embodiment of the present disclosure, the array substrate further includes: a plurality of data lines extending in a first direction; and a plurality of gate lines extending in a second direction intersecting the first direction, and a positive projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps a positive projection of one of the plurality of data lines on the substrate.

[0007] According to an embodiment of the present disclosure, the plurality of first substrate spacers include first spacers corresponding to main spacers on the color filter substrate and second spacers corresponding to auxiliary spacers on the color filter substrate.

[0008] According to an embodiment of the present disclosure, a dimension of the second spacer in the first direction is smaller than a dimension of the first spacer in the first direction, or a dimension of the second spacer in the second direction is larger than a dimension of the first spacer in the second direction.

[0009] According to an embodiment of the present disclosure, at least part of the second spacer has a dimension in the first direction smaller than that of the first spacer in the first direction, and at least part of the second spacer has a dimension in the second direction larger than that of the first spacer in the second direction.

[0010] According to an embodiment of the present disclosure, the second spacer includes a main spacer and sub-spacers disposed on both sides of the main spacer in the first direction, and a positive projection of the sub-spacer on the substrate at least partially overlaps a positive projection of one of the plurality of gate lines on the substrate.

[0011] According to an embodiment of the present disclosure, the sub-spacer includes a plurality of sub-spacers disposed in the second direction.

[0012] According to an embodiment of the present disclosure, the sub-spacer is located at a higher level than the main spacer in a direction perpendicular to the substrate.

[0013] According to an embodiment of the present disclosure, the first spacers disposed in the same row in the second direction are aligned in the second direction, and at least one second spacer and other second spacers disposed in the same row in the second direction are not aligned in the second direction.

[0014] According to an embodiment of the present disclosure, at least one second spacer and the first spacer disposed in the same row in the second direction are not aligned in the second direction.

[0015] An embodiment of the present disclosure provides a display panel, including: a first substrate; and a second substrate disposed opposite to the first substrate. The first substrate includes: a first substrate; a stacked structure disposed on the first substrate facing the second substrate; and a plurality of first substrate spacers. The second substrate includes: a second substrate; a black matrix disposed on the second substrate facing the first substrate; and a plurality of second substrate spacers disposed on the black matrix. The plurality of first substrate spacers correspond to the plurality of second substrate spacers one by one. The first substrate includes a plurality of pixel opening regions and a spacer region between adjacent pixel opening regions, and the height of the stacked structure disposed in the spacer region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers are disposed in the spacer region, and the stacked structure in the spacer region includes a metal spacer layer at the position where the first substrate spacer is disposed, and the plurality of first substrate spacers include the stacked structure in the orthographic projection region of the metal spacer layer on the substrate, which is higher than the stacked structure in the pixel opening region.

[0016] According to an embodiment of the present disclosure, the first substrate further includes a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction intersecting with the first direction. The orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines on the first substrate, and the orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of the corresponding second substrate spacer among the plurality of second substrate spacers on the first substrate.

[0017] According to an embodiment of the present disclosure, the plurality of second substrate spacers include a main spacer and an auxiliary spacer, and the height of the main spacer in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer in the third direction. The plurality of first substrate spacers include a first spacer corresponding to the main spacer and a second spacer corresponding to the auxiliary spacer.

[0018] According to an embodiment of the present disclosure, the size of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, or the size of the second spacer in the second direction is greater than the size of the first spacer in the second direction.

[0019] According to an embodiment of the present disclosure, at least part of the size of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, and at least part of the size of the second spacer in the second direction is greater than the size of the first spacer in the second direction.

[0020] According to an embodiment of the present disclosure, the second spacer includes a main spacer and auxiliary spacers disposed on both sides of the main spacer in the first direction, and a positive projection of the auxiliary spacer on the first substrate at least partially overlaps with a positive projection of one of the plurality of gate lines on the first substrate.

[0021] According to an embodiment of the present disclosure, the auxiliary spacer includes a plurality of sub-spacers disposed in the second direction.

[0022] According to an embodiment of the present disclosure, the auxiliary spacer is located at a higher level than the main spacer in the third direction.

[0023] According to an embodiment of the present disclosure, the first spacers disposed in the same row in the second direction are aligned in the second direction, and at least one second spacer and other second spacers disposed in the same row in the second direction are not aligned in the second direction.

[0024] According to an embodiment of the present disclosure, at least one second spacer and the first spacer disposed in the same row in the second direction are not aligned in the second direction.

[0025] According to an embodiment of the present disclosure, the first substrate is an array substrate, and the second substrate is a color filter substrate.

[0026] According to an embodiment of the present disclosure, the color filter substrate further includes a plurality of color resist layers disposed between the black matrices.

[0027] According to an embodiment of the present disclosure, the plurality of color resist layers include: a blue color resist layer, a green color resist layer, and a red color resist layer.

[0028] An embodiment of the present disclosure further provides a display device, including a display panel according to an embodiment of the present disclosure.

[0029] An embodiment of the present disclosure further provides an electronic device, including a display device according to an embodiment of the present disclosure.

[0030] An embodiment of the present disclosure further provides a method for manufacturing an array substrate, including: preparing a substrate; preparing a stacked structure on the substrate; and forming a plurality of first substrate spacers through the stacked structure, wherein the array substrate includes a plurality of pixel opening regions and a spacer region located between adjacent pixel opening regions, a height of the stacked structure disposed in the spacer region is greater than a height of the stacked structure disposed in the pixel opening region, the plurality of first substrate spacers are disposed in the spacer region, and forming a plurality of first substrate spacers through the stacked structure includes: forming a metal spacer layer on an upper portion of the stacked structure in the spacer region where the plurality of first substrate spacers are to be formed through a metal exposure process.

[0031] An embodiment of the present disclosure also provides a method for manufacturing a display panel, including: preparing a first substrate; preparing a second substrate; and aligning the first substrate with the second substrate to form the display panel. Preparing the first substrate includes: preparing a first substrate; preparing a stacked structure on the first substrate; and forming a plurality of first substrate spacers through the stacked structure. Preparing the second substrate includes: preparing a second substrate; preparing a black matrix on the second substrate; and preparing a plurality of second substrate spacers on the black matrix. The plurality of first substrate spacers correspond to the plurality of second substrate spacers one by one. The first substrate includes a plurality of pixel opening regions and a spacer region between adjacent pixel opening regions, and the height of the stacked structure disposed in the spacer region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers are disposed in the spacer region, and forming a plurality of first substrate spacers through the stacked structure includes: forming a metal spacer layer on the upper portion of the stacked structure in the spacer region where the plurality of first substrate spacers are to be formed through a metal exposure process.

[0032] For the array substrate and its manufacturing method, the display panel and its manufacturing method, the display device and the electronic device according to the embodiments of the present disclosure, since the spacers on the array substrate side include a metal spacer layer, the friction with the corresponding spacers on the color filter substrate side can be increased, so as to ensure that the spacers on the color filter substrate side are not easily slid when the display panel is pressed, thereby avoiding the generation of PS Mura. In addition, a high-performance exposure machine in the factory for manufacturing the array substrate can be utilized to achieve precise control of various forms of the spacers, improving the accuracy of the solution. Description of the Drawings

[0033] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. They are used together with the embodiments of the present disclosure to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed exemplary embodiments with reference to the drawings, the above and other features and advantages will become more apparent to those skilled in the art. In the drawings:

[0034] Figure 1A is a cross-sectional schematic view of an array substrate according to an embodiment of the present disclosure;

[0035] Figure 1B is another cross-sectional schematic view of an array substrate according to an embodiment of the present disclosure;

[0036] Figure 2A is a cross-sectional schematic view of a display panel according to an embodiment of the present disclosure;

[0037] Figure 2B is another cross-sectional schematic view of a display panel according to an embodiment of the present disclosure;

[0038] Figure 3 A top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0039] Figure 4 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0040] Figure 5A Another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0041] Figure 5B It is along Figure 5A The cross-sectional schematic diagram taken along the line AA in;

[0042] Figure 6 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0043] Figure 7 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0044] Figure 8 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0045] Figure 9 Shows a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0046] Figure 10 Shows a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0047] For clarity, the drawings are not necessarily drawn to scale, and the same reference numerals will be used throughout to refer to the same or similar elements. The configurations shown in the drawings are merely examples and should not be construed in any way as limiting. Detailed Embodiments

[0048] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the display panel provided by the present disclosure, its manufacturing method, and a display device including the display panel will be described in detail below with reference to the drawings.

[0049] Hereinafter, example embodiments will be described more fully with reference to the drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0050] During the manufacturing process of a liquid crystal display panel, an organic film coating process is usually adopted. Due to the leveling effect of the organic film layer, the area occupied by the spacers is relatively flat. When the display panel is pressed, the spacers on the color filter substrate side will slide into the opening area of the thin film transistor, scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus forming light leakage, resulting in PS Mura.

[0051] For the display panel according to an embodiment of the present disclosure, the spacers on the array substrate side are formed of a metal layer, so as to increase the distance between the alignment layer of the array substrate and the spacers on the color filter substrate side, ensuring that when the display panel is pressed, the spacers on the color filter substrate side are not likely to come into contact with the alignment layer of the array substrate when sliding, thereby avoiding the generation of PS Mura; at the same time, the spacers on the array substrate side are formed of a metal layer, which can make the fabricated pattern more precise and have less impact on the aperture ratio.

[0052] Figure 1A and Figure 1B FIG. is a cross-sectional schematic view of an array substrate according to an embodiment of the present disclosure, Figure 2A and Figure 2B FIG. is a cross-sectional schematic view of a display panel according to an embodiment of the present disclosure, Figure 3 FIG. is a top view schematic view of a display panel according to an embodiment of the present disclosure.

[0053] As Figure 1A and Figure 1B shown, the array substrate according to an embodiment of the present disclosure includes a substrate, a stacked structure disposed on the substrate, and a plurality of first substrate spacers 107 formed through the stacked structure. The array substrate includes a plurality of pixel opening areas and a spacer area located between adjacent pixel opening areas. The height of the stacked structure disposed in the spacer area is greater than the height of the stacked structure disposed in the pixel opening area. The plurality of first substrate spacers 107 are disposed in the spacer area and include a metal spacer layer disposed on an upper portion of a part of the stacked structure in the spacer area, and the plurality of first substrate spacers include the part by which the stacked structure in the orthographic projection area of the metal spacer layer on the first substrate is higher than the stacked structure located in the pixel opening area.

[0054] As Figure 2A and Figure 2BAs shown, the display panel according to an embodiment of the present disclosure includes a first substrate and a second substrate disposed opposite to the first substrate. The first substrate includes a first substrate, a stacked structure disposed on the first substrate facing the second substrate, and a plurality of first substrate spacers 107 formed through the stacked structure. The second substrate includes a second substrate, a black matrix disposed on the second substrate facing the first substrate, and a plurality of second substrate spacers 108 disposed on the black matrix. The plurality of first substrate spacers 107 correspond to the plurality of second substrate spacers 108 one by one. The first substrate includes a plurality of pixel opening regions and a spacer region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacer region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers 107 are disposed in the spacer region and include a metal spacer layer disposed on an upper portion of a part of the stacked structure in the spacer region, and the plurality of first substrate spacers include the part by which the stacked structure in the orthographic projection region of the metal spacer layer on the first substrate is higher than the stacked structure located in the pixel opening region.

[0055] In the context of the present disclosure, the spacer including the metal spacer layer is referred to as a metal spacer (Metal PS, MPS).

[0056] According to an embodiment of the present disclosure, as Figure 1A and Figure 2A shown, the first substrate may be a glass substrate, and the stacked structure of the spacer region (or wiring region) formed on the first substrate may sequentially include: a gate layer (Gate), a gate insulating layer (GI), an active layer (IGZO), a source-drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a metal spacer layer, and a second dielectric layer (PVX2). In some embodiments, the metal oxide layer (ITO) and the metal spacer layer are in direct contact to achieve electrical connection between the metal oxide layer (ITO) and the metal spacer layer.

[0057] According to an embodiment of the present disclosure, as Figure 1B and Figure 2B shown, the first substrate may be a glass substrate, and the stacked structure of the spacer region (or wiring region) formed on the first substrate may sequentially include: a gate layer (Gate), a gate insulating layer (GI), an active layer (IGZO), a source-drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a second dielectric layer (PVX2), and a metal spacer layer.

[0058] Referring to Figures 1A to 2B , the stacked structure of the pixel opening region formed on the first substrate may sequentially include: a gate insulating layer (GI), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), and a second dielectric layer (PVX2). In addition,Figures 1A to 2B It is also shown that the first substrate and the second substrate respectively include an alignment layer (PI). The alignment layer of the first substrate covers the first substrate spacer 107 and the stacked structure, and the alignment layer of the second substrate covers the second substrate spacer 108 and the black matrix.

[0059] As Figures 1A to 2B shown, the stacked structure formed in the pixel opening region on the substrate does not include a gate layer (Gate), a source-drain layer (SD), and a metal spacer layer. Since there is a height difference between the stacked structure formed in the spacer region and the stacked structure formed in the pixel opening region, the first substrate spacer 107 (MPS) can be formed by the stacked structure in the spacer region. The height of the first substrate spacer 107 is determined by the heights of the gate layer (Gate), the source-drain layer (SD), and the metal spacer layer. That is to say, when the thickness of the same film layer is the same, the height difference formed by the remaining film layers constitutes the first substrate spacer 107.

[0060] In addition to Figures 1A to 2B the exemplary stacked structure shown, the stacked structure formed in the spacer region may further include other layers not shown in the figure. Similarly, the stacked structure formed in the pixel opening region may also further include other layers not shown in the figure. For example, although not shown in the figure, those skilled in the art should understand that a second metal oxide layer may also be formed in the pixel opening region, and the second metal oxide layer may be formed on the first substrate or on the second substrate.

[0061] See Figure 2A and Figure 2B , liquid crystal (not shown) can be filled between the first substrate and the second substrate and a display panel can be formed after cell alignment. At the position corresponding to the pixel opening region, the thickness of the liquid crystal layer (i.e., cell gap, CG) can be appropriately configured with various sizes according to specific process requirements.

[0062] According to an embodiment of the present disclosure, as Figure 2A and Figure 2B shown, the second substrate may be a glass substrate, the black matrix may be formed on the second substrate, the second substrate spacer 108 may be formed on the black matrix, and each second substrate spacer 108 corresponds to the first substrate spacer 107 on the first substrate one by one. The orthographic projection of the black matrix on the first substrate at least partially overlaps with the stacked structure formed in the spacer region on the first substrate. In some embodiments, the orthographic projection of the black matrix on the first substrate completely covers the stacked structure formed in the spacer region on the first substrate.

[0063] According to an embodiment of the present disclosure, as Figure 2A and Figure 2BAs shown, a plurality of second substrate spacers 108 include main spacers 1081 and auxiliary spacers 1082. The height of the main spacer 1081 in the third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer 1082 in the third direction. The plurality of first substrate spacers 107 include a first spacer 1071 corresponding to the main spacer 1081 and a second spacer 1072 corresponding to the auxiliary spacer 1082.

[0064] According to an embodiment of the present disclosure, the first substrate may be an array substrate, and the second substrate may be a color filter substrate.

[0065] Referring to Figure 2A and Figure 2B , the second substrate may be a color filter substrate. In addition to Figure 2A and Figure 2B the second substrate, black matrix, and the second substrate spacers 108 formed on the black matrix shown, the second substrate may further include a plurality of color resist layers (not shown) disposed between the black matrices. The black matrix on the second substrate corresponds to the spacer region (or wiring region) of the first substrate, and the plurality of color resist layers on the second substrate correspond to the pixel opening regions of the first substrate. The plurality of color resist layers may include color resist layers of different colors, for example, a blue color resist layer, a green color resist layer, and a red color resist layer.

[0066] According to an embodiment of the present disclosure, as Figure 3 shown, the first substrate further includes a plurality of data lines 101 extending in the first direction D1 and a plurality of gate lines 102 extending in a second direction D2 intersecting the first direction D1. The orthographic projection of each first substrate spacer 107 among the plurality of first substrate spacers 107 on the first substrate at least partially overlaps with the orthographic projection of one data line 101 among the plurality of data lines 101 on the first substrate, and the orthographic projection of each first substrate spacer 107 among the plurality of first substrate spacers 107 on the first substrate at least partially overlaps with the orthographic projection of the corresponding second substrate spacer 108 among the plurality of second substrate spacers 108 on the first substrate.

[0067] Referring to Figure 3, the first substrate may further include a common electrode line 103 and a common via 105, and the common electrode line 103 is connected to the common electrode 110 via the common connection hole 105. In some embodiments, the common electrode 110 is in direct contact with the metal spacer layer to achieve electrical connection between the common electrode 110 and the metal spacer layer, thereby reducing the resistance of the common electrode 110 and preventing the metal spacer layer from floating. In addition, the first substrate may further include a plurality of thin film transistors 104, the data line 101 is connected to the source electrode of the thin film transistor 104, the gate line 102 is connected to the gate electrode of the thin film transistor 104, the drain electrode of the thin film transistor 104 is connected to a pixel electrode (not shown in the figure) via a drain via 106, and the thin film transistor 104 includes an active layer 109. Figure 3 It shows that the first substrate includes a metal oxide layer, and the metal oxide layer can be used as the common electrode 110. The material of the metal oxide layer may include a transparent oxide, for example, indium tin oxide (ITO).

[0068] As Figure 3 shown, the width of the first substrate spacer 107 in the second direction D2 is wider than that of the data line 101. Generally, the width of the data line can be, for example, about 3 μm, and the width of the first substrate spacer 107 can be, for example, about 15 μm. The length of the first substrate spacer 107 in the first direction D1 can be, for example, about 30 μm. For example, the first substrate spacer 107 can be formed into 14 μm × 28 μm (the dimension in the second direction D2 × the dimension in the first direction D1). It should be recognized that the specific values shown are only examples, and those skilled in the art can appropriately configure various dimensions according to specific process requirements. In some embodiments, both ends of the first substrate spacer 107 in the first direction D1 can at least partially overlap the gate line 102 and the common electrode line 103 respectively, so the height of these two ends can be increased to block the sliding of the second substrate spacer 108. In some embodiments, both ends of the first substrate spacer 107 in the first direction D1 can respectively extend beyond the regions of the gate line 102 and the common electrode line 103, increasing the length of the first substrate spacer 107 in the first direction D1, which can prevent the second substrate spacer 108 from slipping out and basically does not reduce the aperture ratio.

[0069] As Figure 3 shown, the data line 101 forms a bend at the position of the spacer, such that the distances from the center of the data line 101 in the second direction D2 to two adjacent drain vias 106 are substantially the same, and the distances from the center of the first substrate spacer 107 in the second direction D2 to two adjacent drain vias 106 are also substantially the same.

[0070] According to an embodiment of the present disclosure, when no external force is applied to the display panel, there is a certain mutual extrusion force between the main spacer 1081 and the convex portion formed by the corresponding first spacer 1071, which can improve the ability of the display panel to resist external forces and enhance the stability of the display panel. When the display panel is externally squeezed, the main spacer 1081 is further compressed, causing the auxiliary spacer 1082 to contact the corresponding second spacer 1072 to further provide support for the display panel. For example, when the main spacer 1081 and the first spacer 1071 are mutually squeezed, the first spacer 1071 is deformed to protrude toward the first substrate under the extrusion of the main spacer 1081. Since the first spacer 1071 includes a metal spacer layer provided on the upper part, and the morphology of the metal spacer layer can be precisely controlled through a metal exposure process, the friction force between the first spacer 1071 and the main spacer 1081 is increased, ensuring that when the display panel is externally squeezed, the main spacer 1081 is not prone to sliding, thereby preventing the spacer from sliding into the opening area of the thin film transistor 104 and scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus forming light leakage, resulting in PS Mura. In addition, since a high-performance exposure machine in the factory for manufacturing the array substrate can be used to form the metal spacer layer through the metal exposure process, precise control of various forms of the spacer can be achieved, improving the accuracy of the solution.

[0071] According to an embodiment of the present disclosure, as Figure 3 shown, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1 can be smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1.

[0072] Referring to Figure 3 , the main spacer 1081 located at the central position and the auxiliary spacers 1082 located on both sides of the main spacer 1081 are shown in the figure. For example, the first spacer 1071 corresponding to the main spacer 1081 can be formed as 14 μm × 28 μm (size in the second direction D2 × size in the first direction D1), and the second spacer 1072 corresponding to the auxiliary spacer 1082 can be formed as 14 μm × 15 μm (size in the second direction D2 × size in the first direction D1). It should be recognized that the specific values shown are only examples, and those skilled in the art can appropriately configure various sizes according to specific process requirements.

[0073] According to an embodiment of the present disclosure, by reducing the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1, the aperture ratio (AR) can be maximized.

[0074] According to an embodiment of the present disclosure, by increasing the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1, the sliding distance of the auxiliary spacer can be increased to prevent the spacer from slipping.

[0075] As Figure 3 shown, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be substantially equal to the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2, but the present disclosure is not limited thereto. Refer to Figure 4 , according to an embodiment of the present disclosure, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be greater than or less than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2. In some embodiments, the second spacer 1072 can include both a second spacer 1072 whose size in the second direction D2 is greater than the size of the first spacer 1071 in the second direction D2 and a second spacer 1072 whose size in the second direction D2 is less than the size of the first spacer 1071 in the second direction D2. In some embodiments, among the two second spacers 1072 adjacent to both sides of the first spacer 1071, the size of one second spacer 1072 in the second direction D2 can be greater than the size of the first spacer 1071 in the second direction D2, and the size of the other second spacer 1072 in the second direction D2 can be less than the size of the first spacer 1071 in the second direction D2.

[0076] According to an embodiment of the present disclosure, when designing the positions of the first substrate spacers 107 corresponding to the main spacer 1081 and the auxiliary spacer 1082, it is necessary to avoid the vias beside (including, for example, the common via 105 and the drain via 106) so as to leave a gap with the vias. Therefore, when designing the shape of the first substrate spacer 107, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be appropriately increased under the condition of leaving enough gaps with the vias on both sides to increase the contact area with the auxiliary spacer 1082, thereby increasing the friction force. For example, the first spacer 1071 corresponding to the main spacer 1081 can be formed as 14 μm × 28 μm (size in the second direction D2 × size in the first direction D1), and the second spacer 1072 corresponding to the auxiliary spacer 1082 can be formed as 27.5 μm × 15 μm or 23.5 μm × 15 μm (size in the second direction D2 × size in the first direction D1). It should be recognized that the specific values shown are only examples, and those skilled in the art can appropriately configure various sizes according to specific process requirements.

[0077] According to an embodiment of the present disclosure, it is possible to make only the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1. Alternatively, it is possible to make only the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 larger than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1. Alternatively, it is possible to make the size of at least one second spacer 1072 corresponding to the auxiliary spacer 1082 larger than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1, and make the size of at least one second spacer 1072 corresponding to the auxiliary spacer 1082 smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1.

[0078] According to an embodiment of the present disclosure, it is possible to make the size of at least one second spacer 1072 corresponding to the auxiliary spacer 1082 larger than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2. Alternatively, it is possible to make the size of at least one second spacer 1072 corresponding to the auxiliary spacer 1082 smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2.

[0079] According to an embodiment of the present disclosure, it is possible to make both the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1, and make the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 larger than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2.

[0080] Figure 5A Another top view schematic diagram of a display panel according to an embodiment of the present disclosure.

[0081] As Figure 5A shown, compared with the embodiment shown in Figure 3 In the embodiment shown in Figure 5A the second spacer 1072 corresponding to the auxiliary spacer 1082 includes a main spacer 10721, and auxiliary spacers 10722 disposed on both sides of the main spacer 10721 in the first direction D1. The orthographic projection of the auxiliary spacer 10722 on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of gate lines 102 on the first substrate. In Figure 5AThe main spacer 1081 is shown at the central position, and the auxiliary spacers 1082 are located on both sides of the main spacer 1081.

[0082] According to an embodiment of the present disclosure, the sub-spacer 10722 can be used as a retaining wall to block the sliding of the auxiliary spacer 1082 in the first direction D1. As Figure 5A shown, the positive projection of the retaining wall formed by the sub-spacer 10722 on the first substrate can at least partially overlap with the positive projection of one of the plurality of gate lines 102 on the first substrate, and / or can at least partially overlap with the positive projection of the common electrode line 103 on the first substrate.

[0083] According to an embodiment of the present disclosure, referring to Figure 5B , the sub-spacer 10722 can be at a higher level than the main spacer 10721 in the direction perpendicular to the first substrate, so as to better block the sliding of the auxiliary spacer 1082 in the first direction D1.

[0084] It should be recognized that, for clarity, only the auxiliary spacer 1082 and the corresponding second spacer 1702 corresponding to the auxiliary spacer 1082 are schematically shown in the cross-sectional view of Figure 5B . The alignment layer covering the spacer is not shown, nor is the stack structure and the black matrix shown. In addition, the metal spacer layer on the upper part of the second spacer 1702 is schematically used to represent the second spacer 1702. Those skilled in the art should also recognize that although Figure 5B shows that the sub-spacer 10722 can be at a higher level than the main spacer 10721 in the direction perpendicular to the first substrate, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the sub-spacer 10722 can be at the same level as the main spacer 10721 in the direction perpendicular to the first substrate.

[0085] As Figure 6 shown, the sub-spacer 10722 can be provided only on one side of the main spacer 10721 in the first direction D1.

[0086] According to an embodiment of the present disclosure, as Figure 5A and Figure 6 shown, the width of the sub-spacer 10722 in the second direction D2 is substantially the same as the width of the main spacer 10721 in the second direction D2. Alternatively, the width of the sub-spacer 10722 in the second direction D2 can be different from the width of the main spacer 10721 in the second direction D2, greater than or less than the width of the main spacer 10721 in the second direction D2. It should be recognized that those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0087] Figure 7 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure.

[0088] As Figure 7 shown, compared with the embodiment shown in Figure 5A , in the embodiment shown in Figure 7 , the second spacer 1072 corresponding to the auxiliary spacer 1082 includes a main spacer 10721 and sub-spacers 10722' disposed on both sides of the main spacer 10721 in the first direction D1. Among them, the sub-spacers 10722' include a plurality of sub-spacers disposed in the second direction D2. In Figure 7 , the main spacer 1081 located at the central position and the auxiliary spacers 1082 located on both sides of the main spacer 1081 are shown.

[0089] According to an embodiment of the present disclosure, the sub-spacers 10722' can be formed into a plurality of sub-spacers, which is beneficial to the recovery after the spacer is displaced. As Figure 7 shown, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be appropriately adjusted according to the specific positions of the vias (including, for example, the common via 105 and the drain via 106). For example, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side in the figure in the second direction D2 can be formed as large as possible under the condition of avoiding the vias, so as to increase the contact area with the auxiliary spacer 1082, thereby increasing the friction force. For example, the distance between the two vias (two drain vias 106) shown on the left side in the figure can be 33.55 μm. Therefore, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 is formed as 23.4 μm, that is, the size of the main spacer 10721 in the second direction D2 is formed as 23.4 μm, and the sub-spacers 10722' can be formed into three sub-spacers.

[0090] For example, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side in the figure in the second direction D2 can be smaller than the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side in the figure in the second direction D2 when the via holes are avoided. For example, the distance between the two via holes (drain via hole 106 and common via hole 105) shown on the right side in the figure can be 24.55 μm. Therefore, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 is formed to be 14.4 μm, that is, the size of the main spacer 10721 in the second direction D2 is formed to be 14.4 μm, and the sub-spacer 10722' can be formed into two sub-spacers. Therefore, the number of sub-spacers included in the sub-spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side in the figure can be different from the number of sub-spacers included in the sub-spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side in the figure. Specifically, the number of sub-spacers included in the sub-spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side in the figure can be greater than the number of sub-spacers included in the sub-spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side in the figure. It should be recognized that the specific values shown are only examples, and those skilled in the art can appropriately configure various sizes and the number of sub-spacers according to specific process requirements.

[0091] Alternatively, the sub-spacer 10722' can be provided only on one side of the main spacer 10721 in the first direction D1, and the sub-spacer 10722' can be formed into multiple sub-spacers.

[0092] Alternatively, the sub-spacer 10722' can be provided on one side of the main spacer 10721 in the first direction D1, the sub-spacer 10722' can be formed into multiple sub-spacers, and the sub-spacer 10722 as shown in Figure 5A and Figure 6 can be provided on the other side of the main spacer 10721 in the first direction D1.

[0093] According to an embodiment of the present disclosure, as shown in Figure 7 , the width of the sub-spacer 10722' in the second direction D2 is substantially the same as the width of the main spacer 10721 in the second direction D2. Alternatively, the width of the sub-spacer 10722' in the second direction D2 can be different from the width of the main spacer 10721 in the second direction D2, greater than or less than the width of the main spacer 10721 in the second direction D2. It should be recognized that those skilled in the art can appropriately configure various sizes according to specific process requirements.

[0094] According to an embodiment of the present disclosure, the first substrate spacer 107 is formed as a metal spacer including a metal spacer layer. Therefore, a high-performance exposure machine in a factory for manufacturing an array substrate can be used to form the metal spacer layer through a metal exposure process, so as to achieve precise control of various forms of the spacer and improve the accuracy of the solution.

[0095] Figure 8 Another top view schematic diagram of a display panel according to an embodiment of the present disclosure.

[0096] As Figure 8 shown, compared with the embodiment shown in Figure 3 , in the embodiment shown in Figure 8 , each of the first substrate spacers 107 (including the first spacer 1071 and the second spacer 1072) provided in the same row is not aligned in the second direction D2.

[0097] Specifically, referring to Figure 8 , in the same row, each of the first spacers 1071 corresponding to the main spacer 1081 may be aligned in the second direction D2, at least one of the second spacers 1072 corresponding to the auxiliary spacer 1082 and the other second spacers 1072 corresponding to the auxiliary spacer 1082 may not be aligned in the second direction D2, and at least one of the second spacers 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 may not be aligned in the second direction D2. In Figure 8 , the main spacer 1081 located at the central position and the auxiliary spacers 1082 located on both sides of the main spacer 1081 are shown. It should be recognized that the "alignment" described herein specifically refers to the center alignment of components.

[0098] Although in Figure 8 , the second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 are shown to have different sizes in the first direction D1, the present disclosure is not limited thereto, and the second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 may have the same size in the first direction D1. Although in Figure 8 , the second spacer 1072 corresponding to the auxiliary spacer 1082 is shown not to include a main spacer and a sub-spacer, the present disclosure is not limited thereto, and the second spacer 1072 corresponding to the auxiliary spacer 1072 may include a main spacer 10721 and a sub-spacer 10722 as shown in Figure 5A and Figure 6 and / or a main spacer 10721 and a sub-spacer 10722' as shown in Figure 7 .

[0099] By setting the second spacer 1072 corresponding to the auxiliary spacer 1082 to be misaligned with the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2 and including different offset directions, it can be ensured that at least partial support of the second spacer 1072 can be obtained when the auxiliary spacer 1082 is offset in a certain direction, and the total area of the second spacer 1072 can also be reduced, improving the aperture ratio.

[0100] According to an embodiment of the present disclosure, a display device is further provided, including a display panel according to each embodiment of the present disclosure.

[0101] According to an embodiment of the present disclosure, an electronic device is further provided, including a display device according to an embodiment of the present disclosure, which includes a display panel according to each embodiment of the present disclosure.

[0102] Since a display panel according to an embodiment of the present disclosure is adopted, when the display panel is not externally squeezed, there is a certain mutual extrusion force between the convex portions formed by the main spacer and the corresponding first spacer, which can improve the ability of the display panel to resist external forces and improve the stability of the display panel. When the display panel is externally squeezed, the main spacer is further compressed, so that the auxiliary spacer contacts the corresponding second spacer to further provide support for the display panel. Since the first substrate spacer includes a metal spacer layer disposed on the upper portion, the friction force between the first substrate spacer and the corresponding second substrate spacer is increased, ensuring that the second substrate spacer is not easily slid when the display panel is externally squeezed, thereby preventing the spacer from sliding into the opening area of the thin film transistor and scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus forming light leakage and PS Mura. In addition, since a high-performance exposure machine in the factory for manufacturing the array substrate can be used to form the metal spacer layer through a metal exposure process, precise control of various forms of the spacer can be achieved, improving the accuracy of the solution.

[0103] Figure 9 A flowchart showing a manufacturing method of an array substrate according to an embodiment of the present disclosure is shown.

[0104] As Figure 9 shown, the manufacturing method of the array substrate according to an embodiment of the present disclosure includes the following steps S11 to S13.

[0105] In step S11, a substrate is prepared.

[0106] In step S12, a stacked structure is prepared on the substrate.

[0107] In step S13, a plurality of first substrate spacers are formed through the stacked structure.

[0108] According to an embodiment of the present disclosure, the array substrate includes a plurality of pixel opening regions and a spacer region located between adjacent pixel opening regions. The height of the stacked structure provided in the spacer region is greater than the height of the stacked structure provided in the pixel opening region. A plurality of first substrate spacers are provided in the spacer region, and forming a plurality of first substrate spacers through the stacked structure (i.e., step S13) includes: forming a metal spacer layer on the upper portion of the stacked structure in the spacer region where a plurality of first substrate spacers are to be formed through a metal exposure process.

[0109] In the method for manufacturing an array substrate according to an embodiment of the present disclosure, since a metal spacer layer is formed on the upper portion of the stacked structure in the spacer region where a plurality of first substrate spacers are to be formed through a metal exposure process, the friction between the first substrate spacers and the corresponding second substrate spacers is increased. This ensures that when the display panel is externally squeezed, the second substrate spacers are not easily slid, thereby preventing the spacers from sliding into the opening region of the thin film transistor and scratching the alignment layer in the opening region, which affects the liquid crystal alignment and thus causes light leakage and PS Mura. In addition, since a high-performance exposure machine in the factory for manufacturing the array substrate can be used to form the metal spacer layer through the metal exposure process, precise control of various forms of the spacers can be achieved, improving the accuracy of the solution.

[0110] Figure 10 The flowchart showing the method for manufacturing a display panel according to an embodiment of the present disclosure is presented.

[0111] As Figure 10 shown, the method for manufacturing a display panel according to an embodiment of the present disclosure includes the following steps S100 to S300.

[0112] In step S100, a first substrate is prepared.

[0113] In step S200, a second substrate is prepared.

[0114] In step S300, the first substrate and the second substrate are paired to form a display panel.

[0115] Preparing the first substrate (i.e., step S100) includes the following steps S110 to S130.

[0116] In step S110, a first substrate is prepared.

[0117] In step S120, a stacked structure is prepared on the first substrate.

[0118] In step S130, a plurality of first substrate spacers are formed through the stacked structure.

[0119] Preparing the second substrate (i.e., step S200) includes the following steps S210 to S230.

[0120] In step S210, a second substrate is prepared.

[0121] In step S220, a black matrix is prepared on the second substrate.

[0122] In step S230, a plurality of second substrate spacers are prepared on the black matrix.

[0123] According to an embodiment of the present disclosure, the plurality of first substrate spacers and the plurality of second substrate spacers correspond to each other one by one. The first substrate includes a plurality of pixel opening regions and a spacer region between adjacent pixel opening regions. The height of the stacked structure provided in the spacer region is greater than the height of the stacked structure provided in the pixel opening region. The plurality of first substrate spacers are provided in the spacer region, and forming the plurality of first substrate spacers through the stacked structure (i.e., step S130) includes: forming a metal spacer layer on the upper part of the stacked structure in the spacer region where the plurality of first substrate spacers are to be formed by a metal exposure process.

[0124] According to the method for manufacturing a display panel of an embodiment of the present disclosure, during cell alignment, there is a certain mutual extrusion force between the second substrate spacer and the convex portion formed by the corresponding first substrate spacer. In this way, the ability of the display panel to resist external forces can be improved, and the stability of the display panel can be enhanced. Since a metal spacer layer is formed on the upper part of the stacked structure in the spacer region where the plurality of first substrate spacers are to be formed by a metal exposure process, the friction force between the first substrate spacer and the corresponding second substrate spacer is increased. It is ensured that when the display panel is externally squeezed, the second substrate spacer is not easily slid, thereby avoiding the spacer sliding into the opening region of the thin film transistor and scratching the alignment layer in the opening region, affecting the liquid crystal alignment and thus forming light leakage and PS Mura. In addition, since a high-performance exposure machine in the factory for manufacturing the array substrate can be used to form the metal spacer layer by a metal exposure process, precise control of various forms of the spacer can be achieved, and the accuracy of the solution can be improved.

[0125] For the sake of convenience of description, spatial relative terms such as "below...", "above...", "on the left side of...", "on the right side of..." may be used herein to describe the relationship between one element or feature shown in the drawings and another (some) element or feature. It should be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the figure is inverted, the element described as "below other elements or features" will thus be oriented as "above other elements or features". In this way, the exemplary term "below..." can cover both the orientation of "below..." and "above...". The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0126] For convenience of description, ordinal numbers such as "first", "second", "third", etc. may be used in this document. These ordinal numbers are only used to distinguish one element or feature from another (some) element or feature, rather than to limit the order of these elements or features.

[0127] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "consists of" are used in this specification, the specified features, wholes, steps, operations, elements, and / or components are present, but do not preclude the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof.

[0128] Exemplary embodiments have been disclosed herein, and although specific terms have been employed, they are used and are to be interpreted only in a general illustrative sense and not for purposes of limitation. In some embodiments, it will be apparent to those skilled in the art that, unless otherwise expressly stated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. An array substrate, comprising: substrate; a stacked structure disposed on the substrate; as well as a plurality of first substrate spacers, In which, the array substrate also includes a plurality of pixel opening areas and a spacing area located between adjacent pixel opening areas, the height of the stacking structure arranged in the spacing area is greater than the height of the stacking structure arranged in the pixel opening area, the plurality of first substrate spacers are arranged in the spacing area, the stacking structure in the spacing area includes a metal spacer layer located at the top at the position where the first substrate spacers are set, and the plurality of first substrate spacers include a portion of the stacking structure of the metal spacer layer within the orthographic projection area on the substrate that is higher than the stacking structure located in the pixel opening area.

2. The array substrate according to claim 1, wherein: The stack structure includes a metal oxide layer, and the metal spacer layer is directly located on the metal oxide layer.

3. The array substrate according to claim 1, wherein: The array substrate further includes: a plurality of data lines extending in a first direction; and a plurality of gate lines extending in a second direction intersecting the first direction, An orthographic projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps with an orthographic projection of one of the plurality of data lines on the substrate.

4. The array substrate according to claim 3, wherein: The plurality of first substrate spacers include first spacers corresponding to main spacers on the color filter substrate and second spacers corresponding to auxiliary spacers on the color filter substrate.

5. The array substrate according to claim 4, wherein: The size of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, or A size of the second spacer in the second direction is greater than a size of the first spacer in the second direction.

6. The array substrate according to claim 4, wherein: The size of at least part of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, and A size of at least part of the second spacers in the second direction is greater than a size of the first spacers in the second direction.

7. The array substrate according to claim 4, wherein: The second spacer includes a main spacer and auxiliary spacers arranged on both sides of the main spacer in the first direction. An orthographic projection of the sub-spacer on the substrate at least partially overlaps with an orthographic projection of one of the plurality of gate lines on the substrate.

8. The array substrate according to claim 7, wherein: The sub-spacer includes a plurality of sub-spacers arranged in the second direction.

9. The array substrate according to claim 7 or 8, wherein: The sub-spacers are located at a higher level than the main spacers in a direction perpendicular to the substrate.

10. The array substrate according to claim 4, wherein: The first spacers arranged in the same row in the second direction are aligned in the second direction, At least one second spacer arranged in the same row in the second direction and other second spacers are not aligned in the second direction.

11. A display panel, comprising: a first substrate; as well as a second substrate, which is arranged opposite to the first substrate; The first substrate comprises: a first substrate; a stacked structure disposed on the first substrate toward the second substrate; and a plurality of first substrate spacers, The second substrate comprises: a second substrate; A black matrix disposed on the second substrate toward the first substrate; and A plurality of second substrate spacers are arranged on the black matrix, Among them, the multiple first substrate spacers correspond one-to-one to the multiple second substrate spacers, the first substrate includes multiple pixel opening areas and spacing areas located between adjacent pixel opening areas, the height of the stacking structure arranged in the spacing areas is greater than the height of the stacking structure arranged in the pixel opening areas, the multiple first substrate spacers are arranged in the spacing areas, the stacking structure in the spacing areas includes a metal spacer layer located at the top at the position where the first substrate spacers are set, and the multiple first substrate spacers include a portion of the stacking structure of the metal spacer layer in the orthographic projection area on the substrate that is higher than the stacking structure located in the pixel opening area.

12. The display panel according to claim 11, wherein: The stack structure includes a metal oxide layer, and the metal spacer layer is directly located on the metal oxide layer.

13. The display panel according to claim 12, wherein: The first substrate further includes a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction intersecting the first direction. An orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with an orthographic projection of one of the plurality of data lines on the first substrate, and An orthographic projection of each first substrate spacer of the plurality of first substrate spacers on the first substrate at least partially overlaps with an orthographic projection of a corresponding second substrate spacer of the plurality of second substrate spacers on the first substrate.

14. The display panel according to claim 13, wherein: The plurality of second substrate spacers include main spacers and auxiliary spacers, wherein the height of the main spacers in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacers in the third direction. The plurality of first substrate spacers include first spacers corresponding to the main spacers and second spacers corresponding to the auxiliary spacers.

15. The display panel according to claim 14, wherein: The size of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, or A size of the second spacer in the second direction is greater than a size of the first spacer in the second direction.

16. The display panel according to claim 14, wherein: The size of at least part of the second spacer in the first direction is smaller than the size of the first spacer in the first direction, and A size of at least part of the second spacers in the second direction is greater than a size of the first spacers in the second direction.

17. The display panel according to claim 14, wherein: The second spacer includes a main spacer and auxiliary spacers arranged on both sides of the main spacer in the first direction. An orthographic projection of the sub-spacer on the first substrate at least partially overlaps with an orthographic projection of one of the plurality of gate lines on the first substrate.

18. The display panel according to claim 17, wherein: The sub-spacer includes a plurality of sub-spacers arranged in the second direction.

19. The display panel according to claim 17 or 18, wherein: The sub-spacers are located at a higher level than the main spacers in the third direction.

20. The display panel according to claim 14, wherein: The first spacers arranged in the same row in the second direction are aligned in the second direction, At least one second spacer arranged in the same row in the second direction and other second spacers are not aligned in the second direction.

21. A display device comprising the display panel according to any one of claims 11 to 20.

22. An electronic device comprising the display device according to claim 21.

Images