Mirror image LDO circuit and image sensor

Abstract

The utility model proposes a mirror image LDO circuit and an image sensor, the mirror image LDO circuit is connected by a drive circuit, a bias voltage circuit and a state feedback circuit, when the mirror image LDO circuit works in a first working state, the state feedback circuit outputs a first trigger signal to trigger the bias voltage circuit to output a first bias voltage, and when the mirror image LDO circuit works in a second working state, the mirror image LDO circuit outputs a second trigger signal to trigger the bias voltage circuit to output a second bias voltage. And when the mirror image LDO circuit works in a second working state, the state feedback circuit outputs a second trigger signal to trigger the bias voltage circuit to output a second bias voltage, the driving circuit maintains outputting the first load current after receiving the first bias voltage, and the driving circuit maintains outputting the second load current after receiving the second bias voltage. And the voltage of the output end of the driving circuit is maintained to be stabilized at the preset voltage, constant-voltage output is achieved, the output voltage of the mirror image LDO circuit is prevented from fluctuating, and therefore the working stability and reliability of the mirror image LDO circuit are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of image sensors, and particularly relates to a mirror LDO circuit and an image sensor. Background Art

[0002] A low dropout linear regulator (LDO) is a DC linear voltage regulator with an input voltage greater than the output voltage. It has the advantages of fast input-output response, low output noise, few external components, convenient use, and low price. It is widely used in automotive electronic products, portable electronic devices, communication devices, industrial and medical equipment fields. The integration of LDO circuits is also an important development direction.

[0003] Among them, the traditional mirror LDO has the advantage of a large output capacitance compatibility range, but under different load currents, the output voltage fluctuates. As Figure 1 shown, when the output load changes, the load current changes, and the output voltage of the traditional mirror LDO circuit will have a relatively obvious voltage rise or fall. The voltage fluctuation will affect the normal operation of the traditional mirror LDO circuit, resulting in abnormal operation of the traditional mirror LDO circuit. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a mirror LDO circuit, aiming to solve the problem of output voltage fluctuation existing in the traditional mirror LDO circuit.

[0005] In the first aspect of the embodiment of the utility model, a mirror LDO circuit is proposed. The mirror LDO circuit operates in a first working state of outputting a first load current or a second working state of outputting a second load current, and the first load current is greater than the second load current;

[0006] The mirror LDO circuit includes:

[0007] A driving circuit, which includes a power transistor and a first resistor connected in sequence between the positive voltage terminal and the ground terminal. The connection node of the power transistor and the first resistor constitutes the output terminal of the mirror LDO circuit and is used to output a driving power supply to the load circuit. The power transistor receives a bias voltage to generate a load current;

[0008] A bias voltage circuit, connected to the control terminal of the power transistor, outputs a first bias voltage when triggered by a first trigger signal, and outputs a second bias voltage when triggered by a second trigger signal. The absolute value of the first bias voltage is greater than the absolute value of the second bias voltage;

[0009] A state feedback circuit, connected to the bias voltage circuit, is configured to detect the state of the load circuit, and output the first trigger signal when detecting that the mirror LDO circuit is in the first operating state, and output the second trigger signal when detecting that the load circuit is in the second operating state.

[0010] Optionally, the bias voltage circuit includes:

[0011] A first bias voltage generation circuit for generating the first bias voltage;

[0012] A second bias voltage generation circuit for generating the second bias voltage;

[0013] A switch circuit, connected to the first bias voltage generation circuit, the second bias voltage generation circuit, the power transistor, and the state feedback circuit respectively. The switch circuit is triggered by the first trigger signal to connect the first bias voltage generation circuit and the power transistor, and is triggered by the second trigger signal to connect the second bias voltage generation circuit and the power transistor.

[0014] Optionally, the switch circuit includes:

[0015] A first switch, connected between the first bias voltage generation circuit and the control terminal of the power transistor. The control terminal of the first switch is connected to the state feedback circuit. The first switch is turned on by the first trigger signal and turned off by the second trigger signal. The first trigger signal and the second trigger signal are opposite level signals;

[0016] A second switch, connected between the second bias voltage generation circuit and the control terminal of the power transistor. The control terminal of the second switch is connected to the state feedback circuit. The second switch is turned on by the second trigger signal and turned off by the first trigger signal.

[0017] Optionally, the mirror LDO circuit further includes:

[0018] A delay output circuit, connected to the state feedback circuit, the first switch, and the second switch respectively. The delay output circuit is configured to delay the output of the first trigger signal and the second trigger signal to the first switch and the second switch.

[0019] Optionally, the first switch includes a first transmission gate connected between the first bias voltage generation circuit and the control terminal of the power transistor. The first transmission gate includes a first NMOS transistor and a first PMOS transistor connected in parallel;

[0020] The second switch includes a second transmission gate connected between the second bias voltage generation circuit and the control terminal of the power transistor. The second transmission gate includes a second NMOS transistor and a second PMOS transistor connected in parallel. The gates of the first NMOS transistor and the second PMOS transistor are commonly connected to form a first control terminal, and the gates of the first PMOS transistor and the second NMOS transistor are commonly connected to form a second control terminal;

[0021] The delay output circuit includes:

[0022] A delay circuit, connected between the state feedback circuit and the second control terminal, for delaying a received trigger signal by a preset duration and outputting it;

[0023] An inverter circuit, connected between the state feedback circuit and the first control terminal, for inverting and converting a received trigger signal and outputting it.

[0024] Optionally, the delay circuit includes a delay element, and the input terminal and the output terminal of the delay element respectively form the input terminal and the output terminal of the delay circuit.

[0025] Optionally, the inverter circuit includes an inverter, and the input terminal and the output terminal of the inverter respectively form the input terminal and the output terminal of the inverter.

[0026] Optionally, the first bias voltage generation circuit includes a first transistor, a second resistor, and a first operational amplifier;

[0027] The drain of the first transistor is connected to the positive voltage terminal, the gate of the first transistor is connected to the output terminal of the first operational amplifier, the source of the first transistor, the second resistor, and the inverting input terminal of the first operational amplifier are connected, the second end of the second resistor is grounded, and the non-inverting input terminal of the first operational amplifier is used for inputting a first reference voltage.

[0028] Optionally, the first bias voltage generation circuit further includes:

[0029] A plurality of first branches connected in parallel between the drain and the source of the first transistor. Each first branch includes a second transistor and a third switch connected in sequence between the drain and the source of the first transistor. The gates of the plurality of second transistors are commonly connected to the gate of the first transistor, and the plurality of third switches are triggered to conduct or turn off correspondingly by a first switch selection signal;

[0030] A plurality of second branches connected in parallel across the second resistor. Each second branch includes a fourth switch and a third resistor connected in sequence across the second resistor. The plurality of fourth switches are triggered to conduct or turn off correspondingly by a second switch selection signal.

[0031] Optionally, the second bias voltage generating circuit includes a third transistor, a fourth resistor, and a second operational amplifier;

[0032] The drain of the third transistor is connected to the positive voltage terminal, the gate of the third transistor is connected to the output terminal of the second operational amplifier, the source of the third transistor, the fourth resistor, and the inverting input terminal of the second operational amplifier are connected, the second end of the fourth resistor is grounded, and the non-inverting input terminal of the second operational amplifier is used to input a second reference voltage.

[0033] Optionally, the second bias voltage generating circuit further includes:

[0034] A plurality of third branches connected in parallel between the drain and the source of the third transistor, each third branch includes a fourth transistor and a fifth switch connected in sequence between the drain and the source of the third transistor, the gates of the plurality of fourth transistors are commonly connected to the gate of the third transistor, and the plurality of fifth switches are triggered to conduct or turn off correspondingly by a third switch selection signal;

[0035] A plurality of fourth branches connected in parallel across the fourth resistor, each fourth branch includes a sixth switch and a fifth resistor connected in sequence across the fourth resistor, and the plurality of sixth switches are triggered to conduct or turn off correspondingly by a fourth switch selection signal.

[0036] A second aspect of the embodiments of the present invention provides an image sensor, including a load circuit and the mirror image LDO circuit as described above, and the load circuit is connected to the mirror image LDO circuit.

[0037] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above mirror image LDO circuit is connected by a driving circuit, a bias voltage circuit, and a state feedback circuit. When the mirror image LDO circuit operates in the first operating state, the state feedback circuit outputs a first trigger signal to trigger the bias voltage circuit to output a first bias voltage, and when the mirror image LDO circuit operates in the second operating state, the state feedback circuit outputs a second trigger signal to trigger the bias voltage circuit to output a second bias voltage. The driving circuit maintains the output of a first load current after receiving the first bias voltage, and the driving circuit maintains the output of a second load current after receiving the second bias voltage, and maintains the output voltage of the driving circuit stable at a preset voltage, realizing constant voltage output, preventing the output voltage of the mirror image LDO circuit from fluctuating, thereby improving the working stability and reliability of the mirror image LDO circuit. Description of the Drawings

[0038] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0039] Figure 1 It is a circuit schematic diagram of a traditional mirror LDO circuit;

[0040] Figure 2 It is the first structural schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0041] Figure 3 It is a voltage waveform schematic diagram of different working states provided by the embodiment of the present invention;

[0042] Figure 4 It is the second structural schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0043] Figure 5 It is the third structural schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0044] Figure 6 It is the fourth structural schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0045] Figure 7 It is the first circuit schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0046] Figure 8 It is the structural schematic diagram of the delay output circuit provided by the embodiment of the present invention;

[0047] Figure 9 It is the second circuit schematic diagram of the mirror LDO circuit provided by the embodiment of the present invention;

[0048] Figure 10 It is the circuit schematic diagram of the first bias voltage generation circuit provided by the embodiment of the present invention;

[0049] Figure 11 It is the circuit schematic diagram of the second bias voltage generation circuit provided by the embodiment of the present invention;

[0050] Figure 12 It is the circuit schematic diagram of the state feedback circuit provided by the embodiment of the present invention. Detailed implementation manners

[0051] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0052] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.

[0053] A first aspect of an embodiment of the present utility model provides a mirror LDO circuit 100 for providing a load current to a load current. The mirror LDO circuit 100 can operate in different operating states according to a working control instruction or the state of a load circuit 200, and outputs different magnitudes of load currents in different operating states. In an alternative embodiment, the mirror LDO circuit 100 operates in a first operating state of outputting a first load current or a second operating state of outputting a second load current, where the first operating state may be a normal output state and the second operating state may be a standby state.

[0054] In the normal output state, the load current output by the mirror LDO circuit 100 is larger, and in the standby state, the load current output by the mirror LDO circuit 100 is smaller, that is, the first load current is greater than the second load current.

[0055] As Figure 1 shown, when the traditional mirror LDO circuit 100 switches from the normal output state to the standby state, the first load current drops to the second load current. Among them, the load current is related to the gate-source voltage of the power transistor Md of the mirror LDO circuit 100. When the gate voltage of the power transistor Md remains unchanged, in order to adapt to the change of the load current, the output voltage of the power transistor Md rises or falls, resulting in fluctuations in the output voltage Vo of the mirror LDO circuit 100.

[0056] Or, when the mirror LDO circuit 100 switches from the standby state to the normal output state, the second load current rises to the first load current. When the gate voltage of the power transistor Md remains unchanged, in order to adapt to the change of the load current, the output voltage of the power transistor Md drops or rises, resulting in fluctuations in the output voltage Vo of the mirror LDO circuit 100.

[0057] In order to avoid fluctuations in the output voltage caused by changes in the operating state of the mirror LDO circuit 100 and ensure the normal operation of the mirror LDO circuit 100, in this embodiment, as Figure 2As shown, the mirror LDO circuit 100 includes:

[0058] A driving circuit 10, which includes a power transistor Md and a first resistor R1 connected in sequence between the positive voltage terminal VDD and the ground terminal. The connection node of the power transistor Md and the first resistor R1 constitutes the output terminal of the mirror LDO circuit 100 and is used to output a driving power supply to the load circuit 200. The power transistor Md receives a bias voltage to generate a load current;

[0059] A bias voltage circuit 20, connected to the control terminal of the power transistor Md, outputs a first bias voltage Vgate1 when triggered by a first trigger signal, and outputs a second bias voltage Vgate2 when triggered by a second trigger signal. The absolute value of the first bias voltage Vgate1 is greater than the absolute value of the second bias voltage Vgate2;

[0060] A state feedback circuit 30, connected to the bias voltage circuit 20, is used to detect the state of the load circuit 200, and outputs a first trigger signal when it detects that the mirror LDO circuit 100 is in the first working state, and outputs a second trigger signal when it detects that the load circuit 200 is in the second working state.

[0061] In this embodiment, in the initial state, the mirror LDO circuit 100 can operate in the first working state or the second working state. Assuming that the mirror LDO circuit 100 operates in the first working state in the initial state, the bias voltage circuit 20 outputs the first bias voltage Vgate1 to the power transistor Md, and the power transistor Md triggers and outputs a first load current.

[0062] The state feedback circuit 30 can directly obtain the working control instruction of the mirror LDO or detect the state of the load circuit 200 to determine the working state of the current mirror LDO circuit 100. When it detects that the mirror LDO circuit 100 is operating in the first working state, that is, when the current mirror LDO circuit 100 outputs a first load current to the load circuit 200, the state feedback circuit 30 outputs a first trigger signal to trigger the bias voltage circuit 20 to continue to output the first bias voltage Vgate1, maintaining the output of the first load current and maintaining the output voltage of the power transistor Md constant.

[0063] When it detects that the working state of the mirror LDO circuit 100 has changed, that is, after detecting that the mirror LDO circuit 100 has switched to the second working state, at this time, the output current of the power transistor Md becomes smaller, and the state feedback circuit 30 switches to output a second trigger signal to the bias voltage circuit 20, as Figure 3As shown, the bias voltage circuit 20 switches to output a second bias voltage Vgate2 whose absolute value is less than the absolute value of the first bias voltage Vgate1 to the power transistor Md. The gate-source voltage of the power transistor Md becomes smaller, and the gate voltage of the power transistor Md becomes smaller, so that the output voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the working stability and reliability of the mirror LDO circuit 100.

[0064] And assuming that the mirror LDO circuit 100 operates in the second operating state under the initial state, the bias voltage circuit 20 outputs the second bias voltage Vgate2 to the power transistor Md, and the power transistor Md triggers to output the second load current.

[0065] When the state feedback circuit 30 detects that the mirror LDO circuit 100 operates in the second operating state, that is, when the current mirror LDO circuit 100 outputs the second load current to the load circuit 200, the state feedback circuit 30 outputs a second trigger signal to trigger the bias voltage circuit 20 to continue to output the second bias voltage Vgate2, maintaining the output of the second load current and maintaining the output voltage of the power transistor Md constant.

[0066] When detecting that the operating state of the mirror LDO circuit 100 changes, that is, after detecting that the mirror LDO circuit 100 switches to the first operating state, at this time, the output current of the power transistor Md becomes larger, and the state feedback circuit 30 switches to output a first trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 switches to output a first bias voltage Vgate1 whose absolute value is greater than the absolute value of the second bias voltage Vgate2 to the power transistor Md. The gate-source voltage of the power transistor Md becomes larger, and the gate voltage of the power transistor Md becomes larger, so that the output voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the working stability and reliability of the mirror LDO circuit 100.

[0067] Among them, the power transistor Md can be an NMOS transistor or a PMOS transistor. Assuming it is an NMOS transistor, the output current of the power transistor Md is positively correlated with the gate-source voltage, that is, the larger the gate-source voltage, the larger the output current of the power transistor Md, and the smaller the gate-source voltage, the smaller the output current of the power transistor Md. At this time, the first bias voltage Vgate1 and the second bias voltage Vgate2 are positive voltages, and the source voltage of the power transistor Md constitutes the output terminal of the mirror LDO circuit 100.

[0068] When assuming it is a PMOS transistor, the output current of the power transistor Md is negatively correlated with the gate-source voltage. Among them, the source of the PMSO transistor is connected to the positive voltage terminal VDD, and its voltage remains unchanged. The drain of the power transistor Md constitutes the output terminal of the mirror LDO circuit 100. At this time, the first bias voltage Vgate1 and the second bias voltage Vgate2 are negative voltages.

[0069] When the power transistor Md is an NMOS transistor, when the mirror LDO circuit 100 switches from the first working state to the second working state, initially the mirror LDO circuit 100 operates in the first working state. The bias voltage circuit 20 outputs the first bias voltage Vgate1 of a positive voltage to the power transistor Md, and the power transistor Md triggers the output of the first load current.

[0070] When the state feedback circuit 30 detects that the working state of the mirror LDO circuit 100 has changed, that is, after detecting that the mirror LDO circuit 100 has switched to the second working state, at this time, the output current of the power transistor Md becomes smaller. The state feedback circuit 30 switches to output the second trigger signal to the bias voltage circuit 20, and the bias voltage circuit 20 switches to output the second bias voltage Vgate2 smaller than the first bias voltage Vgate1 to the power transistor Md. The gate-source voltage of the power transistor Md becomes smaller, and the gate voltage of the power transistor Md becomes smaller, so that the source voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100, and improving the working stability and reliability of the mirror LDO circuit 100.

[0071] And when the mirror LDO circuit 100 switches from the second working state to the first working state, initially the mirror LDO circuit 100 operates in the second working state. The bias voltage circuit 20 outputs the second bias voltage Vgate2 of a positive voltage to the power transistor Md, and the power transistor Md triggers the output of the second load current.

[0072] When the state feedback circuit 30 detects that the working state of the mirror LDO circuit 100 has changed, that is, after detecting that the mirror LDO circuit 100 has switched to the first working state, at this time, the output current of the power transistor Md becomes smaller. The state feedback circuit 30 switches to output the first trigger signal to the bias voltage circuit 20, and the bias voltage circuit 20 switches to output the first bias voltage Vgate1 larger than the second bias voltage Vgate2 to the power transistor Md. The gate-source voltage of the power transistor Md becomes larger, and the gate voltage of the power transistor Md becomes larger, so that the source voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100, and improving the working stability and reliability of the mirror LDO circuit 100.

[0073] When the power transistor Md is a PMOS transistor, when the mirror LDO circuit 100 switches from the first operating state to the second operating state, initially the mirror LDO circuit 100 operates in the first operating state, the bias voltage circuit 20 outputs a first negative bias voltage Vgate1 to the power transistor Md, and the power transistor Md triggers the output of a first load current.

[0074] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, that is, after detecting that the mirror LDO circuit 100 has switched to the second operating state, at this time, the output current of the power transistor Md becomes smaller, the state feedback circuit 30 switches to output a second trigger signal to the bias voltage circuit 20, and the bias voltage circuit 20 switches to output a second bias voltage Vgate2 greater than the first bias voltage Vgate1 to the power transistor Md, that is, the absolute value of the first bias voltage Vgate1 is greater than the absolute value of the second bias voltage Vgate2. The source voltage of the power transistor Md remains unchanged, the gate-source voltage of the power transistor Md becomes smaller, and the gate voltage of the power transistor Md becomes larger, so that the drain voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the operating stability and reliability of the mirror LDO circuit 100.

[0075] When the mirror LDO circuit 100 switches from the second operating state to the first operating state, initially the mirror LDO circuit 100 operates in the second operating state, the bias voltage circuit 20 outputs a second negative bias voltage Vgate2 to the power transistor Md, and the power transistor Md triggers the output of a second load current.

[0076] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, that is, after detecting that the mirror LDO circuit 100 has switched to the first operating state, at this time, the output current of the power transistor Md becomes smaller, the state feedback circuit 30 switches to output a first trigger signal to the bias voltage circuit 20, and the bias voltage circuit 20 switches to output a first bias voltage Vgate1 less than the second bias voltage Vgate2 to the power transistor Md, that is, the absolute value voltage of the second bias voltage Vgate2 is less than the first bias voltage Vgate1. The source voltage of the power transistor Md remains unchanged, the gate-source voltage of the power transistor Md becomes larger, so that the drain voltage of the power transistor Md can be kept constant, avoiding fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the operating stability and reliability of the mirror LDO circuit 100.

[0077] The bias voltage circuit 20 can adopt structures such as a voltage source and a voltage generator, and trigger the output of different bias voltages according to different received trigger signals.

[0078] The state feedback circuit 30 can adopt structures such as a controller, a sampling circuit, a comparator, etc. By obtaining the magnitude of the load current or the working control instruction of the mirror LDO circuit 100, etc., the working state of the current mirror LDO circuit 100 is determined. In an alternative embodiment, the state feedback circuit 30 includes a current detection circuit. The current detection circuit is connected to the output terminal of the mirror LDO circuit 100 and detects the magnitude of the load current. When the first load current is detected, a first trigger signal is output, and when the second load current is detected, a second trigger signal is output.

[0079] The current detection circuit can adopt structures such as a current transformer, a voltage dividing resistor, etc. In an alternative embodiment, as Figure 12 shown, the current detection circuit includes a sixth resistor R6, a seventh resistor R7, and a comparator AMP3. The first end of the sixth resistor R6 is connected to the output terminal of the power transistor Md. The second end of the sixth resistor R6, the first end of the seventh resistor R7, and the inverting input terminal of the comparator AMP3 are connected. The non-inverting input terminal of the comparator AMP3 is used to input a third reference voltage. The second end of the seventh resistor R7 is grounded. The output terminal of the comparator AMP3 constitutes the output terminal of the current detection circuit.

[0080] When the power transistor Md outputs the first load current, the voltage at the connection node of the sixth resistor R6 and the seventh resistor R7 is greater than the third reference voltage, and the comparator AMP3 outputs a low level. When the power transistor Md outputs the second load current, the voltage at the connection node of the sixth resistor R6 and the seventh resistor R7 is less than the third reference voltage, and the comparator AMP3 outputs a high level.

[0081] As Figure 4 shown, in an alternative embodiment, the bias voltage circuit 20 includes:

[0082] A first bias voltage generation circuit 21 for generating a first bias voltage Vgate1;

[0083] A second bias voltage generation circuit 22 for generating a second bias voltage Vgate2;

[0084] A switch switching circuit 23 is respectively connected to the first bias voltage generation circuit 21, the second bias voltage generation circuit 22, the power transistor Md, and the state feedback circuit 30. The switch switching circuit 23 is triggered by the first trigger signal to connect the first bias voltage generation circuit 21 and the power transistor Md, and is triggered by the second trigger signal to connect the second bias voltage generation circuit 22 and the power transistor Md.

[0085] In this embodiment, the first input terminal of the switch switching circuit 23 is connected to the first bias voltage generating circuit 21 and is used to receive the first bias voltage Vgate1. The second input terminal of the switch switching circuit 23 is connected to the second bias voltage generating circuit 22 and is used to receive the second bias voltage Vgate2. The output terminal of the switch switching circuit 23 is connected to the gate of the power transistor Md, and selects to output the first bias voltage Vgate1 or the second bias voltage Vgate2 to the power transistor Md according to the received trigger signal.

[0086] When the mirror LDO circuit 100 operates in the first operating state, the state feedback circuit 30 outputs a first trigger signal to the switch switching circuit 23. The switch switching circuit 23 connects its first input terminal and output terminal, and the first bias voltage Vgate1 is output to the power transistor Md, and controls the power transistor Md to output a first load current and output a preset voltage.

[0087] When the mirror LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs a second trigger signal to the switch switching circuit 23. The switch switching circuit 23 connects its second input terminal and output terminal, and the second bias voltage Vgate2 is output to the power transistor Md, and controls the power transistor Md to output a second load current and output a constant preset voltage.

[0088] Among them, the switch switching circuit 23 can adopt a multi-input single-output switch device or adopt different switch combinations. In an alternative embodiment, as Figure 5 shown, the switch switching circuit 23 includes:

[0089] A first switch S1 is connected between the first bias voltage generating circuit 21 and the control terminal of the power transistor Md. The control terminal of the first switch S1 is connected to the state feedback circuit 30. The first switch S1 is triggered to conduct by the first trigger signal and is triggered to turn off by the second trigger signal. The first trigger signal and the second trigger signal are opposite level signals;

[0090] A second switch S2 is connected between the second bias voltage generating circuit 22 and the control terminal of the power transistor Md. The control terminal of the second switch S2 is connected to the state feedback circuit 30. The second switch S2 is triggered to conduct by the second trigger signal and is triggered to turn off by the first trigger signal.

[0091] In this embodiment, at the same moment, the switching states of the first switch S1 and the second switch S2 are different. When the mirror LDO circuit 100 operates in the first operating state, the state feedback circuit 30 outputs a first trigger signal to the first switch S1 and the second switch S2. The first switch S1 is turned on, the second switch S2 is turned off, and the first bias voltage generation circuit 21 and the power transistor Md are connected. The first bias voltage Vgate1 is output to the power transistor Md, and the power transistor Md is controlled to output a first load current and a preset voltage.

[0092] When the mirror LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs a second trigger signal to the first switch S1 and the second switch S2. The first switch S1 is turned off, the second switch S2 is turned on, the second bias voltage Vgate2 is output to the power transistor Md, and the power transistor Md is controlled to output a second load current and maintain the output of a constant preset voltage.

[0093] The first switch S1 and the second switch S2 can adopt switching devices with controlled on-off, and the two switch types are opposite. The first trigger signal and the second trigger signal can be high and low level signals respectively.

[0094] At the same time, when the first trigger signal and the second trigger signal are output, at the critical switching point of the two signals, there is a situation where the first switch S1 and the second switch S2 are turned on simultaneously, resulting in a direct connection between the first bias voltage generation circuit 21 and the second bias voltage generation circuit 22, causing a voltage signal to flow back, and there is a risk of damaging the bias voltage generation circuit. For this reason, in an alternative embodiment, as Figure 6 shown, the mirror LDO circuit 100 further includes:

[0095] A delay output circuit 40, which is respectively connected to the state feedback circuit 30, the first switch S1, and the second switch S2. The delay output circuit 40 is used to delay the output of the first trigger signal and the second trigger signal to the first switch S1 and the second switch S2.

[0096] In this embodiment, when the mirror LDO circuit 100 operates in the first operating state, the state feedback circuit 30 outputs a first trigger signal, the delay output circuit 40 delays the output of the first trigger signal, the first switch S1 is turned on, the second switch S2 is turned off, and the first bias voltage generation circuit 21 and the power transistor Md are connected. The first bias voltage Vgate1 is output to the power transistor Md, and the power transistor Md is controlled to output a first load current and a preset voltage.

[0097] When the mirror LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs a second trigger signal. At this time, the second trigger signal is delayed and output. The first switch S1 is turned off first, and the second switch S2 is turned on later, thereby preventing a through problem from occurring in the two bias voltage generation circuits. The second bias voltage Vgate2 is output to the power transistor Md, and controls the power transistor Md to output a second load current and maintain a preset voltage that is constant at the output.

[0098] Similarly, when the mirror LDO circuit 100 switches to the first operating state again, the state feedback circuit 30 outputs a first trigger signal. The first trigger signal is delayed and output by the delay output circuit 40. The second switch S2 is turned off first, and the first switch S1 is turned on later, thereby preventing a through problem from occurring in the two bias voltage generation circuits. The first bias voltage Vgate1 is output to the power transistor Md, and controls the power transistor Md to output a second load current and maintain a preset voltage that is constant at the output.

[0099] In an alternative embodiment, as Figure 7 shown, the first switch S1 includes a first transmission gate TG1 connected between the first bias voltage generation circuit 21 and the control terminal of the power transistor Md. The first transmission gate TG1 includes a first NMOS transistor and a first PMOS transistor connected in parallel;

[0100] The second switch S2 includes a second transmission gate TG2 connected between the second bias voltage generation circuit 22 and the control terminal of the power transistor Md. The second transmission gate TG2 includes a second NMOS transistor and a second PMOS transistor connected in parallel. The gate of the first NMOS transistor and the gate of the second PMOS transistor are commonly connected to form a first control terminal, and the gate of the first PMOS transistor and the gate of the second NMOS transistor are commonly connected to form a second control terminal.

[0101] Among them, the first NMOS transistor and the second NMOS transistor are triggered to conduct when receiving a high level, and are triggered to turn off when receiving a low level. The first PMOS transistor and the second PMOS transistor are triggered to turn off when receiving a high level, and are triggered to conduct when receiving a high level.

[0102] As Figure 8 shown, the delay output circuit 40 includes:

[0103] A delay circuit 41, connected between the state feedback circuit 30 and the second control terminal. The delay circuit 41 is configured to delay and output the received trigger signal for a preset duration;

[0104] An inverter circuit 42, connected between the state feedback circuit 30 and the first control terminal. The inverter circuit 42 is configured to perform an inverting conversion on the received trigger signal and output it.

[0105] In this embodiment, in the first working state, the first trigger signal is at a low level, and in the second working state, the second trigger signal is at a high level.

[0106] In the initial state, the first trigger signal outputs a high level to the first NMOS transistor of the first transmission gate TG1 and outputs to the second PMOS transistor of the second transmission gate TG2 through the inverter circuit 42. At this time, the delay circuit 41 outputs a low level to the first PMOS transistor of the first transmission gate TG1 and outputs to the second NMOS transistor of the second transmission gate TG2 after a delay. The first transmission gate TG1 is turned on, and the second transmission gate TG2 is turned off. At this time, the first bias voltage Vgate1 is transmitted to the power transistor Md through the first transmission gate TG1, and controls the power transistor Md to output the first load current and output a preset voltage.

[0107] When the mirror LDO circuit 100 switches to the second working state, the state feedback circuit 30 outputs the second trigger signal. At this time, the second trigger signal is inverted by the inverter circuit 42 and outputs a low level to the first NMOS transistor of the first transmission gate TG1 and outputs to the second PMOS transistor of the second transmission gate TG2. The first NMOS transistor is turned off, and the first transmission gate TG1 is turned off. After a preset delay duration, the delay circuit 41 outputs a high level to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2. The second transmission gate TG2 is turned on after a delay, thereby preventing a direct connection problem from occurring in the two bias voltage generation circuits. The second bias voltage Vgate2 is output to the power transistor Md, and controls the power transistor Md to output the second load current and maintain the output of a constant preset voltage.

[0108] Similarly, when the mirror LDO circuit 100 switches to the first working state again, the state feedback circuit 30 outputs the first trigger signal. The first trigger signal is inverted by the inverter circuit 42 and outputs a high level to the first NMOS transistor of the first transmission gate TG1 and outputs to the second PMOS transistor of the second transmission gate TG2. The second PMOS transistor is turned off, and the second transmission gate TG2 is turned off. After a preset delay duration, the delay circuit 41 outputs a low level to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2. The first transmission gate TG1 is turned on after a delay, thereby preventing a direct connection problem from occurring in the two bias voltage generation circuits. The first bias voltage Vgate1 is output to the power transistor Md, and controls the power transistor Md to output the first load current and maintain the output of a constant preset voltage.

[0109] Among them, the delay circuit 41 can be composed of multiple inverters or a delay element. To simplify the circuit structure, in an alternative embodiment, the delay circuit 41 includes a delay element. The input terminal and the output terminal of the delay element respectively form the input terminal and the output terminal of the delay circuit 41. The delay element delays the input trigger signal by a preset duration and then outputs it to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2, so as to control the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2 to conduct or turn off with a delay, preventing the two bias voltage generation circuits from being directly connected.

[0110] The inverting circuit 42 can be composed of one or more inverters or a level conversion circuit. To simplify the circuit structure, in an alternative embodiment, the inverting circuit 42 includes an inverter. The input terminal and the output terminal of the inverter respectively form the input terminal and the output terminal of the inverting circuit 42. The inverter inverts the input trigger signal and outputs it to the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2, so as to control the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2 to conduct or turn off.

[0111] The first bias voltage generation circuit 21 and the second bias voltage generation circuit 22 can adopt a voltage source, a mirror source circuit, etc. In an alternative embodiment, as Figure 9 shown, the first bias voltage generation circuit 21 includes a first transistor M1, a second resistor R2, and a first operational amplifier AMP1;

[0112] The drain of the first transistor M1 is connected to the positive voltage terminal VDD. The gate of the first transistor M1 is connected to the output terminal of the first operational amplifier AMP1. The source of the first transistor M1, the second resistor R2, and the inverting input terminal of the first operational amplifier AMP1 are connected. The second terminal of the second resistor R2 is grounded. The non-inverting input terminal of the first operational amplifier AMP1 is used to input the first reference voltage Vref1.

[0113] The second bias voltage generation circuit 22 includes a third transistor M3, a fourth resistor R4, and a second operational amplifier AMP2;

[0114] The drain of the third transistor M3 is connected to the positive voltage terminal VDD. The gate of the third transistor M3 is connected to the output terminal of the second operational amplifier AMP2. The source of the third transistor M3, the fourth resistor R4, and the inverting input terminal of the second operational amplifier AMP2 are connected. The second terminal of the fourth resistor R4 is grounded. The non-inverting input terminal of the second operational amplifier AMP2 is used to input the second reference voltage Vref2.

[0115] In this embodiment, the power transistor Md, the first transistor M1, and the third transistor are NMOS transistors. When the first switch S1 is turned on, the first transistor M1, the second resistor R2, and the first operational amplifier AMP1 form a negative feedback network, and together with the power transistor Md and the first resistor R1, they form a mirror LDO circuit 100. When the voltage input at the positive voltage terminal VDD changes, the terminal voltage of the second resistor R2 increases or decreases. At this time, the first operational amplifier AMP1 performs negative feedback regulation, thereby outputting a changing gate voltage, changing the current on the second resistor R2, and finally achieving that the terminal voltage of the second resistor R2 is equal to the first reference voltage Vref1, and achieving that the first operational amplifier AMP1 outputs a constant first bias voltage Vgate1.

[0116] Similarly, when the second switch S2 is turned on, the third transistor M3, the fourth resistor R4, and the second operational amplifier AMP2 form a negative feedback network, and together with the power transistor Md and the first resistor R1, they form a mirror LDO circuit 100. When the voltage input at the positive voltage terminal VDD changes, the terminal voltage of the fourth resistor R4 increases or decreases. At this time, the second operational amplifier AMP2 performs negative feedback regulation, thereby outputting a changing gate voltage, changing the current on the fourth resistor R4, and finally achieving that the terminal voltage of the fourth resistor R4 is equal to the second reference voltage Vref2, and achieving that the second operational amplifier AMP2 outputs a constant second bias voltage Vgate2.

[0117] Among them, the first reference voltage Vref1 and the second reference voltage Vref2 can be equal or unequal, and the second resistor R2 and the fourth resistor R4 can be equal or unequal. Among them, in order to achieve different bias voltage outputs, at least one of the reference voltages and resistors of the two bias voltage generation circuits has different parameters.

[0118] Due to factors such as testing, power supply toggling, process offset, load current drift, etc., the bias voltage generation circuit composed of a single resistor and a single transistor may not be able to meet the output requirements caused by factor changes, and the magnitude of the bias voltage output may change, and a constant bias voltage cannot be output. Therefore, in an alternative embodiment, as Figure 10 shown, the first bias voltage generation circuit 21 further includes:

[0119] A plurality of first branches 211 connected in parallel between the drain and source of the first transistor M1. The first branch 211 includes a second transistor M2 and a third switch S3 connected in sequence between the drain and source of the first transistor M1. The gates of the plurality of second transistors M2 are commonly connected to the gate of the first transistor M1, and the plurality of third switches S3 are triggered to conduct or turn off corresponding to the first switch selection signal bit0;

[0120] A plurality of second branches 212 are connected in parallel across the second resistor R2. The second branch 212 includes a fourth switch S4 and a third resistor R3 connected in sequence across the second resistor R2. The plurality of fourth switches S4 are triggered to conduct or turn off correspondingly by the second selection signal bit1.

[0121] In this embodiment, the second transistor M2 is an NMOS transistor. When parameter changes cause a change in the output of the first bias voltage Vgate1, the first switch selection signal bit0 is output, thereby changing the number of second transistors M2 connected in parallel to the first transistor M1, further changing the equivalent impedance of the first transistor M1 and the second transistor M2 as a whole, further changing the terminal voltage of the second resistor R2, and changing the magnitude of the output first bias voltage Vgate1.

[0122] And / or, the second selection signal bit1 is output to change the number of third resistors R3 connected in parallel to the second resistor R2, further changing the impedance of the second resistor R2 and the third resistor R3 as a whole, further changing the terminal voltage of the second resistor R2, and changing the magnitude of the output first bias voltage Vgate1, realizing fine-tuning output of the first bias voltage Vgate1, so that the first bias voltage Vgate1 is stabilized at the initial set value to meet constant voltage output.

[0123] Similarly, when different magnitudes of the first bias voltage Vgate1 need to be output, the number of second transistors M2 connected in parallel and the number of third resistors R3 connected in parallel can also be changed, thereby changing the terminal voltage of the second resistor R2 and the magnitude of the output first bias voltage Vgate1.

[0124] Correspondingly, as Figure 11 shown, in an alternative embodiment, the second bias voltage generating circuit 22 further includes:

[0125] A plurality of third branches 221 are connected in parallel between the drain and source of the third transistor M3. The third branch 221 includes a fourth transistor M4 and a fifth switch S5 connected in sequence between the drain and source of the third transistor M3. The gates of the plurality of fourth transistors M4 are commonly connected to the gate of the third transistor M3. The plurality of fifth switches S5 are triggered to conduct or turn off correspondingly by the third selection signal bit2;

[0126] A plurality of second branches 212 are connected in parallel across the fourth resistor R4. The second branch 212 includes a sixth switch S6 and a fifth resistor R5 connected in sequence across the fourth resistor R4. The plurality of sixth switches S6 are triggered to conduct or turn off correspondingly by the fourth selection signal bit3.

[0127] In this embodiment, the fourth transistor is an NMOS transistor. When parameter variations cause changes in the output of the first bias voltage Vgate1, the third selection signal bit2 is output, thereby changing the number of fourth transistors M4 connected in parallel to the third transistor M3, further changing the equivalent impedance of the overall third transistor M3 and fourth transistor M4, further changing the terminal voltage of the fourth resistor R4, and changing the magnitude of the output second bias voltage Vgate2.

[0128] And / or, the fourth selection signal bit3 is output to change the number of fifth resistors R5 connected in parallel to the fourth resistor R4, further changing the impedance of the overall fourth resistor R4 and fifth resistor R5, further changing the terminal voltage of the fourth resistor R4, and changing the magnitude of the output second bias voltage Vgate2, realizing fine-tuning output of the second bias voltage Vgate2, so that the second bias voltage Vgate2 is stabilized at the initial set value to meet constant voltage output.

[0129] Similarly, when it is necessary to output a second bias voltage Vgate2 of different magnitudes, the number of fourth transistors M4 connected in parallel and the number of fifth resistors R5 connected in parallel can also be changed, thereby changing the terminal voltage of the fourth resistor R4 and changing the magnitude of the output second bias voltage Vgate2.

[0130] The beneficial effects of the embodiment of the present utility model compared with the prior art are as follows: The above-mentioned mirror LDO circuit 100 is connected by a driving circuit 10, a bias voltage circuit 20, and a state feedback circuit 30. When the mirror LDO circuit 100 operates in the first operating state, the state feedback circuit 30 outputs a first trigger signal to trigger the bias voltage circuit 20 to output a first bias voltage Vgate1, and when the mirror LDO circuit 100 operates in the second operating state, the state feedback circuit 30 outputs a second trigger signal to trigger the bias voltage circuit 20 to output a second bias voltage Vgate2. The driving circuit 10 maintains the output of a first load current after receiving the first bias voltage Vgate1, and the driving circuit 10 maintains the output of a second load current after receiving the second bias voltage Vgate2, and maintains the output terminal voltage of the driving circuit 10 stable at a preset voltage to achieve constant voltage output, preventing the output voltage Vo of the mirror LDO circuit 100 from fluctuating, thereby improving the working stability and reliability of the mirror LDO circuit 100.

[0131] The present utility model also proposes an image sensor, which includes a load circuit 200 and a mirror LDO circuit 100. The specific structure of the mirror LDO circuit 100 refers to the above embodiment. Since this image sensor adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one. Among them, the load circuit 200 is connected to the mirror LDO circuit 100.

[0132] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A mirror LDO circuit, characterized in that: The mirror LDO circuit operates in a first working state of outputting a first load current or in a second working state of outputting a second load current, and the first load current is greater than the second load current; The mirror LDO circuit comprises: A driving circuit, the driving circuit comprising a power tube and a first resistor connected in sequence between a positive voltage terminal and a ground terminal, a connection node between the power tube and the first resistor forming an output terminal of the mirror LDO circuit and used for outputting a driving power supply to a load circuit, the power tube receiving a bias voltage to generate a load current; A bias voltage circuit, connected to the control end of the power tube, is triggered by a first trigger signal to output a first bias voltage, and is triggered by a second trigger signal to output a second bias voltage, wherein the absolute value of the first bias voltage is greater than the absolute value of the second bias voltage; A state feedback circuit is connected to the bias voltage circuit, and the state feedback circuit is used to detect the state of the load circuit, and output the first trigger signal when it is detected that the mirror LDO circuit is in a first working state, and output the second trigger signal when it is detected that the load circuit is in a second working state.

2. The mirror LDO circuit according to claim 1, characterized in that: The bias voltage circuit comprises: A first bias voltage generating circuit, used for generating the first bias voltage; A second bias voltage generating circuit, used for generating the second bias voltage; The switch switching circuit is respectively connected to the first bias voltage generating circuit, the second bias voltage generating circuit, the power tube and the state feedback circuit. The switch switching circuit is triggered by the first trigger signal to connect the first bias voltage generating circuit and the power tube, and is triggered by the second trigger signal to connect the second bias voltage generating circuit and the power tube.

3. The mirror LDO circuit according to claim 2, characterized in that: The switch switching circuit comprises: a first switch connected between the first bias voltage generating circuit and the control end of the power tube, the control end of the first switch being connected to the state feedback circuit, the first switch being turned on by the first trigger signal and turned off by the second trigger signal, the first trigger signal and the second trigger signal being opposite level signals; The second switch is connected between the second bias voltage generating circuit and the control end of the power tube, the control end of the second switch is connected to the state feedback circuit, and the second switch is turned on by the second trigger signal and turned off by the first trigger signal.

4. The mirror LDO circuit as claimed in claim 3, characterized in that: The mirror LDO circuit also includes: A delayed output circuit is connected to the state feedback circuit, the first switch and the second switch respectively, and the delayed output circuit is used to delay output of the first trigger signal and the second trigger signal to the first switch and the second switch.

5. The mirror LDO circuit according to claim 4, characterized in that: The first switch includes a first transmission gate connected between the first bias voltage generating circuit and the control end of the power tube, and the first transmission gate includes a first NMOS tube and a first PMOS tube connected in parallel; The second switch includes a second transmission gate connected between the second bias voltage generating circuit and the control end of the power tube, the second transmission gate includes a second NMOS tube and a second PMOS tube connected in parallel, the gate of the first NMOS tube and the gate of the second PMOS tube are connected together to form a first control end, and the gate of the first PMOS tube and the gate of the second NMOS tube are connected together to form a second control end; The delay output circuit comprises: A delay circuit, connected between the state feedback circuit and the second control terminal, the delay circuit being used to delay the output of the received trigger signal by a preset time length; The inverting circuit is connected between the state feedback circuit and the first control terminal, and is used for performing inverting conversion on the received trigger signal and outputting the inverted signal.

6. The mirror LDO circuit as claimed in claim 5, characterized in that: The delay circuit comprises a delay device, and an input end and an output end of the delay device constitute an input end and an output end of the delay circuit respectively.

7. The mirror LDO circuit according to claim 5, characterized in that: The inverting circuit comprises an inverter, and an input end and an output end of the inverter constitute an input end and an output end of the inverter respectively.

8. The mirror LDO circuit as claimed in claim 2, characterized in that: The first bias voltage generating circuit includes a first transistor, a second resistor and a first operational amplifier; The drain of the first transistor is connected to the positive voltage terminal, the gate of the first transistor is connected to the output terminal of the first operational amplifier, the source of the first transistor, the second resistor and the inverting input terminal of the first operational amplifier are connected, the second end of the second resistor is grounded, and the non-inverting input terminal of the first operational amplifier is used to input a first reference voltage.

9. The mirror LDO circuit according to claim 8, characterized in that: The first bias voltage generating circuit further includes: A plurality of first branches connected in parallel between the drain and the source of the first transistor, wherein the first branch comprises a second transistor and a third switch connected in sequence between the drain and the source of the first transistor, the gates of the plurality of second transistors are connected in common with the gate of the first transistor, and the plurality of third switches are turned on or off correspondingly triggered by the first switch selection signal; A plurality of second branches are connected in parallel to both ends of the second resistor, wherein the second branch comprises a fourth switch and a third resistor which are sequentially connected to both ends of the second resistor, and the plurality of fourth switches are triggered to turn on or off in response to a second switch selection signal.

10. The mirror LDO circuit according to claim 2, characterized in that: The second bias voltage generating circuit includes a third transistor, a fourth resistor and a second operational amplifier; The drain of the third transistor is connected to the positive voltage terminal, the gate of the third transistor is connected to the output terminal of the second operational amplifier, the source of the third transistor, the fourth resistor and the inverting input terminal of the second operational amplifier are connected, the second end of the fourth resistor is grounded, and the non-inverting input terminal of the second operational amplifier is used to input a second reference voltage.

11. The mirror LDO circuit according to claim 10, wherein: The second bias voltage generating circuit further includes: A plurality of third branches connected in parallel between the drain and the source of the third transistor, the third branches comprising a fourth transistor and a fifth switch sequentially connected between the drain and the source of the third transistor, the gates of the plurality of fourth transistors being commonly connected to the gate of the third transistor, and the plurality of fifth switches being turned on or off correspondingly triggered by a third switch selection signal; A plurality of fourth branches are connected in parallel to both ends of the fourth resistor, wherein the fourth branch comprises a sixth switch and a fifth resistor which are sequentially connected to both ends of the fourth resistor, and the plurality of sixth switches are triggered to turn on or off in response to a fourth switch selection signal.

12. An image sensor, characterized in that: The invention comprises a load circuit and the mirror LDO circuit according to any one of claims 1 to 11, wherein the load circuit is connected to the mirror LDO circuit.

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