Memory chip with destroying function
By setting up flash memory, charging module and capacitor module on the printed circuit board of the memory chip, and controlling the capacitor module to discharge to the flash memory through the switch module, the problem of data destruction failure in the prior art is solved, and data destruction at the physical level is achieved.
Patent Information
- Application Number
- CN202421627375.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-07-10
AI Technical Summary
When clearing data from memory chips, the prior art mainly relies on software-level erasing of the main control chip, and there is a risk of data destruction failure.
A memory chip with destruction function was designed. By setting up flash memory, charging module and capacitor module on the printed circuit board, the charging module is connected to the capacitor module, the capacitor module is connected to the flash memory, and the capacitor module is controlled to discharge electricity to the flash memory through the switch module, and data is destroyed at the physical level.
This ensures effective data destruction by physically destroying flash memory, avoiding the failure of data destruction caused by software-level erasing.
Smart Images
Figure CN222980016U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor manufacturing, and particularly relates to a storage chip with a destruction function. Background Art
[0002] In the related art, when the device equipped with the storage chip is discarded, there is a need to erase the data stored in the flash memory. Currently, the data stored in the flash memory is basically erased quickly by the main control chip. However, erasing through the main control chip is a pure software-level destruction solution, which will fail in some cases, resulting in the failure of data destruction. Summary of the Utility Model
[0003] Aiming at the deficiencies of the prior art, the present application provides a storage chip with a destruction function, which is beneficial to destroying the storage chip by damaging the flash memory to ensure the effectiveness of data destruction.
[0004] To solve the above problems, the utility model provides the following technical solutions:
[0005] In a first aspect, an embodiment of the present application provides a storage chip with a destruction function. The storage chip includes a printed circuit board, on which a flash memory, a charging module, and a capacitor module are provided;
[0006] The charging module is connected to the first end of the capacitor module and is used to charge the capacitor module;
[0007] The second end of the capacitor module is connected to the first end of the flash memory;
[0008] The second end of the flash memory is grounded.
[0009] In some embodiments, the printed circuit board further includes a first switch module;
[0010] The charging module is connected to the capacitor module through the first switch module. When the first switch module is turned on, the charging module charges the capacitor module;
[0011] When the first switch module is turned off, the charging module stops charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.
[0012] In some embodiments, the printed circuit board further includes a second switch module, a third switch module, and a current limiting module; the current limiting module includes at least one current limiting resistor;
[0013] The second end of the capacitor module is connected to the first ends of the second switch module and the third switch module;
[0014] The second end of the second switch module is connected to the first end of the flash memory;
[0015] The second end of the third switch module is connected to the first end of the current limiting module, and the second end of the current limiting module is grounded.
[0016] In some embodiments, the charging module includes an external interface for connecting to an external device and receiving electrical energy transmitted by the external device to enable the external device to charge the capacitor module.
[0017] In some embodiments, the printed circuit board further includes a main control chip for controlling the switch states of the first switch module, the second switch module, and the third switch module; wherein, the switch states include on and off.
[0018] In some embodiments, the main control chip includes a first pin and a second pin. The first pin is used to receive a destruction instruction for controlling the first switch module to turn on, and the second pin is used to receive a stop destruction instruction for controlling the second switch module to turn off and the third switch module to turn on.
[0019] In some embodiments, the printed circuit board further includes a power chip for charging the capacitor module.
[0020] In some embodiments, the capacitor module includes a plurality of tantalum capacitors connected in parallel.
[0021] In some embodiments, on the printed circuit board, the distance between each tantalum capacitor and the corresponding flash memory is less than 5 mm.
[0022] In some embodiments, a plurality of flash memories and a plurality of capacitor modules are provided on the printed circuit board; wherein,
[0023] The charging module is connected to the first end of each capacitor module;
[0024] The second end of each capacitor module is connected to the first end of the corresponding flash memory;
[0025] The second end of each flash memory is grounded.
[0026] The present application provides a storage chip with a destruction function. The storage chip includes a printed circuit board, on which a flash memory, a charging module, and a capacitor module are provided. The charging module is connected to the first end of the capacitor module for charging the capacitor module. The second end of the capacitor module is connected to the first end of the flash memory. The second end of the flash memory is grounded. In the present application, after the charging module charges the capacitor module, the capacitor module can apply a high voltage to damage the structure of the flash memory, thereby achieving data destruction at the physical level. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 FIG. 1 is a first schematic structural diagram of a storage chip with a destruction function provided by an embodiment of the present application.
[0028] Figure 2 FIG. 2 is a second schematic structural diagram of a storage chip with a destruction function provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0030] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.
[0031] Please refer to Figure 1 , Figure 1 FIG. 1 is a first schematic structural diagram of a storage chip with a destruction function provided by an embodiment of the present application. As Figure 1 shown, the storage chip 1 with a destruction function includes a printed circuit board 10, on which a flash memory 20, a charging module 30, and a capacitor module 40 are provided.
[0032] In some embodiments, the charging module 30 and the capacitor module 40 are circuit structures drawn in a printed circuit board (PCB).
[0033] In some embodiments, the storage chip 1 further includes a plastic encapsulation layer (not shown in the figure). Plastic encapsulation refers to the process of encapsulating and protecting some components on a circuit board or the entire circuit board. This encapsulation usually uses plastic materials such as epoxy resin or silicone resin. The plastic encapsulation layer can provide mechanical protection, moisture resistance, dust protection, and insulation for the circuit, extending the service life and reliability of the product.
[0034] In some embodiments, the flash memory 20 is a chip installed in the PCB board.
[0035] Optionally, a main control chip 20 and a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM) are also provided in the printed circuit board.
[0036] Specifically, Figure 1 Only the connection relationships among the flash memory 20, the charging module 30, and the capacitor module 40 are schematically shown, and the remaining connection relationships are not shown, which should not be construed as a limitation to this application.
[0037] Exemplarily, the main control chip 50 is also connected to the flash memory 20 through a bus to read or write data, but Figure 1 it is not shown in the figure. The bus is, for example, a "Serial Peripheral Interface (SPI) bus", an "Inter-Integrated Circuit (I²C) bus", a "Quad SPI (QSPI) bus", a "Universal Serial Bus (USB)", a "Peripheral Component Interconnect express (PCIe)" bus, etc. The bus defines the physical path, communication protocol, and electrical specifications for data transmission between the main control chip 50 and the flash memory 20.
[0038] Optionally, the main control chip 50 includes a Central Processing Unit (CPU) or a Micro controller Unit (MCU).
[0039] In some embodiments, to ensure that the electrical energy released by the capacitor module 30 can damage the flash memory, the breakdown voltage value of the capacitor module 30 is greater than the operating voltage of the flash memory 20; wherein, the breakdown voltage value of the capacitor refers to the maximum voltage value that the capacitor can withstand. When the voltage of the capacitor is less than or equal to the breakdown voltage value, the capacitor will not be broken down or damaged due to excessive voltage.
[0040] In some embodiments, the charging module 30 is connected to the first end of the capacitor module 40 for charging the capacitor module 40; the second end of the capacitor module 40 is connected to the first end of the flash memory 20; and the second end of the flash memory 20 is grounded.
[0041] Optionally, the first end of the flash memory 20 is one of the pins of the flash memory 20, and the second end of the flash memory 20 is the ground pin of the flash memory 20.
[0042] In some embodiments, in the circuit loop formed by the flash memory 20, the charging module 30, and the capacitor module 40, the capacitor module 40 and the flash memory 20 are connected in series.
[0043] In some embodiments, the charging current I of the charging module 30 should be greater than or equal to C * dV / dt, where C is the capacitance value of the capacitor module 40, and dV / dt is equal to the withstand voltage value of the capacitor module 40 divided by the charging time.
[0044] In some embodiments, the capacitor module 40 includes a plurality of parallel-connected tantalum capacitors. Specifically, for tantalum capacitors with the same capacitance, the volume is much smaller than that of aluminum electrolytic capacitors, which is suitable for high-density installation, especially in electronic devices with limited space. Moreover, the temperature characteristics and frequency characteristics of tantalum capacitors are better than those of aluminum electrolytic capacitors, with a wide operating temperature range, small leakage current, and good long-term stability.
[0045] In some embodiments, in order to achieve rapid data destruction, on the printed circuit board, the distance between each tantalum capacitor and the corresponding flash memory is less than 5 mm.
[0046] Optionally, the storage chip 1 is a solid-state drive. A solid-state drive processes a wafer-level main control chip, flash memory, cache chip, and some other electronic components into a single chip through system-in-package (SiP) technology, with a small form factor, and its area is generally less than 100 mm * 100 mm.
[0047] Please refer to Figure 2 , Figure 2 which is the second structural schematic diagram of the storage chip with a destruction function provided by the embodiment of the present application. As Figure 2 shown, the printed circuit board 10 further includes a first switch module 70.
[0048] In some embodiments, the charging module 30 is connected to the capacitor module 40 through the first switch module 70. When the first switch module 70 is turned on, the charging module 30 charges the capacitor module 40; when the first switch module 70 is turned off, the charging module 30 stops charging the capacitor module 40, and the capacitor module 40 discharges to the flash memory 20 to destroy the flash memory 20.
[0049] Specifically, the main control chip 50 can control the first switch module 70 to turn on or off. When the first switch module 70 is turned on, the charging module 30 charges the capacitor module 40, and when the first switch module 70 is turned off, the capacitor module 40 discharges outward.
[0050] Through the first switch module 70, it is possible to control whether the charging module 30 charges the capacitor module 40, thereby controlling the timing of data destruction.
[0051] In some embodiments, the printed circuit board 1 further includes a second switch module 80, a third switch module 90, and a current limiting module 100; the current limiting module 100 includes at least one current limiting resistor; the second end of the capacitor module 30 is connected to the first end of the second switch module 80 and the first end of the third switch module 90; the second end of the second switch module 80 is connected to the first end of the flash memory 20; the second end of the third switch module 90 is connected to the first end of the current limiting module 100, and the second end of the current limiting module 100 is grounded.
[0052] In some embodiments, the voltage range of the flash memory 20 is generally in the range of 1.8V to 3.6V. Since the withstand voltage value of the capacitor module 30 needs to be greater than 18V, for example, 28V, in order to prevent the current released when the capacitor module 30 releases electrical energy from being too large, the value of the current limiting resistor should be greater than 500 ohms, for example, 1K ohms.
[0053] Optionally, for the sake of simple wiring, all capacitor modules 30 release voltage through the same pressure relief circuit. At this time, the value of the current limiting resistor should be greater than N * 500 ohms, for example, N * 1K ohms; where N is the number of flash memories 20 and also the number of capacitor modules 30.
[0054] In some embodiments, a plurality of flash memories 20 and a plurality of capacitor modules 40 are provided on the printed circuit board 1; wherein, the charging module 30 is connected to the first end of each capacitor module 40; the second end of each capacitor module 40 is connected to the first end of the corresponding flash memory 20; the second end of each flash memory 20 is grounded.
[0055] In some embodiments, when N flash memories 20 and N capacitor modules 40 are provided on the printed circuit board 1, N second switch modules 80 and one third switch module 90 should be provided on the printed circuit board 1, that is, each flash memory 20 corresponds to a capacitor module 40 and a second switch module 80, but all capacitor modules 40 release voltage through the same third switch module 90; where N is a positive integer.
[0056] At this time, the second end of each capacitor module 40 is connected to the first end of the corresponding second switch module 80 and the first end of the third switch module 90, and the second end of each second switch module 80 is connected to the first end of the corresponding flash memory.
[0057] In some embodiments, the charging module 30 includes an external interface for connecting to an external device and receiving electrical energy delivered by the external device to charge the capacitor module 40.
[0058] Specifically, the above arrangement is applicable to storage chips with relatively low costs. When there is a need for destruction, an external voltage is applied to destroy the flash memory 20 to destroy the data.
[0059] In some embodiments, the printed circuit board 1 further includes a main control chip 50 for controlling the switching states of the first switch module 70, the second switch module 80, and the third switch module 90; wherein, the switching states include on and off.
[0060] Optionally, the first switch module 70 includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The main control chip 50 can control the first switch module 70 to turn on or off by applying a control signal to the gate of the MOSFET.
[0061] Optionally, both the second switch module 80 and the third switch module 90 include Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The main control chip 50 can control the second switch module 80 and the third switch module 90 to turn on or off by applying control signals to the gates of the MOSFETs in the second switch module 80 and the third switch module 90.
[0062] In some embodiments, the main control chip 50 includes a first pin and a second pin. The first pin is used to receive a destruction instruction for controlling the first switch module 70 to turn on, and the second pin is used to receive a stop destruction instruction for controlling the second switch module 80 to turn off and the third switch module 90 to turn on.
[0063] Optionally, the main control chip 50 has idle pins, which can be used to receive the destruction instruction and the stop destruction instruction.
[0064] In some embodiments, each capacitor module 40 includes a plurality of capacitors. The plurality of capacitors are connected in parallel. The plurality of capacitors are sorted. Except for the first capacitor among the plurality of capacitors, each of the remaining capacitors is connected to an NMOS transistor. The capacitor corresponding to the NMOS transistor is defined as the current capacitor. The gate of each NMOS transistor is connected to the second terminal of the previous capacitor of the current capacitor. The second terminal of the previous capacitor is connected to the first switch module 70, the source is connected to the first switch module 70, and the drain is connected to the current capacitor.
[0065] Thereby, the capacitors in the capacitor module 40 are charged in a stepped manner, appropriately extending the charging time of the capacitor module 40, giving the user sufficient time window to issue a receive notification destruction instruction, preventing the capacitor module 40 from being in a high voltage state for a long time, generating electromagnetic interference to other chips and generating excessive heat, etc.
[0066] In some embodiments, the printed circuit board further includes a power chip, and the power chip is used to charge the capacitor module.
[0067] In some embodiments, a diode is further provided between the second switch module 80 and the flash memory 20. The anode of the diode is connected to the second switch module 80, and the cathode of the diode is connected to the flash memory 20.
[0068] In some embodiments, after receiving the destruction instruction, the first switch module 70 is controlled to turn on, the second switch module 80 is turned on, and the third switch module 90 is turned off. When the capacitor module 40 reaches a preset voltage, such as its breakdown voltage, the first switch module 70 is turned off, and then the capacitor module 40 discharges to the flash memory 20 to destroy the flash memory.
[0069] Further, when the first switch module 70 is turned on, if a stop destruction instruction is received, then after turning on the third switch module 90 and turning off the second switch module 80, the first switch module 70 is turned off, so that the capacitor module 40 releases electrical energy through the current limiting module 100.
[0070] In summary, the present application provides a storage chip with a destruction function. The storage chip includes a printed circuit board, and a flash memory, a charging module, and a capacitor module are arranged on the printed circuit board; the charging module is connected to the first end of the capacitor module and is used to charge the capacitor module; the second end of the capacitor module is connected to the first end of the flash memory; the second end of the flash memory is grounded. In the present application, after the charging module charges the capacitor module, the capacitor module can apply a high voltage to damage the structure of the flash memory, thereby realizing data destruction at the physical level.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A memory chip with a destruction function, characterized in that: The storage chip includes a printed circuit board, and a flash memory, a charging module and a capacitor module are arranged on the printed circuit board; The charging module is connected to the first end of the capacitor module and is used to charge the capacitor module; The second end of the capacitor module is connected to the first end of the flash memory; The second terminal of the flash memory is grounded.
2. The memory chip according to claim 1, characterized in that: The printed circuit board also includes a first switch module; The charging module is connected to the capacitor module via a first switch module, and when the first switch module is turned on, the charging module charges the capacitor module; When the first switch module is turned off, the charging module stops charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.
3. The memory chip according to claim 2, characterized in that: The printed circuit board further includes a second switch module, a third switch module and a current limiting module; the current limiting module includes at least one current limiting resistor; The second end of the capacitor module is connected to the first end of the second switch module and the first end of the third switch module; The second end of the second switch module is connected to the first end of the flash memory; The second end of the third switch module is connected to the first end of the current limiting module, and the second end of the current limiting module is grounded.
4. The memory chip according to claim 1, characterized in that: The charging module comprises an external interface, and the external interface is used to connect an external device and receive electric energy transmitted by the external device, so that the external device charges the capacitor module.
5. The memory chip according to claim 3, characterized in that: The printed circuit board further includes a main control chip, and the main control chip is used to control the switch states of the first switch module, the second switch module and the third switch module; wherein the switch states include on and off.
6. The memory chip according to claim 5, characterized in that: The main control chip includes a first pin and a second pin, the first pin is used to receive a destruction instruction for controlling the first switch module to be turned on, and the second pin is used to receive a stop destruction instruction for controlling the second switch module to be turned off and the third switch module to be turned on.
7. The memory chip according to claim 1, characterized in that: The printed circuit board also includes a power chip, and the power chip is used to charge the capacitor module.
8. The memory chip according to any one of claims 1 to 7, characterized in that: The capacitor module includes a plurality of tantalum capacitors connected in parallel.
9. The memory chip according to claim 8, characterized in that: On the printed circuit board, the distance between each tantalum capacitor and the corresponding flash memory is less than 5 mm.
10. The memory chip according to any one of claims 1 to 7, characterized in that: A plurality of flash memories and a plurality of capacitor modules are arranged on the printed circuit board; wherein, The charging module is connected to the first end of each of the capacitor modules; The second end of each capacitor module is connected to the first end of the corresponding flash memory; The second terminal of each of the flash memories is grounded.