Power unit, three-phase full-bridge power module, power supply system and vehicle

Abstract

The utility model discloses a power unit, a three-phase full-bridge power module, a power supply system and a vehicle. Wherein the power unit comprises an upper bridge power chip and a lower bridge power chip, a second pole of the upper bridge power chip and a first pole of the lower bridge power chip are electrically connected with an alternating current output conductive path of the power unit, and a first pole of the upper bridge power chip and a second pole of the lower bridge power chip are electrically connected with two different conductive layers respectively. The two different conductive layers are at least partially stacked and are DC input conductive paths of the power unit. According to the technical scheme, parasitic inductance in the power unit packaging structure can be reduced.

Description

Technical Field

[0001] This application belongs to the technical field of power supplies, and particularly relates to a power unit, a three-phase full-bridge power module, a power supply system, and a vehicle. Background Art

[0002] The three-phase full-bridge power module is an important component in power electronic devices, and it is widely used in multiple fields. For example, it can be applied to new energy vehicles, and it can convert the DC current output by the battery into an AC current to drive devices such as motors that require AC power.

[0003] The power unit is a component of the three-phase full-bridge power module. A typical power unit includes a single-layer ceramic substrate, and a half-bridge unit or a full-bridge unit disposed on the surface of the single-layer ceramic substrate. The full-bridge unit is also composed of two half-bridge units; for each half-bridge unit, it may include an upper-bridge power chip, a lower-bridge power chip, and a commutation circuit connected to the upper-bridge power chip and the lower-bridge power chip. In the prior art, there is a problem of excessive parasitic inductance in the power unit packaging structure, and this excessive parasitic inductance usually causes a series of problems such as turn-off overvoltage, voltage-current oscillation, mis-switching, and electromagnetic interference during the switching process of the power unit. With the application of devices such as SiC and GaN in the power unit, although they have advantages such as high switching speed and can reduce switching losses, they are also more sensitive to parasitic inductance. Therefore, how to reduce the parasitic inductance in the power unit packaging structure is a technical problem that needs to be solved. Summary of the Invention

[0004] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a power unit, a three-phase full-bridge power module, a power supply system, and a vehicle, which can reduce the parasitic inductance in the power unit packaging structure.

[0005] In a first aspect, this application provides a power unit, including a first substrate, and at least one half-bridge unit formed on the first substrate. The half-bridge unit includes an upper-bridge power chip and a lower-bridge power chip. The second pole of the upper-bridge power chip and the first pole of the lower-bridge power chip are both electrically connected to the AC output conduction path of the power unit. The first pole of the upper-bridge power chip and the second pole of the lower-bridge power chip are respectively electrically connected to two different conductive layers. The two different conductive layers are at least partially stacked and serve as the DC input conduction path of the power unit.

[0006] In some embodiments, a first conductive layer and a second conductive layer are formed on the upper surface of the first substrate;

[0007] The upper-bridge power chip is disposed on the first conductive layer, and the first pole of the upper-bridge power chip is electrically connected to the first conductive layer;

[0008] The lower-bridge power chip is disposed on the second conductive layer. The second pole of the upper-bridge power chip and the first pole of the lower-bridge power chip are both electrically connected to the second conductive layer, and the second conductive layer is the AC output conductive path of the power unit.

[0009] The above-mentioned power unit further includes:

[0010] A second substrate is disposed on the first conductive layer, and a third conductive layer is formed on the upper surface of the second substrate. The third conductive layer and the first conductive layer are at least partially stacked, and the second pole of the lower-bridge power chip is electrically connected to the third conductive layer.

[0011] The first conductive layer and the third conductive layer are the DC input conductive paths of the power unit.

[0012] In some embodiments, the upper-bridge power chip and / or the lower-bridge power chip is a MOSFET, the first pole is the drain, the second pole is the source, the first conductive layer is the DC positive input conductive path of the power unit, and the third conductive layer is the DC negative input conductive path of the power unit.

[0013] In some embodiments, the upper-bridge power chip and / or the lower-bridge power chip is an IGBT, the first pole is the collector, the second pole is the emitter, the first conductive layer is the DC positive input conductive path of the power unit, and the third conductive layer is the DC negative input conductive path of the power unit.

[0014] In some embodiments, a fourth conductive layer is further formed on the upper surface of the first substrate, and the fourth conductive layer is electrically connected to the control pole of the upper-bridge power chip;

[0015] A fifth conductive layer is further formed on the upper surface of the first substrate, and the fifth conductive layer is electrically connected to the control pole of the lower-bridge power chip.

[0016] In some embodiments, the number of the upper-bridge power chips and the lower-bridge power chips is at least two, and the at least two upper-bridge power chips and the at least two lower-bridge power chips all extend along the length direction of the first substrate. In the width direction of the first substrate, the fourth conductive layer, the first conductive layer, the second conductive layer, and the fifth conductive layer of the half-bridge unit are arranged in sequence.

[0017] In some embodiments, the second pole includes a power second pole and a drive second pole, and a sixth conductive layer and a seventh conductive layer are further formed on the upper surface of the first substrate;

[0018] The power second pole of the upper-bridge power chip is electrically connected to the second conductive layer, and the drive second pole of the upper-bridge power chip is electrically connected to the sixth conductive layer, forming a Kelvin connection;

[0019] The second power pole of the lower-bridge power chip is electrically connected to the third conductive layer, and the second driving pole of the lower-bridge power chip is electrically connected to the seventh conductive layer, forming a Kelvin connection.

[0020] In some embodiments, the upper-bridge power chip, the lower-bridge power chip, and the second substrate are fixed on the upper surface of the first substrate through a connection layer.

[0021] In some embodiments, the second substrate is fixed on one side of the first conductive layer adjacent to the second conductive layer through a connection layer, and the upper-bridge power chip is located on one side of the first conductive layer away from the second conductive layer.

[0022] In some embodiments, the second pole of the upper-bridge power chip is electrically connected to the second conductive layer through a first connection line, and the first connection line straddles the second substrate;

[0023] The second pole of the lower-bridge power chip is electrically connected to the third conductive layer through a second connection line.

[0024] In some embodiments, the first connection line is one of a bonding wire or a copper sheet; the second connection line is one of a bonding wire or a copper sheet.

[0025] In some embodiments, the first substrate includes a first insulating substrate, a first copper layer on the upper surface of the first insulating substrate, and a second copper layer on the lower surface of the first insulating substrate. The first copper layer is etched to obtain at least one of the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer;

[0026] The second substrate includes a second insulating substrate and a third copper layer on the upper surface of the second insulating substrate, and the third copper layer serves as the third conductive layer.

[0027] In some embodiments, it further includes at least one of the following:

[0028] A DC positive input terminal and a DC negative input terminal, which are electrically connected to one of the first conductive layer and the third conductive layer respectively;

[0029] An AC output terminal, which is electrically connected to the second conductive layer;

[0030] A first upper-bridge driving terminal, which is electrically connected to the fourth conductive layer;

[0031] A first lower-bridge driving terminal, which is electrically connected to the fifth conductive layer;

[0032] A second upper-bridge driving terminal, which is electrically connected to the sixth conductive layer;

[0033] A second lower-bridge driving terminal, which is electrically connected to the seventh conductive layer.

[0034] In some embodiments, the DC positive input terminal and the DC negative input terminal are disposed at the first end of the first substrate along the length direction, and at least partially stacked;

[0035] The AC output terminal is disposed at the second end of the first substrate along the length direction.

[0036] In some embodiments, the DC positive input terminal, the DC negative input terminal, and the AC output terminal are all disposed in the middle section of the first substrate in the length direction, and the DC positive input terminal and the DC negative input terminal are disposed adjacent to each other.

[0037] In some embodiments, two half-bridge units are formed on the first substrate, namely a first half-bridge unit and a second half-bridge unit;

[0038] The second conductive layer of the first half-bridge unit and the second conductive layer of the second half-bridge unit are integrally provided, and the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are respectively disposed on the outer sides of the integrally provided second conductive layer in the width direction.

[0039] In some embodiments, the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are electrically connected.

[0040] In some embodiments, the fourth conductive layer and / or the sixth conductive layer are disposed on the outer side of the first conductive layer in the width direction;

[0041] The fifth conductive layer and the seventh conductive layer are disposed in the hollowed-out area in the middle of the second conductive layer, and the lower-bridge power chips of the first half-bridge unit and the lower-bridge power chips of the second half-bridge unit are respectively disposed on both sides of the hollowed-out area.

[0042] In some embodiments, the hollowed-out area includes a plurality of sub-hollowed-out areas, the fifth conductive layer and the seventh conductive layer include a plurality of sub-conductive layers respectively disposed in the sub-hollowed-out areas, the plurality of sub-conductive layers of the fifth conductive layer are electrically connected to each other, the plurality of sub-conductive layers of the seventh conductive layer are electrically connected to each other, and the control electrodes of the lower-bridge power chips are respectively connected to the sub-conductive layers of the fifth conductive layer adjacent thereto, and the drive electrodes of the lower-bridge power chips are respectively connected to the sub-conductive layers of the seventh conductive layer adjacent thereto.

[0043] In some embodiments, a conductive connection layer is disposed in the hollowed-out area at the edge of the first substrate, and the fourth conductive layer of the first half-bridge unit and the fourth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer, and / or, the sixth conductive layer of the first half-bridge unit and the sixth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer.

[0044] In a second aspect, the present application provides a three-phase full-bridge power module, including three power units as described in any one of the above, as well as a heat dissipation plate and a housing;

[0045] The lower surfaces of the first substrates in the three power units are all fixed on the heat dissipation plate, and the housing covers the three power units.

[0046] Thirdly, an embodiment of the present application further provides a power supply system, including a battery and the above-mentioned three-phase full-bridge power module.

[0047] Fourthly, an embodiment of the present application further provides a vehicle, including the above-mentioned power supply system.

[0048] In the technical solution provided by the embodiment of the present application, the half-bridge unit includes a first substrate, an upper-bridge power chip and a lower-bridge power chip formed on the first substrate, and the second pole of the upper-bridge power chip and the first pole of the lower-bridge power chip are used as the AC output terminals, and are both electrically connected to the AC output conductive path of the power unit; the first pole of the upper-bridge power chip and the second pole of the lower-bridge power chip are used as the DC input terminals, and are respectively electrically connected to two different conductive layers. The above two different conductive layers are at least partially stacked, and are the DC input conductive path of the power unit. The current flows in opposite directions in the above two different conductive layers, having a negative mutual inductance, forming a mutual inductance cancellation effect so as to reduce the total parasitic inductance in the power unit. And in the embodiment of the present application, at least part of the two conductive layers are stacked to form a stacked structure, so that the distance between the conductive planes formed by the two is extremely small. Generally, the closer the distance, the better the mutual inductance cancellation effect. Therefore, the embodiment of the present application helps to reduce the parasitic inductance inside the power unit.

[0049] Some of the additional aspects and advantages of the present application will be given in the following description, some will become obvious from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0050] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, in which:

[0051] Figure 1 is a schematic structural diagram of a power chip in an embodiment of the present application;

[0052] Figure 2 is a schematic cross-sectional structural diagram of a power unit in an embodiment of the present application;

[0053] Figure 3 is a top view schematic diagram of a power unit in an embodiment of the present application;

[0054] Figure 4 is a top view schematic diagram of the upper surface of the first substrate in an embodiment of the present application;

[0055] Figure 5Schematic diagram of the connection of the power unit in the embodiment of the present application Figure 1 ;

[0056] Figure 6 Schematic diagram of the connection of the power unit in the embodiment of the present application Figure 2 ;

[0057] Figure 7 Schematic diagram of the structure of the power unit with connection terminals in the embodiment of the present application Figure 1 ;

[0058] Figure 8 Schematic diagram of the structure of the power unit with connection terminals in the embodiment of the present application Figure 2 ;

[0059] Figure 9 is Figure 7 equivalent circuit diagram of the power unit in the shown embodiment;

[0060] Figure 10 Top view schematic diagram of another power unit in the embodiment of the present application;

[0061] Figure 11 is Figure 10 top view schematic diagram of the first substrate in the shown embodiment;

[0062] Figure 12 is Figure 10 top view schematic diagram of the second substrate in the shown embodiment;

[0063] Figure 13 is Figure 10 schematic diagram of the connection of the power unit in the shown embodiment Figure 3 ;

[0064] Figure 14 Schematic diagram of the structure of the power unit with connection terminals in the embodiment of the present application Figure 3 ;

[0065] Figure 15 Schematic diagram of the structure of the three-phase full-bridge power module in the embodiment of the present application Figure 1 ;

[0066] Figure 16 Schematic diagram of the structure of the three-phase full-bridge power module in the embodiment of the present application Figure 2

[0067] Figure 17 Schematic diagram of the structure of a power supply system in the embodiment of the present application;

[0068] Figure 18 Schematic diagram of a vehicle in the embodiment of the present application. Detailed implementation manners

[0069] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application.

[0070] As described in the background art, there is currently a problem of excessive parasitic inductance in the power unit packaging structure in the prior art. This excessive parasitic inductance usually causes a series of problems such as turn-off overvoltage, voltage-current oscillation, false switching, and electromagnetic interference during the switching process of the power unit. Moreover, with the application of devices such as SiC and GaN in power units, although they have advantages such as high switching speed and can reduce switching losses, they are also more sensitive to parasitic inductance. Therefore, how to reduce the parasitic inductance in the power unit packaging structure is a technical problem to be solved. During the implementation of the technical solution of the present application, it is found that the commutation inductance inside the commutation unit is the main source of parasitic inductance in the power unit packaging structure. This is mainly because the commutation loop connecting the upper-bridge power chip and the lower-bridge power chip in the prior art is arranged in the same plane and has a large distance, which will result in a large commutation inductance inside the power unit. The technical solution provided by the embodiments of the present application provides a targeted solution to the above problems.

[0071] The embodiments of the present application provide a power unit, a three-phase full-bridge power module including the above power unit, a power supply system, and a vehicle to solve the above technical problems. The half-bridge unit in the power unit provided in the embodiments of the present application includes a first substrate, an upper-bridge power chip and a lower-bridge power chip formed on the first substrate. The second pole of the upper-bridge power chip and the first pole of the lower-bridge power chip, as the AC output terminals, are both electrically connected to the AC output conduction path of the power unit; the first pole of the upper-bridge power chip and the second pole of the lower-bridge power chip, as the DC input terminals, are respectively electrically connected to two different conductive layers. The above two different conductive layers are at least partially stacked and are the DC input conduction path of the power unit. The current flows in opposite directions in the above two different conductive layers, having a negative mutual inductance, forming a mutual inductance cancellation effect to reduce the total parasitic inductance in the power unit. And at least part of the two conductive layers in the embodiments of the present application are stacked to form a stacked structure, so that the distance between the conductive planes formed by the two is extremely small. Generally, the closer the distance, the better the mutual inductance cancellation effect. Therefore, the embodiments of the present application help to reduce the parasitic inductance inside the power unit.

[0072] Specifically, for the power unit provided in the embodiments of the present application, the two conductive layers serving as the DC input conductive path can be at least partially stacked in various ways. For example, the above two conductive layers can be disposed on different surfaces of the first substrate, or by adding more substrates, the above two conductive layers are disposed on different substrates to achieve this.

[0073] In one implementation, it can be as Figures 1 - 7 shown. The power unit therein includes a first substrate 2 and at least one half-bridge unit formed on the first substrate 2. For each half-bridge unit, it can include a first conductive layer 21 and a second conductive layer 22 formed on the upper surface of the first substrate 2; and an upper-bridge power chip 101 is disposed on the first conductive layer 21, and the first pole of the upper-bridge power chip 101 is electrically connected to the first conductive layer 21; a lower-bridge power chip 102 is disposed on the second conductive layer 22, and the second pole of the upper-bridge power chip 101 and the first pole of the lower-bridge power chip 102 are both electrically connected to the second conductive layer 22, and the second conductive layer 22 is the AC output conductive path of the power unit.

[0074] Furthermore, the power unit further includes a second substrate 3. The second substrate 3 is disposed on the first conductive layer 21, and a third conductive layer 31 is formed on the upper surface of the second substrate 3. The third conductive layer 31 and the first conductive layer 21 are at least partially stacked, and the second pole of the lower-bridge power chip 102 is electrically connected to the third conductive layer 31.

[0075] In the above embodiments of the present application, the first conductive layer 21 and the third conductive layer 31 are the DC input conductive paths of the power unit, specifically, they can be the DC positive input conductive path or the DC negative input conductive path. That is, if the first conductive layer 21 is the DC positive input conductive path, then the third conductive layer 31 is the DC negative input conductive path, or if the first conductive layer 21 is the DC negative input conductive path, then the third conductive layer 31 is the DC positive input conductive path.

[0076] In the above embodiments of the present application, the third conductive layer 31 and the first conductive layer 21 are at least partially stacked to form a 3D multi-layer circuit structure, and the current directions of the DC positive input conductive path and the DC negative input conductive path are opposite, which can form good coupling to reduce inductance, and the above stacked structure makes the distance between them smaller, further enhancing the mutual inductance cancellation effect, achieving extremely low parasitic inductance in the power unit.

[0077] For the upper-bridge power chip 101 and the lower-bridge power chip 102 in the above embodiments of the present application, they can be power chips of the same type and structure, or power chips of different types and structures. Figure 1 It is a schematic structural diagram of a power chip in the embodiments of the present application, asFigure 1 As shown, the above-mentioned power chip can be a power chip with a vertical structure, including a first pole 11 located on the bottom surface, a second pole 12 and a control pole 13 located on the top surface, where Figure 1 mainly shows the top surface of the power chip, and the bottom surface is on the opposite side. For some types of power chips, such as in the case of MOSFET, when the second pole 12 is the source pole at this time, the second pole 12 can be partitioned into a power second pole 121 and a drive second pole 122, so as to be connected to the external power circuit and drive circuit respectively, but the two are connected inside the chip and have equal potentials; or in some cases, the second pole 12 is not partitioned, and at this time the second pole 12 can be connected to the power circuit and the drive circuit at the same time. The above two types of power chips have no difference in function and can both be applied to the technical solution of this application. In the embodiments of this application, the types of the power chips include but are not limited to vertical structure chips such as MOSFET and IGBT.

[0078] Specifically, if the above upper-bridge power chip 101 and / or lower-bridge power chip 102 is a MOSFET, then the above first pole 11 is the drain, the second pole 12 is the source, and the control pole 13 is the gate. At this time, the above first conductive layer 21 is the DC positive input conductive path of the power unit, and the third conductive layer 31 is the DC negative input conductive path of the power unit; or, the above first pole 11 is the source, the second pole 12 is the drain, and the control pole 13 is the gate. At this time, the above first conductive layer 21 is the DC negative input conductive path of the power unit, and the third conductive layer 31 is the DC positive input conductive path of the power unit.

[0079] In some other cases, when the upper-bridge power chip 101 and / or lower-bridge power chip 102 is an IGBT, at this time the above first pole 11 is the collector, the second pole 12 is the emitter, and the control pole 13 is the gate. At this time, the above first conductive layer 21 is the DC positive input conductive path of the power unit, and the third conductive layer 31 is the DC negative input conductive path of the power unit; or, the above first pole 11 is the emitter, the second pole 12 is the collector, and the control pole 13 is the gate. At this time, the above first conductive layer 21 is the DC negative input conductive path of the power unit, and the third conductive layer 31 is the DC positive input conductive path of the power unit.

[0080] In a specific embodiment, it is possible that both the upper-bridge power chip 101 and the lower-bridge power chip 102 described above are MOSFETs, or both are IGBTs, or the upper-bridge power chip 101 uses a MOSFET and the lower-bridge power chip 102 uses an IGBT, or the upper-bridge power chip 101 uses an IGBT and the lower-bridge power chip 102 uses a MOSFET. However, the electrode types and connection relationships of each power chip shall all refer to the above description.

[0081] In the subsequent embodiments of this application, mainly taking the case where both the upper-bridge power chip 101 and the lower-bridge power chip 102 are MOSFETs as an example for illustration, and the first electrode is the drain and the second electrode is the source.

[0082] Figure 2 It is a schematic cross-sectional structure diagram of a power unit in an embodiment of this application, as Figure 2 shown. The power unit includes a first substrate 2 and a half-bridge unit located on the first substrate. Specifically, the half-bridge unit may include a second substrate 3, an upper-bridge power chip 101, and a lower-bridge power chip 102. The second substrate 3 is disposed on the upper surface of the first substrate 2 to form a stacked substrate. At the same time, the upper-bridge power chip 101 and the lower-bridge power chip 102 are also disposed on the upper surface of the first substrate 2.

[0083] Specifically, the first substrate 2 may be a ceramic substrate with double-sided copper cladding, such as an AMB substrate, a DBC substrate, etc. The ceramic substrate is a first insulating substrate 20, and its main functions are support, insulation, and heat conduction. Copper layers can be disposed on both the upper surface and the lower surface of the ceramic substrate. For example, a first copper layer is disposed on the upper surface and a second copper layer is disposed on the lower surface. The main function of the first copper layer on the upper surface is for conduction, and the required pattern can be obtained through etching, such as the first conductive layer 21 and the second conductive layer 22 described above. The main function of the second copper layer is for heat conduction and can be connected to a heat sink.

[0084] The second substrate 3 has a relatively small demand for a large amount of heat conduction, and there are various structural options. For example, the second substrate 3 can also be optionally double-sided copper clad, with a second insulating substrate 30 in the middle, such as a ceramic substrate like an AMB substrate, a DBC substrate, etc., or a thick copper PCB board, an FPC flexible substrate, etc. At this time, the above-mentioned second substrate 3 can be connected to the first substrate 2 through a connection layer 4. The main function of the second insulating substrate 30 is to provide support and insulation. The above-mentioned second substrate 3 can also be selected to have only a third copper layer disposed on its upper surface as the above-mentioned third conductive layer 31. At this time, the second insulating substrate 30 can additionally have an adhesive ability, and the third copper layer is adhered to the upper surface of the first substrate 2 through the second insulating substrate 30.

[0085] In the embodiments of the present application, a copper layer is used to prepare each conductive layer, and other materials with conductive properties can also be used to prepare the conductive layer.

[0086] In some embodiments, as Figure 2 shown, the upper bridge power chip 101 and the lower bridge power chip 102 therein can also be connected to the upper surface of the first substrate 2 through the connection layer 4, and the connection layer 4 has good electrical and thermal conductivity. Optionally, the connection layer 4 can be a sintered silver layer or a solder layer, and the corresponding connection process can be sintering or soldering.

[0087] In the above embodiments of the present application, the first copper layer on the upper surface of the first substrate 2 and the third copper layer on the upper surface of the second substrate 3 constitute a stacked conductive plane. Generally speaking, for two adjacent conductors, when the current directions therein are opposite, there is a negative mutual inductance, forming a mutual inductance cancellation effect to reduce the total parasitic inductance in the power unit, and the closer the conductors are, the better the mutual inductance cancellation effect. Therefore, compared with the traditional power unit, the first copper layer and the third copper layer in the embodiments of the present application have a stacked structure, so that the distance between the conductive planes formed by the two is extremely small, which helps to achieve extremely low parasitic inductance.

[0088] Figure 3 is a top view schematic diagram of a power unit in the embodiments of the present application. As described in the above embodiments, when the first copper layer is provided on the upper surface of the first substrate 2, the first conductive layer 21 and the second conductive layer 22 can be obtained through an etching process. In addition, a fourth conductive layer 23 can be formed on the upper surface of the first substrate 2, and the fourth conductive layer 23 is electrically connected to the gate 13 of the control electrode of the upper bridge power chip 101; and a fifth conductive layer 26 is also formed on the upper surface of the first substrate 2, and the fifth conductive layer 26 is electrically connected to the control electrode 13 of the lower bridge power chip 102. For a MOSFET, the above control electrode 13 is a gate, and for an IGBT, the above control electrode 13 is a gate.

[0089] In some embodiments, as described above, when the second poles 12 of the upper bridge power chip 101 and the lower bridge power chip 102 can be divided into a power second pole 121 and a drive second pole 122, a sixth conductive layer 24 and a seventh conductive layer 25 can also be formed on the upper surface of the first substrate 2. At this time, the power second pole 121 of the upper bridge power chip 101 is electrically connected to the second conductive layer 22, and the drive second pole 122 of the upper bridge power chip 102 is electrically connected to the sixth conductive layer 24 to form a Kelvin connection; at the same time, the power second pole 121 of the lower bridge power chip 102 is electrically connected to the third conductive layer 31, and the drive second pole 122 of the upper bridge power chip 102 is electrically connected to the seventh conductive layer 25 to form a Kelvin connection.

[0090] For a MOSFET, the above-mentioned driving second pole 122 is the driving source pole. Additionally, as can be seen from Figure 3 the number of the upper-bridge power chips 101 and the lower-bridge power chips 102 therein is at least two, and the above-mentioned at least two upper-bridge power chips 101 and at least two lower-bridge power chips 102 all extend along the length direction of the first substrate 2, i.e., the A direction, while each conductive layer is arranged along the B direction. Among them, for the number of the upper-bridge power chips 101 and the lower-bridge power chips 102 in the half-bridge unit, it can also be more, and can continue to extend along the length direction A.

[0091] Figure 4 is a top view schematic diagram of the upper surface of the first substrate in the embodiment of the present application. As Figure 4 shown, in the width direction of the first substrate, the fourth conductive layer 23, the first conductive layer 21, the second conductive layer 22, and the fifth conductive layer 26 of the half-bridge unit are arranged in sequence. In addition, when there is a need, a sixth conductive layer 24 can be formed between the fourth conductive layer 23 and the first conductive layer 21, and a seventh conductive layer 25 can be formed between the second conductive layer 22 and the fifth conductive layer 26.

[0092] In some cases, for example, when the driving second poles 122 of the upper-bridge power chips 101 and the lower-bridge power chips 102 are not separately provided, in this case, the above-mentioned sixth conductive layer 24 and seventh conductive layer 25 do not need to be formed on the upper surface of the first substrate 2. For the specific positions of the sixth conductive layer 24 and the seventh conductive layer 25, and the fourth conductive layer 23 and the fifth conductive layer 26, the sixth conductive layer 24 and the seventh conductive layer 25 can also be arranged on the outside.

[0093] Additionally, in the embodiment of the present application, the second substrate 3 can be fixed on one side of the first conductive layer 21 adjacent to the second conductive layer 22 through the connection layer 4, and the upper-bridge power chip 101 is located on one side of the first conductive layer 21 away from the second conductive layer 22.

[0094] Figure 5 and Figure 6 is a connection schematic diagram of the power unit in the embodiment of the present application. As Figure 5 and Figure 6 shown, and referring to the structures of the upper-bridge power chip 101 and the lower-bridge power chip 102 shown in Figure 1 the second pole 12 of the upper-bridge power chip 101 can be electrically connected to the second conductive layer 22 through the first connection line, and the first connection line straddles the second substrate 3. Among them, the above-mentioned first connection line can be Figure 5 the first bonding wire 51 in the example shown in Figure 6 or the first copper sheet 62 in the embodiment shown in

[0095] The second pole 12 of the lower-bridge power chip 102 can be electrically connected to the third conductive layer 31 through a second connection line. Among them, the above-mentioned second connection line can be Figure 5 the second bonding wire 52 in the illustrated example, or can also be Figure 6 the second copper sheet 61 in the illustrated embodiment.

[0096] In addition, for the control poles 13 of the upper-bridge power chip 101 and the lower-bridge power chip 102, they can be electrically connected to the above-mentioned fourth conductive layer 23 and fifth conductive layer 26 respectively through a third connection line. Specifically, the above-mentioned third connection line can be the third bonding wire 53. And in the case where the second poles 12 of the above-mentioned upper-bridge power chip 101 and lower-bridge power chip 102 can be divided into a power second pole 121 and a drive second pole 122, it can be that the above-mentioned power second pole 121 is electrically connected to the second conductive layer 22 through a first connection line and is electrically connected to the third conductive layer 31 through a second connection line; while the drive second poles 122 of the upper-bridge power chip 101 and the lower-bridge power chip 102 can be electrically connected to the sixth conductive layer 24 and the seventh conductive layer 25 respectively through a fourth connection line, and this fourth connection line can be the fourth bonding wire 54. In the above Figure 5 and Figure 6 illustrated embodiment, the difference between the first connection line and the second connection line is whether to select a bonding wire or a copper sheet. For the case of using the copper sheet 61, it can be connected to the second pole 12 of the power chip, such as the power second pole 121, as well as the second conductive layer 22 and the third conductive layer 31, through welding or sintering. For the above-mentioned third connection line and fourth connection line, bonding wires are usually used to achieve the connection.

[0097] Figure 7 and Figure 8 are schematic structural diagrams of the connection terminals provided for the power unit in the embodiments of the present application. As Figure 7 and Figure 8 shown, corresponding connection terminals are provided for each conductive layer of the power unit in the embodiments of the present application. For example, a DC positive input terminal 71 and a DC negative input terminal 72 are provided, and they can be electrically connected to one of the above-mentioned first conductive layer 21 and third conductive layer 31 respectively. For example Figure 7 and Figure 8As shown, the DC positive input terminal 71 is electrically connected to the first conductive layer 21, and the DC negative input terminal 72 is electrically connected to the third conductive layer 31. At this time, correspondingly, the first pole 11 of the above-mentioned upper-bridge power chip 101 and lower-bridge power chip 102 can be the drain, and the second pole 12 can be the source. The first conductive layer 21 is the DC positive circuit of the power unit, and the third conductive layer 31 is the DC negative input conductive path of the power unit. In some other embodiments, it can also be that the DC positive input terminal 71 is electrically connected to the third conductive layer 31, and the DC negative input terminal 72 is electrically connected to the first conductive layer 21.

[0098] Furthermore, it further includes an AC output terminal 73, which can be electrically connected to the second conductive layer 22. Through the AC output terminal 73, the alternating current converted by the power unit can be output.

[0099] Furthermore, it can also include:

[0100] The first upper-bridge drive terminal 74, which is electrically connected to the above-mentioned fourth conductive layer 23;

[0101] The first lower-bridge drive terminal 75, which is electrically connected to the above-mentioned fifth conductive layer 26;

[0102] The second upper-bridge drive terminal 76, which is electrically connected to the above-mentioned sixth conductive layer 24;

[0103] The second lower-bridge drive terminal 77, which is electrically connected to the above-mentioned seventh conductive layer 25.

[0104] The above-mentioned various terminals are set according to actual needs, including one or more of them. For the specific setting methods, Figure 7 and Figure 8 different embodiments are given respectively.

[0105] As Figure 7 shown, the DC positive input terminal 71 and the DC negative input terminal 72 are set at the first end of the first substrate 2 along the length direction. The two have a certain insulation distance and are at least partially stacked. The stacked setting can reduce the parasitic inductance introduced by the above-mentioned DC positive input terminal 71 and DC negative input terminal 72; at the same time, the AC output terminal 73 is set at the second end of the first substrate along the length direction; the AC output terminal 73 is set at the other end in the length direction, which is convenient for the layout of the external circuit. For each drive terminal, it can be set at the first end or the second end.

[0106] In the embodiments of the present application, each of the terminals can be connected to the corresponding conductive layer by means of ultrasonic welding, soldering and sintering.

[0107] In addition, as Figure 8As shown, the above-mentioned DC positive input terminal 71, DC negative input terminal 72, and AC output terminal 73 can also be all arranged in the middle section of the first substrate 2 in the length direction. Moreover, the DC positive input terminal 71 and the DC negative input terminal 72 are arranged adjacent to each other, which can reduce the parasitic inductance introduced by the terminals. And each of the above terminals is led out vertically upward. And, as Figure 8 shown, the upper-bridge power chip 101 is divided into two groups, which are respectively located on both sides of the DC positive input terminal 71, and the lower-bridge power chip 102 is divided into two groups, which are respectively located on both sides of the AC output terminal 73. The above terminal arrangement method can further reduce the parasitic inductance introduced by the conductors inside the power unit and can effectively improve the dynamic current sharing.

[0108] Figure 9 For Figure 7 the equivalent circuit diagram of the power unit in the shown embodiment, as Figure 9 shown, the overall commutation loop is as follows: The positive pole of the DC current is connected to the first conductive layer 21 through the DC positive input terminal 71. The first conductive layer 21 is connected to the first pole of the upper-bridge power chip 101, and this first pole is the drain. The second power pole of the upper-bridge power chip 101, that is, the power source pole, is connected to the second conductive layer 22. The second conductive layer 22 is connected to the first pole of the lower-bridge power chip 102. The second power pole of the lower-bridge power chip 102, that is, the power source pole, is connected to the third conductive layer 31. The third conductive layer 31 is connected to the DC negative input terminal 72, and finally, it can be connected to the negative pole of the DC power supply through the DC negative input terminal 72; The second conductive layer 22 is electrically connected to the AC output terminal 73, and thus can be connected to an external output load.

[0109] For the power unit in the embodiment of the present application, parasitic inductance will be introduced in each section of the conductor on the overall commutation loop. Among them, the inductance introduced by the first conductive layer 21 and the third conductive layer 31 usually accounts for the main part. As Figure 9 shown, taking the connection positions of each power chip as nodes, the main inductances are segmented, and the parasitic inductance introduced by the conductive layer between two adjacent power chips is marked. The self-inductance of each section of the conductive layer on the first conductive layer 21 is L1, the self-inductance of each section of the conductive layer on the third conductive layer 31 is L2, and the mutual inductance between the two is M. The total inductance of this section of the first conductive layer 21 and the third conductive layer 31 acting on the commutation loop is L = L1 + L2 + 2*M.

[0110] The above-mentioned inductance L is the main component of the inductor of the power unit and is also the main factor causing dynamic current sharing imbalance, which needs to be reduced as much as possible. When connected to the positive and negative poles of the direct power supply respectively, the above-mentioned mutual inductance M is negative. Therefore, the total inductance of the loop can be reduced by strengthening the coupling between the first conductive layer 21 and the third conductive layer 31; the coupling coefficient is related to the distance between the two conductive layers. The smaller the distance, the larger the coupling coefficient and the smaller the total parasitic inductance.

[0111] Compared with the planar structure of the traditional layout, the stacked structure proposed in the embodiment of the present application can greatly reduce the overall distance between the first conductive layer 21 and the third conductive layer 31, so that the coupling coefficient is higher and extremely low parasitic inductance can be achieved. By simulating the technical solution provided in the embodiment of the present application, the simulation results show that Figure 7 In the shown embodiment, the coupling coefficient between each section of the first conductive layer 21 and the third conductive layer 31 reaches -0.85, while the coupling coefficient between the planar commutation loops in the traditional power unit is about -0.05 to -0.5. Figure 7 The inductance introduced by the commutation loop inside the shown power unit (including the AMB substrate and the connection lines between the power chips) is only about 1 - 2 nH, which is much lower than 5 - 10 nH of the traditional power unit. Therefore, the technical solution provided in the embodiment of the present application can effectively reduce the parasitic inductance introduced by the conduction path inside the power unit and effectively improve dynamic current sharing.

[0112] In the above-mentioned embodiment of the present application, it can be expanded in the width direction of the first substrate to expand more half-bridge units. The expanded half-bridge units can be arranged in parallel to form a half-bridge module with a larger current-carrying capacity. The specific number of expansions can be set according to actual needs. For example, one more half-bridge unit can be expanded. Figure 10 This is a top view schematic diagram of another power unit in the embodiment of the present application. As Figure 10 shown, the power unit includes a first substrate 2 and two half-bridge units formed on the first substrate 2, namely the first half-bridge unit 1001 and the second half-bridge unit 1002. For the above-mentioned first half-bridge unit 1001 and second half-bridge unit 1002, they can respectively have the structural features described in the above embodiment.

[0113] In addition, Figure 11 This is Figure 10 a top view schematic diagram of the first substrate in the shown embodiment, Figure 12 This is Figure 10 a top view schematic diagram of the second substrate in the shown embodiment, Figure 13 This is Figure 10 a connection schematic diagram of the power unit in the shown embodiment Figure 3 ., referring to the above-mentioned attached Figures 10 - 13As shown, on the first substrate 2, the conductive layers that are close in position and have the same function in the first half-bridge unit 1001 and the second half-bridge unit 1002 can be combined or connected, so as to optimize the layout, improve the integration degree and performance. For example, the second conductive layers 22 of the first half-bridge unit 1001 and the second half-bridge unit 1002 are interconnected with each other to form an integrally arranged structure. The first conductive layer 21 of the first half-bridge unit 1001 and the first conductive layer 21 of the second half-bridge unit 1002 can be respectively arranged on the outer sides in the width direction of the integrally arranged second conductive layer 22.

[0114] In some embodiments, as described above Figure 11 shown, a connection structure can also be added so that the first conductive layers 21 of the above two half-bridge units are also electrically connected to form an integrally arranged structure. Specifically, electrical connection can be achieved through bonding wires, copper sheets, etc., or as Figure 11 shown, an interconnection conductive layer 29 that is connected to the first conductive layers on both sides is formed on the upper surface of the first substrate to form an integral first conductive layer.

[0115] Based on the above embodiments, at least one of the fourth conductive layer 23 electrically connected to the control electrodes of the upper-bridge power chips 101 of the two half-bridge units, and the sixth conductive layer 24 electrically connected to the driving second poles of the upper-bridge power chips 101 of the two half-bridge units can be arranged on the outer sides in the width direction of the above first conductive layer 21. And for the fifth conductive layer 25 electrically connected to the control electrodes of the lower-bridge power chips 102 of the two half-bridge units, and at least one of the seventh conductive layer 26 electrically connected to the driving second poles of the lower-bridge power chips 102 of the two half-bridge units, they can be arranged in the hollowed-out area 27 in the middle of the second conductive layer 22. The lower-bridge power chips 102 of the first half-bridge unit 1001 and the second half-bridge unit 1002 are respectively arranged on both sides of the hollowed-out area 27.

[0116] Specifically, referring to Figure 11 and Figure 13 shown in the embodiments, the hollowed-out area 27 includes a plurality of sub-hollowed-out areas. And for the above fifth conductive layer 25 and seventh conductive layer 26, they can include a plurality of sub-conductive layers respectively arranged in the above different sub-hollowed-out areas. Among them, the plurality of sub-conductive layers of the fifth conductive layer 25 can be electrically connected to each other, and the plurality of sub-conductive layers of the seventh conductive layer 26 can also be electrically connected to each other. And the control electrodes of the lower-bridge power chips 102 are respectively connected to the adjacent sub-conductive layers of the fifth conductive layer 25, and the driving electrodes of the lower-bridge power chips 102 are respectively connected to the adjacent sub-conductive layers of the seventh conductive layer 26.

[0117] In some embodiments, still referring to the above Figure 11 andFigure 13 In the illustrated embodiment, when the hollowed-out area 27 is provided, a conductive connection layer 28 can be provided in the hollowed-out area 27 located at the edge of the first substrate 2. The fourth conductive layer 23 of the first half-bridge unit 1001 and the fourth conductive layer 23 of the second half-bridge unit 1002 are electrically connected through the above-mentioned conductive connection layer 28, and / or the sixth conductive layer 24 of the first half-bridge unit 1001 and the sixth conductive layer 24 of the second half-bridge unit 1002 can also be electrically connected through the conductive connection layer 28.

[0118] As Figure 13 shown, the case of electrical connection by bonding wires is taken as an example for illustration. Among them, the second pole of the upper-bridge power chip 101 of the two half-bridge units can be electrically connected to the second conductive layer 22 through the first bonding wire 51, and the first bonding wire 51 straddles the second substrate 3. In some embodiments, the second pole 12 of the lower-bridge power chip 102 of the two half-bridge units can be electrically connected to the third conductive layer 31 through the second bonding wire 52. The above-mentioned first bonding wire 51 and second bonding wire 52 can both be replaced by copper sheets.

[0119] In addition, for the control poles 13 of the upper-bridge power chip 101 and the lower-bridge power chip 102, they can be respectively electrically connected to the above-mentioned fourth conductive layer 23 and fifth conductive layer 26 through the third bonding wire 53. And when the second poles 12 of the above-mentioned upper-bridge power chip 101 and lower-bridge power chip 102 can be divided into a power second pole and a drive second pole, it can be that the above-mentioned power second pole 121 is respectively electrically connected to the second conductive layer 22 through the first bonding wire 51 and electrically connected to the third conductive layer 31 through the second bonding wire 52; while the drive second poles 122 of the upper-bridge power chip 101 and the lower-bridge power chip 102 can be respectively electrically connected to the sixth conductive layer 24 and the seventh conductive layer 25 through the fourth bonding wire 54.

[0120] For the two fourth conductive layers 23 provided outside the second conductive layer 22, they can be respectively connected to the conductive connection layer 28 in the hollowed-out area through the third bonding wire 53, and for the two sixth conductive layers 24 provided outside the second conductive layer 22, they can be connected to the conductive connection layer 28 in the hollowed-out area through the fourth bonding wire 54.

[0121] Figure 14 Structural schematic of the power unit for setting connection terminals in the embodiment of the present application Figure 3 As Figure 14As shown, the DC positive connection terminal 71 is electrically connected to the first conductive layer 21, the DC negative connection terminal 72 is electrically connected to the third conductive layer 31, and both the DC positive connection terminal 71 and the DC negative connection terminal 72 are provided at the first end of the first substrate and are at least partially stacked, which can effectively reduce the parasitic inductance. In addition, for the AC output terminal 73, it can be provided at the second end of the first substrate, and further includes:

[0122] The first upper bridge drive terminal 74 is electrically connected to the above-mentioned fourth conductive layer 23;

[0123] The first lower bridge drive terminal 75 is electrically connected to the above-mentioned fifth conductive layer 26;

[0124] The second upper bridge drive terminal 76 is electrically connected to the above-mentioned sixth conductive layer 24;

[0125] The second lower bridge drive terminal 77 is electrically connected to the above-mentioned seventh conductive layer 25.

[0126] In the embodiment of the present application, the number of required half-bridge units can be selected according to the power requirement to obtain different power ranges, and its structure can be expanded in the manner described in the above embodiment to be applicable to an extremely wide power range.

[0127] In the embodiment of the present application, a three-phase full-bridge power module is also provided. Figure 15 and Figure 16 is a schematic structural diagram of the three-phase full-bridge power module in the embodiment of the present application. Figure 16 is based on Figure 15 and the housing 9 is added. As Figure 15 and Figure 16 shown, the three-phase full-bridge power module includes three Figures 1 - 14 any of the power units shown, as well as a heat sink 8 and a housing 9; the lower surfaces of the first substrates 2 in the three power units are all fixed on the above-mentioned heat sink 8, and the housing 9 covers the three power units. Specifically, an opening can be made in the housing 9 to expose at least one of the DC positive input terminal, direct negative input terminal, AC output terminal, first upper bridge drive terminal, second upper bridge drive terminal, first lower bridge drive terminal, and second lower bridge drive terminal of each of the above-mentioned power units.

[0128] Among them, the above-mentioned heat sink 8 can play a role in mechanical fixation and heat conduction, and as described in the above embodiment, the first substrate 2 can have copper layers provided on both the upper surface and the lower surface. The copper layer on the upper surface has been etched into each conductive layer in the power unit, and the copper layer on the lower surface mainly plays a role in heat conduction. At this time, it can be connected to the above-mentioned heat sink 8 to achieve good heat dissipation. In addition, for the above-mentioned housing 9, it mainly plays a role in protection and insulation.

[0129] The three-phase full-bridge power module provided by the embodiment of the present application, because it includes Figures 1 - 14 any of the shown power units, and in each power unit, since the first conductive layer 21 and the third conductive layer 31 are stacked, and the first conductive layer 21 and the third conductive layer 31 are respectively connected to the DC positive input terminal and the DC negative input terminal, so that the current directions in the first conductive layer 21 and the third conductive layer 31 are opposite, thus having a negative mutual inductance, forming a mutual inductance cancellation effect, thereby reducing the total parasitic inductance in the power unit, and being able to effectively improve dynamic current sharing.

[0130] Figure 17 is a schematic structural diagram of a power supply system in an embodiment of the present application, as Figure 17 shown, the power supply system therein includes a battery 171 and the above-mentioned three-phase full-bridge power module 172. The battery 171 can output direct current, and this direct current can be converted into alternating current by the three-phase full-bridge power module 172 and further output to electrical equipment that needs to operate with alternating current. The power supply system provided by the embodiment of the present application has the technical features and technical effects in the above embodiment, which will not be elaborated in this embodiment.

[0131] Figure 18 is a schematic structural diagram of a vehicle in an embodiment of the present application, as Figure 18 shown, the vehicle therein includes the above-mentioned power supply system 18, and the above-mentioned power supply system 18 can supply power to each electrical equipment on the vehicle. For example, for some electrical equipment that uses alternating current, the three-phase full-bridge power module in the power supply system 18 can convert direct current into alternating current. This embodiment has the corresponding technical features and technical effects recorded in the above embodiment, which will not be elaborated in this embodiment.

[0132] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same type, and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally represents an "or" relationship between the associated objects before and after.

[0133] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0134] In the description of the present application, the "first feature" and "second feature" may include one or more of such features.

[0135] In the description of the present application, the meaning of "a plurality" is two or more.

[0136] In the description of the present application, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween.

[0137] In the description of the present application, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature.

[0138] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0139] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A power unit, characterized in that: It includes a first substrate and at least one half-bridge unit formed on the first substrate, wherein the half-bridge unit includes an upper bridge power chip and a lower bridge power chip, the second pole of the upper bridge power chip and the first pole of the lower bridge power chip are both electrically connected to the AC output conductive path of the power unit, the first pole of the upper bridge power chip and the second pole of the lower bridge power chip are respectively electrically connected to two different conductive layers, the two different conductive layers are at least partially stacked, and the two different conductive layers are respectively the DC input conductive paths of the power unit.

2. The power unit according to claim 1, characterized in that: A first conductive layer and a second conductive layer are formed on the upper surface of the first substrate; An upper bridge power chip is arranged on the first conductive layer, and a first electrode of the upper bridge power chip is electrically connected to the first conductive layer; A lower bridge power chip is arranged on the second conductive layer, the second pole of the upper bridge power chip and the first pole of the lower bridge power chip are electrically connected to the second conductive layer, and the second conductive layer is an AC output conductive path of the power unit; The power unit further includes: A second substrate is arranged on the first conductive layer, and a third conductive layer is formed on the upper surface of the second substrate, the third conductive layer and the first conductive layer are at least partially stacked, and the second electrode of the lower bridge power chip is electrically connected to the third conductive layer; The first conductive layer and the third conductive layer are direct current input conductive paths of the power unit.

3. The power unit according to claim 2, characterized in that: The upper bridge power chip and / or the lower bridge power chip is a MOSFET, the first pole is a drain, the second pole is a source, the first conductive layer is a DC positive input conductive path of the power unit, and the third conductive layer is a DC negative input conductive path of the power unit.

4. The power unit according to claim 2, characterized in that: The upper bridge power chip and / or the lower bridge power chip is an IGBT, the first pole is a collector, the second pole is an emitter, the first conductive layer is a DC positive input conductive path of the power unit, and the third conductive layer is a DC negative input conductive path of the power unit.

5. The power unit according to any one of claims 2 to 4, characterized in that: A fourth conductive layer is also formed on the upper surface of the first substrate, and the fourth conductive layer is electrically connected to the control electrode of the upper bridge power chip; A fifth conductive layer is also formed on the upper surface of the first substrate, and the fifth conductive layer is electrically connected to the control electrode of the lower bridge power chip.

6. The power unit according to claim 5, characterized in that: The number of the upper bridge power chips and the number of the lower bridge power chips are at least two, and the at least two upper bridge power chips and the at least two lower bridge power chips extend along the length direction of the first substrate, and in the width direction of the first substrate, the fourth conductive layer, the first conductive layer, the second conductive layer and the fifth conductive layer of the half-bridge unit are arranged in sequence.

7. The power unit according to claim 5, characterized in that: The second electrode includes a power second electrode and a driving second electrode, and a sixth conductive layer and a seventh conductive layer are further formed on the upper surface of the first substrate; The power second electrode of the upper bridge power chip is electrically connected to the second conductive layer, and the driving second electrode of the upper bridge power chip is electrically connected to the sixth conductive layer to form a Kelvin connection; The power second electrode of the lower bridge power chip is electrically connected to the third conductive layer, and the driving second electrode of the lower bridge power chip is electrically connected to the seventh conductive layer, forming a Kelvin connection.

8. The power unit according to claim 7, characterized in that: The upper bridge power chip, the lower bridge power chip and the second substrate are fixed on the upper surface of the first substrate through a connection layer.

9. The power unit according to claim 8, characterized in that: The second substrate is fixed on a side of the first conductive layer adjacent to the second conductive layer through a connecting layer, and the upper bridge power chip is located on a side of the first conductive layer away from the second conductive layer.

10. The power unit according to claim 9, characterized in that: The second electrode of the upper bridge power chip is electrically connected to the second conductive layer through a first connecting line, and the first connecting line crosses the second substrate; The second electrode of the lower bridge power chip is electrically connected to the third conductive layer through a second connecting line.

11. The power unit according to claim 10, characterized in that: The first connecting wire is one of a bonding wire and a copper sheet; the second connecting wire is one of a bonding wire and a copper sheet.

12. The power unit according to claim 7, characterized in that: The first substrate includes a first insulating substrate, a first copper layer located on an upper surface of the first insulating substrate, and a second copper layer located on a lower surface of the first insulating substrate, wherein the first copper layer is etched to obtain at least one of the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer; The second substrate includes a second insulating substrate and a third copper layer located on the upper surface of the second insulating substrate, and the third copper layer serves as the third conductive layer.

13. The power unit according to claim 7, characterized in that: Also includes at least one of the following: A DC positive input terminal and a direct negative input terminal are electrically connected to one of the first conductive layer and the third conductive layer respectively; an AC output terminal, electrically connected to the second conductive layer; A first upper bridge driving terminal, electrically connected to the fourth conductive layer; A first lower bridge driving terminal is electrically connected to the fifth conductive layer; A second upper bridge driving terminal is electrically connected to the sixth conductive layer; The second lower bridge driving terminal is electrically connected to the seventh conductive layer.

14. The power unit according to claim 13, characterized in that: The DC positive input terminal and the direct negative input terminal are arranged at a first end of the first substrate along the length direction, and are at least partially stacked; The AC output terminal is disposed at a second end of the first substrate along the length direction.

15. The power unit according to claim 13, characterized in that: The DC positive input terminal, the direct negative input terminal and the AC output terminal are all arranged in the middle section of the first substrate in the length direction, and the DC positive input terminal and the direct negative input terminal are arranged adjacent to each other.

16. The power unit according to claim 13, wherein two half-bridge units are formed on the first substrate, namely a first half-bridge unit and a second half-bridge unit; The second conductive layer of the first half-bridge unit and the second conductive layer of the second half-bridge unit are integrally arranged, and the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are respectively arranged outside the integrally arranged second conductive layer in the width direction.

17. The power unit according to claim 16, characterized in that: The first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are electrically connected through an interconnect conductive layer.

18. The power unit according to claim 17, characterized in that: The fourth conductive layer and the sixth conductive layer are arranged outside the first conductive layer in the width direction; The fifth conductive layer and the seventh conductive layer are arranged in a hollow area in the middle of the second conductive layer, and the lower bridge power chip of the first half-bridge unit and the lower bridge power chip of the second half-bridge unit are respectively arranged on both sides of the hollow area.

19. The power unit according to claim 18, characterized in that: The hollow area includes a plurality of sub-hollow areas, the fifth conductive layer and the seventh conductive layer include a plurality of sub-conductive layers respectively arranged in the sub-hollow areas, the plurality of sub-conductive layers of the fifth conductive layer are electrically connected to each other, the plurality of sub-conductive layers of the seventh conductive layer are electrically connected to each other, and the control electrode of the lower bridge power chip is respectively connected to the adjacent sub-conductive layer of the fifth conductive layer, and the driving second electrode of the lower bridge power chip is respectively connected to the adjacent sub-conductive layer of the seventh conductive layer.

20. The power unit according to claim 19, characterized in that: A conductive connection layer is arranged in the hollow area located at the edge of the first substrate, and the fourth conductive layer of the first half-bridge unit and the fourth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer, and / or the sixth conductive layer of the first half-bridge unit and the sixth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer.

21. A three-phase full-bridge power module, characterized in that: Comprising three power units as described in any one of claims 1 to 20, as well as a heat sink and a housing; The lower surfaces of the first substrates in the three power units are all fixed on the heat sink, and the housing covers the three power units.

22. A power supply system, characterized in that: It comprises a battery and the three-phase full-bridge power module as claimed in claim 21.

23. A vehicle, characterized in that: A power supply system comprising the power supply system of claim 22.

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