Spinning electronic device

Abstract

A spin electron device includes a substrate, a Ge1-xSnx channel layer, a Ge1-ySny barrier layer, a first opening, a second opening, a first source / drain electrode, a second source / drain electrode, and a first gate electrode. The Ge1-xSnx channel layer is located on the substrate, wherein the Ge1-xSnx channel layer is in a metastable state. The Ge1-ySny barrier layer is located on the Ge1-xSnx channel layer, so that two-dimensional hole gas is formed in the Ge1-xSnx channel layer. The first opening is located in the Ge1-xSnx channel layer and the Ge1-ySny barrier layer. The second opening is located in the Ge1-xSnx channel layer and the Ge1-ySny barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on the Ge1-ySny barrier layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a spintronic device. Background Art

[0002] Quantum computing refers to the field of research on computing systems that utilize quantum mechanical phenomena to manipulate data. Several milestones have been achieved on the roadmap aimed at fabricating scalable silicon-based quantum computers. Quantum computing may involve initializing N quantum bits (or qubits), generating controlled quantum entanglement between them, evolving these states, and reading out the states of the qubits after the evolution. A qubit can be a system with two degenerate (i.e., equal energy) quantum states, and the probability of the system being in either state is non-zero. Therefore, N qubits can define an initial state that is a combination of 2N classical states. Summary of the Utility Model

[0003] According to some embodiments of the present disclosure, a spintronic device includes a substrate, Ge 1-x Sn x channel layer, Ge 1-y Sn y barrier layer, a first opening, a second opening, a first source / drain electrode, a second source / drain electrode, and a first gate electrode. The Ge 1- x Sn x channel layer is located on the substrate, wherein the Ge 1-x Sn x channel layer is in a metastable state. The Ge 1-y Sn y barrier layer is located on the Ge 1-x Sn x channel layer such that a two-dimensional hole gas is formed in the Ge 1-x Sn x channel layer. The first opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The second opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on the Ge 1-y Sn y barrier layer.

[0004] According to some embodiments of the present disclosure, a spintronic device includes a substrate, Ge1-x Sn x Channel layer, Ge 1-y Sn y Barrier layer, first opening, second opening, first source / drain electrode, second source / drain electrode, and first gate electrode. Ge 1- x Sn x The channel layer is located on the substrate. Ge 1-y Sn y The barrier layer is located on Ge 1-x Sn x the channel layer, such that Ge 1-x Sn x a two-dimensional hole gas is formed in the channel layer, wherein Ge 1-y Sn y the barrier layer is in a metastable state. The first opening is located in Ge 1-x Sn x the channel layer and Ge 1-y Sn y the barrier layer. The second opening is located in Ge 1-x Sn x the channel layer and Ge 1-y Sn y the barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on Ge 1-y Sn y the barrier layer.

[0005] According to some embodiments of the present disclosure, a spintronic device includes a substrate, Ge 1-x Sn x channel layer, Ge 1-y Sn y barrier layer, Ge 1-z Sn z buffer layer, first opening, second opening, first source / drain electrode, second source / drain electrode, and first gate electrode. Ge 1-x Sn x The channel layer is located on the substrate, wherein Ge 1-x Sn x the channel layer is in a metastable state. Ge 1-y Sn y The barrier layer is located on Ge 1-x Sn x the channel layer, such that Ge 1-x Sn x a two-dimensional hole gas is formed in the channel layer. Ge 1-z Sn z The buffer layer is located on the substrate, wherein Ge 1-x Sn x the channel layer and Ge1-z Sn z contacts the buffer layer. The first opening is located in Ge 1-x Sn x in the channel layer and Ge 1-y Sn y in the barrier layer. The second opening is located in Ge 1-x Sn x in the channel layer and Ge 1-y Sn y in the barrier layer. The first source / drain electrode is located within the first opening. The second source / drain electrode is located within the second opening. The first gate electrode is located on Ge 1-y Sn y on the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of the present disclosure may be best understood. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 4B Shows top views and cross-sectional views of several stages in the formation of a spintronic device in accordance with some embodiments of the present disclosure;

[0008] Figure 5 Presents the simulated hole density in a GeSn layer plotted against spin-orbit energy (Δ SO ) at different gate voltages in accordance with some embodiments of the present disclosure;

[0009] Figure 6 Presents the simulated stress difference (ε) in the channel layer for different [Sn] (tin concentration) and in the buffer layer for different [Sn] in accordance with some embodiments of the present disclosure;

[0010] Figures 7A to 11B Shows top views and cross-sectional views of several stages in the formation of a spintronic device in accordance with some embodiments of the present disclosure.

[0011]

SYMBOL DESCRIPTION

[0012] 100, 200: Spintronic device

[0013] 110, 210: Substrate

[0014] 120, 220: Base buffer layer

[0015] 130, 230: Channel stack

[0016] 130’: Epitaxial stack

[0017] 132, 132’, 232: First epitaxial layer

[0018] 134, 134’, 234: Second epitaxial layer

[0019] 136, 136’, 236: Third epitaxial layer

[0020] 140: First dielectric layer

[0021] 150, 252, 254, 256, 258: Source / drain electrode

[0022] 160: Gate dielectric layer

[0023] 170: Gate electrode

[0024] 260: First gate dielectric layer

[0025] 280: Second gate dielectric layer

[0026] 290: Third gate dielectric layer

[0027] 312, 314, 316: Restricted gate

[0028] 322, 324, 326, 328: Extended gate

[0029] 332, 334, 336, 338: Accumulated gate

[0030] 341, 342, 343, 346, 347, 348: Bridging gate

[0031] 910, 920, 930: Data

[0032] A - A, A’ - A’, B - B, C - C, D - D: Line segment

[0033] AM, AM’: Alignment mark

[0034] CH1, CH2: Channel region

[0035] D1: Direction

[0036] M1, M2: Path

[0037] O1, O2: Opening

[0038] R1: Recess

[0039] T1, T2, T3: Thickness Detailed implementation manner

[0040] The following disclosure provides many different embodiments or examples for implementing different features of the described subject matter. The following describes specific examples of components and configurations to simplify this specification. Of course, these are merely examples and not restrictive. For example, forming a first feature over or above a second feature in the subsequent description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, this disclosure may reuse reference numerals and / or reference letters in multiple examples. Such reuse is for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0041] Spatial relative terms such as "under", "below", "bottom", "on", "top", etc. may be used herein for purposes of convenience in description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0042] As used herein, "about", "approximately", "substantially" or "roughly" generally mean within 20%, within 10% or within 5% of a given value or range. The quantities given herein are approximate values, representing that the terms "about", "approximately", "substantially" or "roughly" may be implied if not explicitly stated. Those of ordinary skill in the art will understand that dimensions can vary according to different technology nodes. Those of ordinary skill in the art will recognize that dimensions are based on specific device types, technology generations, minimum feature sizes, etc. Therefore, the terms are deliberately interpreted in view of the technology being evaluated.

[0043] As used herein, the term "etch selectivity" refers to the ratio of the etch rates of two different materials under the same etching conditions. As used herein, "high dielectric constant" refers to a dielectric constant greater than that of SiO 2 (i.e., greater than 3.9). As used herein, the term "P-type" refers to a structure, layer, and / or region doped with a P-type dopant such as boron. As used herein, the term "N-type" refers to a structure, layer, and / or region doped with an N-type dopant such as phosphorus. As used herein, the term "conductive" refers to a conductive structure, layer, and / or region. As used herein, the source / drain region may refer to the source or the drain individually or collectively depending on the context.

[0044] Embodiments of the present disclosure provide a spintronic device including a channel stack having a strong spin-orbit coupling (SOC) effect to enhance the quantum computing efficiency of the spintronic device. Also, the SOC effect of the channel stack can be tuned by changing the gate bias of the spintronic device and / or the material composition of the channel stack. In some embodiments, the transistor used in the spintronic device can be a device selected from the group consisting of a planar device, a multi-gate device, a fin field-effect transistor (FinFET), a nanosheet gate field-effect transistor, and a gate-all-around transistor.

[0045] Figures 1A to 4B FIGS. show top views and cross-sectional views of several stages in the formation of a spintronic device 100 according to some embodiments of the present disclosure. In the various views and exemplary embodiments, the same reference numerals are used to label the same elements. It is to be understood that additional operations may be provided before, during, or after the processes shown, and some of the operations described below may be replaced or removed for other embodiments of the method. The order of the operations and processes may be interchanged. Figures 1A to 4B FIGS. show top views and cross-sectional views of several stages in the formation of a spintronic device 100 according to some embodiments of the present disclosure. In the various views and exemplary embodiments, the same reference numerals are used to label the same elements. It is to be understood that additional operations may be provided before, during, or after the processes shown, and some of the operations described below may be replaced or removed for other embodiments of the method. The order of the operations and processes may be interchanged.

[0046] Referring to Figure 1A and Figure 1B where Figure 1B is a cross-sectional view along line A-A of Figure 1A . A substrate 110 is provided or received. In some embodiments, the substrate 110 may include silicon (Si). Alternatively, the substrate 110 may include germanium (Ge), silicon germanium, gallium arsenide, or other suitable semiconductor materials. In some alternative embodiments, the substrate 110 may include an epitaxial layer with or without dopants. Additionally, the substrate 110 may include a silicon-on-insulator (SOI) structure having a buried dielectric layer therein. The buried dielectric layer, for example, may include a buried oxide (BOX) layer. The SOI structure may be formed by a method called oxygen implantation isolation technology, wafer bonding, selective epitaxial growth (SEG), or other suitable methods.

[0047] The base buffer layer 120 is formed on the substrate 110. The base buffer layer 120 and the substrate 110 are made of different materials. In some embodiments, the base buffer layer 120 includes an epitaxial growth layer. The epitaxial growth layer may include a Group-IV compound material, Ge, and / or other suitable materials. In some embodiments, the base buffer layer 120 contacts the substrate 110 and has a different material from the substrate 110. For example, the base buffer layer 120 is a substantially pure germanium layer (i.e., the percentage of germanium atoms is greater than 90%) while the substrate 110 is a substantially pure silicon layer (i.e., the percentage of silicon atoms is greater than 90%). The base buffer layer 120 is configured to reduce the lattice mismatch between the substrate 110 and the layer formed thereon (i.e., the channel stack 130). As used herein, the term "substantially" can be applied to modify any quantitative representation that is allowable to vary without causing a change in its relevant basic function.

[0048] The epitaxial stack 130' is formed on the base buffer layer 120. In some embodiments, the epitaxial stack 130' includes a first epitaxial layer 132', a second epitaxial layer 134', and a third epitaxial layer 136'. In some embodiments, the first epitaxial layer 132', the second epitaxial layer 134', and the third epitaxial layer 136' are made of a Group-IV-IV compound material. The first epitaxial layer 132', the second epitaxial layer 134', and the third epitaxial layer 136' can be formed by one or more epitaxial processes, such as selective epitaxial growth in any suitable epitaxial deposition system. Suitable epitaxial deposition systems include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure (or reduced-pressure) chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In some embodiments, the first epitaxial layer 132', the second epitaxial layer 134', and the third epitaxial layer 136' are in a metastable state.

[0049] Next, an etching process is performed to form an alignment mark AM in the epitaxial stack 130'. For example, a patterned mask layer is formed on the epitaxial stack 130', and the etching process is performed using the patterned mask layer as an etching mask to form the alignment mark AM in the epitaxial stack 130'. In Figure 1A and Figure 1B the alignment mark AM is a trench, an opening, a recess, or other suitable structure.

[0050] Referring to Figure 2A and Figure 2B where Figure 2B is along Figure 2ACross-sectional view of line B-B. Another etching process is performed to pattern the epitaxial stack 130' into a channel stack 130 on the base buffer layer 120. Thus, the channel stack 130 includes a first epitaxial layer 132, a second epitaxial layer 134, and a third epitaxial layer 136. In some embodiments, the channel stack 130 has a rod shape, a rectangular shape, a strip shape, or other suitable shape in a top view. Thus, the channel stack 130 can be regarded as a one-dimensional (1D) channel. The etching process forms a recess R1 to surround the channel stack 130. In some embodiments, the recess R1 extends through the third epitaxial layer 136 and the second epitaxial layer 134, but does not extend through the first epitaxial layer 132. However, in some embodiments, the recess R1 may also extend through the first epitaxial layer 132. Also, as Figure 2A and Figure 1B and Figure 2B shown, the alignment mark AM can be deeper than the recess R1.

[0051] Referring to Figure 3A and Figure 3B , where Figure 3B is a cross-sectional view of line B-B along Figure 3A . The first dielectric layer 140 is formed on the base buffer layer 120 and in the recess R1 (see Figure 2B ). In some embodiments, the first dielectric layer 140 includes, for example, oxides formed by tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxides, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The first dielectric layer 140 can be deposited by a PECVD process or other suitable deposition techniques.

[0052] Next, a plurality of openings O1 are formed in the first dielectric layer 140 and at opposite ends of the channel stack 130. Thus, the end sidewalls of the channel stack 130 are exposed by the openings O1. For example, another patterned mask layer is formed on the channel stack 130 and the first dielectric layer 140, and an etching process is performed using the patterned mask layer as an etching mask to form the openings O1. In some embodiments, the etching process is a selective etching process, and this selective etching process etches the first dielectric layer 140 at a rate faster than that of the channel stack 130.

[0053] After that, a plurality of source / drain electrodes 150 are respectively formed in the openings O1. The source / drain electrodes 150 can be ferromagnetic materials, such as Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd, combinations of the above, or similar materials. In some embodiments, one of the source / drain electrodes 150 serves as a spin filter, and the other source / drain electrode 150 serves as a spin detector.

[0054] Reference Figure 4A and Figure 4B wherein Figure 4B is a cross-sectional view along the B-B line segment of Figure 4A . The gate dielectric layer 160 and the gate electrode 170 are formed on the channel stack 130. For example, a dielectric layer and a conductive layer are sequentially formed on the structures of Figure 3A and Figure 3B , and then the conductive layer and the dielectric layer are patterned to form the gate electrode 170 and the gate dielectric layer 160. In some embodiments, the gate dielectric layer 160 may include silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the gate dielectric layer 160 may be a high-k dielectric layer with a dielectric constant (κ) higher than SiO 2 , i.e., κ > 3.9. The gate dielectric layer 160 may include LaO, Al 2 O 3 , ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO (BST), Si 3 N 4 , silicon oxynitride (SiON), or other suitable materials. The gate dielectric layer 160 is deposited by suitable techniques such as ALD, CVD, PVD, thermal oxidation, a combination of the above, or other suitable techniques.

[0055] The gate electrode 170 is formed on the gate dielectric layer 160. The gate electrode 170 includes one or more layers of conductive materials. Examples of the gate electrode 170 include W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, TiAl, HfTi, TiSi, TiAlC, a combination of the above, or similar materials. The gate electrode 170 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable techniques.

[0056] In Figure 4A and Figure 4BIn [the figure], the spintronic device 100 is a spin FET and includes a channel stack 130, source / drain electrodes 150, and a gate electrode 170. The source / drain electrodes 150 are on opposite sides of the channel stack. Also, the source / drain electrodes 150 contact and are connected to the second epitaxial layer 134, and the gate electrode 170 is on the channel stack 130. The channel stack 130 includes a first epitaxial layer 132, a second epitaxial layer 134 on the first epitaxial layer 132, and a third epitaxial layer 136 on the second epitaxial layer. The first epitaxial layer 132 and the second epitaxial layer 134 are composed of the same group-IV-IV compound material but have different concentrations. Similarly, the second epitaxial layer 134 and the third epitaxial layer 136 are composed of the same group-IV-IV compound material but have different concentrations. Therefore, the first epitaxial layer 132, the second epitaxial layer 134, and the third epitaxial layer 136 form a heterostructure. Since the first epitaxial layer 132, the second epitaxial layer 134, and the third epitaxial layer 136 are group-IV-IV compound materials, the spintronic device 100 can be applied to and be compatible with silicon-based devices, such as silicon-based FinFETs, silicon-based GAA FETs, and so on.

[0057] In some embodiments, the group-IV-IV compound material is a metal-containing binary compound material including a group-IV semiconductor element and a group-IV metal. For example, the first epitaxial layer 132 is composed of Ge 1-y Sn y The second epitaxial layer 134 is composed of Ge 1-x Sn x The third epitaxial layer 136 is composed of Ge 1-z Sn z and x is greater than y and z. In some embodiments, y is equal to z. That is, the percentage of Ge atoms in the second epitaxial layer 134 is lower than the percentage of Ge atoms in the first epitaxial layer 132 and is also lower than the percentage of Ge atoms in the third epitaxial layer 136. Therefore, the second epitaxial layer 134 is a strained layer. Such a configuration forms a quantum well (QW) in the second epitaxial layer 134, and a two-dimensional hole gas (2DHG) can be formed in the second epitaxial layer 134. In this way, the second epitaxial layer 134 can be referred to as the channel layer, the third epitaxial layer 136 can be referred to as the barrier layer or the upper buffer layer, and the first epitaxial layer 132 can be referred to as the lower buffer layer.

[0058] As described above, the first epitaxial layer 132, the second epitaxial layer 134, and the third epitaxial layer 136 may be in a metastable state. The percentage of Sn atoms (i.e., the percentage of metal atoms) in the metastable state can reach up to about 30%. That is, in some embodiments, 0 ≤ y < x ≤ 30% and 0 ≤ z < x ≤ 30%. Compared with the pure Ge layer, the Sn atoms in the channel stack 130 enhance the (Rashba) SOC therein, that is, the interaction between the spin of electrons and their orbital motion around the nucleus. Through a strong enough SOC, the gate electrode 170 can effectively control the spin of carriers (holes in this example) in the second epitaxial layer 134, and the magnetic material that provides a magnetic field to control the spin can be omitted. In this way, the size of the spintronic device 100 can be reduced. Also, the stronger the SOC, the faster the spin manipulation rate of the spintronic device 100, resulting in a faster data rate for the spin FET.

[0059] As described above, the third epitaxial layer 136 is composed of a Group-IV compound material, such that the third epitaxial layer 136 is substantially free of N-type or P-type dopants. For example, the atomic percentage of N-type and / or P-type dopants in the third epitaxial layer 136 is less than about 0.01%. In the absence of N-type or P-type dopants, the carrier concentration in the second epitaxial layer 134 can be tuned by the voltage (or bias voltage) of the gate electrode 170. More specifically, when a bias voltage is applied to the gate electrode 170, an electric field is formed in the channel stack 130. If the third epitaxial layer contains a sufficient amount of N-type and / or P-type dopants, these dopants will shield the electric field, and the second epitaxial layer 134 may be less sensitive to the bias voltage. However, since the third epitaxial layer 136 is composed of a Group-IV compound material and does not contain a sufficient amount of N-type and / or P-type dopants, the third epitaxial layer 136 does not shield the electric field. When the bias voltage of the gate electrode 170 changes, the carrier concentration of the second epitaxial layer 134 also changes (e.g., increases), and the higher the carrier concentration, the stronger the SOC effect.

[0060] Figure 5 Showing the simulated hole density in the GeSn layer plotted against the spin-orbit energy (Δ SO ) at different gate voltages according to some embodiments of the present disclosure. The data 910 show the hole density of the Ge 1-x1 Sn x1 channel layer at different gate voltages, the data 920 show the hole density of the Ge 1-x2 Sn x2 channel layer at different gate voltages, and the data 930 show the hole density of the Ge 1-x3 Sn x3 channel layer at different gate voltages, where x3 > x2 > x1. As Figure 5As shown, as the gate voltage changes, the hole density in the GeSn channel layer also changes accordingly. As the hole density increases, the spin--orbit energy Δ SO increases accordingly, and the SOC effect also increases accordingly.

[0061] In some embodiments, the SOC of the channel stack 130 can be tuned by adjusting the Sn concentration (or the atomic percentage of Sn, or [Sn]) and / or the stress difference (ε) between the first epitaxial layer 132, the second epitaxial layer 134, and the third epitaxial layer 136. Figure 6 Shows the simulated stress difference (ε) of different [Sn] in the channel layer and different [Sn] in the buffer layer according to some embodiments of the present disclosure. In Figure 4B and Figure 6 when x > y and / or x > z, the second epitaxial layer 134 and the first epitaxial layer 132 (and / or the third epitaxial layer 136) are negative, and the second epitaxial layer 134 has compressive strain to form 2DHG therein.

[0062] The [Sn] in the channel stack 130 can be determined in different ways. For example, in some embodiments, as shown by path M1 in Figure 6 the difference between the [Sn] of the second epitaxial layer 134 (channel layer) and the [Sn] of the first epitaxial layer 132 and the third epitaxial layer 136 (buffer layer) can be fixed. That is, the [Sn] in the first epitaxial layer 132 and the third epitaxial layer 136 (i.e., the y value and the z value) changes as the [Sn] in the second epitaxial layer 134 changes. With (x - y) and (x - z) being constant values, when the values of x, y, and z increase as shown by path M1, the SOC in the channel stack 130 also increases. In some embodiments, (x - y) and / or (x - z) are in the range of about 0% to about 30%. If (x - y) and / or (x - z) are higher than about 30%, the stress in the channel stack 130 may be too severe, thus damaging the channel stack 130; if (x - y) and / or (x - z) are lower than about 0%, the QW may not form in the second epitaxial layer 134. In other embodiments, as shown by path M2 in Figure 6 the [Sn] in the second epitaxial layer 134 is fixed, and the [Sn] in the first epitaxial layer 132 and the third epitaxial layer 136 increases, so that the stress (ε) decreases. In this scenario, the SOC of the channel stack 130 also increases.

[0063] As in Figure 4BAs shown, in some embodiments, the first epitaxial layer 132 has a thickness T1, the second epitaxial layer 134 has a thickness T2, and the third epitaxial layer 136 has a thickness T3. The thickness T2 of the second epitaxial layer 134 is in the range of about 2 nanometers to about 30 nanometers. If the thickness T2 is less than 2 nanometers, quantum wells may not form in the second epitaxial layer 134. If the thickness T2 is greater than about 30 nanometers, the stress in the second epitaxial layer 134 may damage the second epitaxial layer 134. In addition, the thickness T1 is greater than the thickness T2, and the thickness T3 is greater than the thickness T2. In this way, the stress of the second epitaxial layer 134 is dominated by the first epitaxial layer 132 and the third epitaxial layer 136.

[0064] In some embodiments, [Sn] in the first epitaxial layer 132 decreases along the depth direction D1. For example, [Sn] is approximately 0 at the bottom surface of the first epitaxial layer 132, and [Sn] is approximately y at the top surface of the first epitaxial layer 132. Therefore, the first epitaxial layer 132 can relieve the lattice mismatch between the second epitaxial layer 134 and the underlying buffer layer 120. In some embodiments, the thickness T1 is greater than the thickness T2 and the thickness T3 to provide a thickness sufficient to form a [Sn] gradient in the first epitaxial layer 132.

[0065] Figures 7A to 11B Illustrated are top views and cross-sectional views of several stages in the formation of a spintronic device 200 according to some embodiments of the present disclosure. In the multiple views and exemplary embodiments, the same reference numerals are used to label the same elements. It is to be understood that additional operations may be provided before, during, or after the processes shown, and some of the operations described below may be replaced or removed for alternative embodiments of this method. The order of the operations and processes may be interchanged. Figures 7A to 11B As shown, additional operations may be provided before, during, or after the processes shown, and some of the operations described below may be replaced or removed for alternative embodiments of this method. The order of the operations and processes may be interchanged.

[0066] Refer to Figure 7A and Figure 7B where Figure 7B is a cross-sectional view along the line A'-A' in Figure 7A . A substrate 210 is provided, and the substrate 210 is similar to or the same as the substrate 110 in Figure 1B . An underlying buffer layer 220 is formed on the substrate 210. The underlying buffer layer 220 is similar to or the same as the underlying buffer layer 120 in Figure 1B . Thereafter, a channel stack 230 is formed on the underlying buffer layer 220. The channel stack 230 includes a first epitaxial layer 232 on the underlying buffer layer, a second epitaxial layer 234 on the first epitaxial layer 232, and a third epitaxial layer 236 on the second epitaxial layer 234. The first epitaxial layer 232 is similar to or the same as the first epitaxial layer 132 in Figure 1B , the second epitaxial layer 234 is similar to or the same as the second epitaxial layer 134 in Figure 1B , and the third epitaxial layer 236 is similar to or the same asFigure 1B the third epitaxial layer 136 therein.

[0067] In some embodiments, an etching process is performed on the channel stack 230 to form alignment marks AM'. For example, a patterned mask layer is formed on the channel stack 230, and an etching process is performed using the patterned mask layer as an etching mask to form alignment marks AM' in the channel stack 230. In Figure 7A and Figure 7B the alignment marks AM' are trenches, openings, recesses, or other suitable structures.

[0068] Referring to Figure 8A and Figure 8B where Figure 8B is a cross-sectional view along the C-C line segment of Figure 8A . A plurality of openings O2 are formed in the channel stack 230. For example, another patterned mask layer is formed on the channel stack 230, and an etching process is performed using the patterned mask layer as an etching mask to form the openings O2. In some embodiments, the openings O2 extend through the third epitaxial layer 236 but do not extend through the second epitaxial layer 234. However, in some embodiments, the openings O2 may also extend through the second epitaxial layer 234 (and the first epitaxial layer 232).

[0069] Next, a plurality of source / drain electrodes 252, 254, 256, and 258 are respectively formed in the openings O2. For example, a conductive material is filled in the openings O2, and then a CMP process or a back-etching process is performed to remove the portion of the conductive material outside the openings O2, such that the source / drain electrodes 252, 254, 256, and 258 are embedded in the channel stack 230. In some embodiments, the conductive material is composed of W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, TiAl, HfTi, TiSi, TaSi, TiAlC, combinations of the above, or other similar materials. The conductive material can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0070] Referring to Figure 9A and Figure 9B where Figure 9B is a cross-sectional view along the D-D line segment of Figure 9A . A first gate dielectric layer 260 is deposited on the channel stack 230 and the source / drain electrodes 252, 254, 256, and 258. For clarity, the first gate dielectric layer 260 is not shown in Figure 9A , and the elements covered by the first gate dielectric layer 260 are shown in Figure 9A . The first gate dielectric layer 260 is similar to or the same as Figure 4BThe gate dielectric layer 160 therein. Then, the confinement gates 312, 314, and 316 are formed on the first gate dielectric layer 260. For example, a conductive layer is deposited on the first gate dielectric layer 260 and then patterned to form the confinement gates 312, 314, and 316. The conductive layer (and thus the confinement gates 312, 314, and 316) is composed of W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, TiAl, HfTi, TiSi, TaSi, TiAlC, combinations of the above, or other similar materials. The conductive layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0071] In some embodiments, each of the confinement gates 312, 314, and 316 has a bar shape, rectangular shape, strip shape, or other suitable shape in a top view (see Figure 9A ). The confinement gates 312, 314, and 316 are configured to confine the current path in the channel stack 230. Specifically, the confinement gates 312, 314, and 316 prevent carriers (such as electrons and / or holes) from flowing through the region directly below the confinement gates 312, 314, and 316. Thus, the confinement gates 312, 314, and 316 define the channel regions CH1 and CH2 of the spintronic device 200. As Figure 9A shown, a pair of source / drain electrodes 252 and 254 are located between the proximities of the two confinement gates 312 and 314, and the confinement gates 312 and 314 define the channel region CH1 between the confinement gates 312 and 314 and between the source / drain electrodes 252 and 254. In this way, current can flow from one of the source / drain electrodes 252 and 254, through the channel region CH1, to the other of the source / drain electrodes 252 and 254. Similarly, a pair of source / drain electrodes 256 and 258 are located between the proximities of the two confinement gates 314 and 316, and the confinement gates 314 and 316 define the channel region CH2 between the confinement gates 314 and 316 and between the source / drain electrodes 256 and 258. In this way, current can flow from one of the source / drain electrodes 256 and 258, through the channel region CH2, to the other of the source / drain electrodes 256 and 258.

[0072] Referring to Figure 10A and Figure 10B , where Figure 10B is a cross-sectional view along the C-C line segment of Figure 10A . The second gate dielectric layer 280 is deposited on the first gate dielectric layer 260 and the confinement gates 312, 314, and 316. For clarity, the second gate dielectric layer 280 is not shown in Figure 10A , and the components covered by the second gate dielectric layer 280 are shown inFigure 10A In. The second gate dielectric layer 280 is similar to or the same as Figure 9B the first gate dielectric layer 260 in. Then, an extended gate 322, 324, 326, and 328 and an accumulation gate 332, 334, 336, and 338 are formed on the second gate dielectric layer 280. For example, another conductive layer is deposited on the second gate dielectric layer 280 and patterned to form the extended gate 322, 324, 326, and 328 and the accumulation gate 332, 334, 336, and 338. The conductive layer (and thus the extended gate 322, 324, 326, and 328 and the accumulation gate 332, 334, 336, and 338) is composed of W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, TiAl, HfTi, TiSi, TaSi, TiAlC, a combination of the above, or other similar materials. The conductive layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0073] As Figure 10A shown, the accumulation gates 332 and 334 are formed above and across the channel regions CH1 and the confinement gates 312 and 314, and the accumulation gates 336 and 338 are formed above and across the channel regions CH2 and the confinement gates 314 and 316. The extended gate 322 is located between the accumulation gate 332 and the source / drain electrode 252 in a top view, the extended gate 324 is located between the accumulation gate 334 and the source / drain electrode 254 in a top view, the extended gate 326 is located between the accumulation gate 336 and the source / drain electrode 256 in a top view, and the extended gate 328 is located between the accumulation gate 338 and the source / drain electrode 258 in a top view. Carriers (holes in this example) can be stored in the channel regions CH1 and CH2 and respectively under the accumulation gates 332, 334, 336, and 338, and each carrier stored under the accumulation gates 332, 334, 336, and 338 is a qubit.

[0074] Referring to Figure 11A and Figure 11B , where Figure 11B is a cross-sectional view along the Figure 11A C-C line segment of. A third gate dielectric layer 290 is deposited on the second gate dielectric layer 280, the extended gate 322, 324, 326, and 328, and the accumulation gate 332, 334, 336, and 338. For clarity, the third gate dielectric layer 290 is not shown in Figure 11A and the elements covered by the third gate dielectric layer 290 are shown in Figure 11AIn. The third gate dielectric layer 290 is similar to or the same as Figure 9B the first gate dielectric layer 260 in. Then, bridging gates 341, 342, 343, 346, 347, and 348 are formed on the third gate dielectric layer 290. For example, another conductive layer is deposited on the third gate dielectric layer 290 and patterned to form the bridging gates 341, 342, 343, 346, 347, and 348. The conductive layer (and thus the bridging gates 341, 342, 343, 346, 347, and 348) is composed of W, Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, Co, TaC, TiAl, HfTi, TiSi, TaSi, TiAlC, a combination of the above, or other similar materials. The conductive layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0075] The bridging gate 341 is located between the extended gate 322 and the accumulation gate 332, the bridging gate 342 is located between the accumulation gates 332 and 334, the bridging gate 343 is located between the accumulation gates 334 and the extended gate 324, the bridging gate 346 is located between the extended gate 326 and the accumulation gate 336, the bridging gate 347 is located between the accumulation gates 336 and 338, and the bridging gate 348 is located between the accumulation gate 338 and the extended gate 328. When a bias voltage is applied to the bridging gates 341 and 342 and the extended gate 322, a single carrier can flow from the source / drain electrode 252 to the channel region CH1 directly below the accumulation gate 334; when a bias voltage is applied to the bridging gate 341 and the extended gate 322, a single carrier can flow from the source / drain electrode 252 to the channel region CH1 directly below the accumulation gate 332; when a bias voltage is applied to the bridging gate 343 and the extended gate 324, the qubit stored directly below the accumulation gate 334 can flow to the source / drain electrode 254; when a bias voltage is applied to the bridging gates 342 and 343 and the extended gate 324, the qubit stored directly below the accumulation gate 332 can flow to the source / drain electrode 254. Similarly, when a bias voltage is applied to the bridging gates 346 and 347 and the extended gate 326, a single carrier can flow from the source / drain electrode 256 to the channel region CH2 directly below the accumulation gate 338; when a bias voltage is applied to the bridging gate 346 and the extended gate 326, a single carrier can flow from the source / drain electrode 256 to the channel region CH2 directly below the accumulation gate 336; when a bias voltage is applied to the bridging gate 348 and the extended gate 328, the qubit stored directly below the accumulation gate 338 can flow to the source / drain electrode 258; when a bias voltage is applied to the bridging gates 347 and 348 and the extended gate 328, the qubit stored directly below the accumulation gate 336 can flow to the source / drain electrode 258.

[0076] As Figure 11A and Figure 11B shown in, the spintronic device 200 is a spin qubit device and includes a channel stack 230, source / drain electrodes 252, 254, 256, and 258, extension gates 322, 324, 326, and 328, accumulation gates 332, 334, 336, and 338, and bridging gates 341, 342, 343, 346, 347, and 348. By controlling the bias voltages of the accumulation gates 332, 334, 336, and 338, the spin directions of the corresponding qubits can be controlled. Additionally, as described above, by controlling the values of [Sn] and / or (x - y) and (x - z), the SOC of the channel stack 230 can be enhanced, thereby improving the qubit fidelity of the spintronic device 200.

[0077] Based on the above discussion, it can be recognized that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be disclosed herein, and not all embodiments require specific advantages. One advantage is that the channel stack of the spintronic device has strong SOC, resulting in higher qubit fidelity and thus faster data rates. In addition, since the channel stack is composed of group IV-IV compound materials, the spintronic device can be compatible with silicon-based devices. Further, the spin direction of the spintronic device is controlled by gates, enabling the size of the spintronic device to be reduced.

[0078] According to some embodiments, a method includes epitaxially growing Ge 1-x Sn x channel layer on a substrate. The Ge 1-x Sn x channel layer is in a metastable state. Epitaxially grow Ge 1-x Sn x barrier layer on the Ge 1-y Sn y channel layer to form a two-dimensional hole gas in the Ge 1-x Sn x channel layer. Etch the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer to form a first opening and a second opening in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. Deposit a first source / drain electrode and a second source / drain electrode in the first opening and the second opening, respectively. Form a first gate electrode on the Ge 1-y Sn y barrier layer.

[0079] In some embodiments, x > y. In some embodiments, 0 < x < 30%. In some embodiments, Ge 1- y Sn y The barrier layer is in a metastable state. In some embodiments, a method further includes forming a second gate electrode on the Ge 1-y Sn y barrier layer, wherein the second gate electrode is located between the first gate electrode and the first source / drain electrode. In some embodiments, a method further includes epitaxially growing Ge 1-z Sn z a buffer layer on a substrate, and epitaxially growing the Ge 1-z Sn z channel layer and contacting the Ge 1-z Sn z buffer layer, wherein x > z. In some embodiments, the percentage of tin atoms in the Ge 1-z Sn z buffer layer decreases along the depth direction.

[0080] According to some embodiments, a method includes receiving a substrate. Performing a first epitaxial process to form a channel layer on the substrate. The channel layer includes tin and germanium and has a first tin atom percentage. Based on the first tin atom percentage of the channel layer, a second tin atom percentage in the barrier layer is determined to increase the spin-orbit coupling effect of the channel layer. Performing a second epitaxial process to form a barrier layer having the second tin atom percentage on the channel layer, and the barrier layer contacts the channel layer. Forming a first source / drain electrode and a second source / drain electrode in the channel layer and the barrier layer. Forming a gate electrode between the first source / drain electrode and the second source / drain electrode to cover the barrier layer.

[0081] In some embodiments, the barrier layer is substantially free of N-type dopants and P-type dopants. In some embodiments, the second tin atom percentage of the barrier layer is higher than the first tin atom percentage of the channel layer. In some embodiments, the barrier layer further includes germanium. In some embodiments, the percentage of germanium atoms in the channel layer is lower than the percentage of germanium atoms in the barrier layer. In some embodiments, before performing the first epitaxial process, a third epitaxial process is performed to form a buffer layer on the substrate. In some embodiments, the buffer layer includes tin and germanium.

[0082] According to some embodiments, a method includes epitaxially growing a channel stack on a substrate. The channel stack is a heterostructure and includes a channel layer and a barrier layer, where the channel layer includes a first metal-containing binary compound material, and the barrier layer contacts the channel layer and includes a second binary compound material, and the percentage of metal atoms in the first metal-containing binary compound material is higher than the percentage of metal atoms in the second metal-containing binary compound material. The method further includes forming a plurality of source / drain electrodes on the substrate that contact the channel layer. A gate dielectric layer is deposited to cover the channel stack. A gate electrode is formed on the gate dielectric layer and the channel stack.

[0083] In some embodiments, the percentage of metal atoms in the first metal-containing binary compound material is not higher than about 30%. In some embodiments, the percentage of metal atoms in the second metal-containing binary compound material is not higher than about 30%. In some embodiments, the channel layer is in a metastable state. In some embodiments, the channel stack includes a buffer layer, and the buffer layer is located under the channel layer and includes a third metal-containing binary compound material, and the percentage of metal atoms in the first metal-containing binary compound material is higher than the percentage of metal atoms in the third metal-containing binary compound material. In some embodiments, the first metal-containing binary compound material is GeSn.

[0084] According to some embodiments, a spintronic device includes a substrate, Ge 1-x Sn x channel layer, Ge 1-y Sn y barrier layer, a first opening, a second opening, a first source / drain electrode, a second source / drain electrode, and a first gate electrode. The Ge 1-x Sn x channel layer is located on the substrate, where the Ge 1-x Sn x channel layer is in a metastable state. The Ge 1-y Sn y barrier layer is located on the Ge 1- x Sn x channel layer such that a two-dimensional hole gas is formed in the Ge 1-x Sn x channel layer. The first opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The second opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on the Ge1-y Sn y on the barrier layer.

[0085] In some embodiments, x > y. In some embodiments, 0 < x < 30%. In some embodiments, Ge 1- y Sn y The barrier layer is in a metastable state. In some embodiments, the spintronic device further includes Ge located on a substrate 1-z Sn z buffer layer. In some embodiments, Ge 1-x Sn x The channel layer is in contact with the Ge 1-z Sn z buffer layer, and x > z.

[0086] According to some embodiments, a spintronic device, characterized in that it includes a substrate, Ge 1-x Sn x channel layer, Ge 1-y Sn y barrier layer, a first opening, a second opening, a first source / drain electrode, a second source / drain electrode, and a first gate electrode. Ge 1-x Sn x The channel layer is located on the substrate. Ge 1-y Sn y The barrier layer is located on the Ge 1-x Sn x channel layer, such that a two-dimensional hole gas is formed in the Ge 1-x Sn x channel layer, where Ge 1-y Sn y The barrier layer is in a metastable state. The first opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The second opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on the Ge 1-y Sn y barrier layer.

[0087] In some embodiments, the spintronic device further includes a second gate electrode located on the Ge 1-y Sn y barrier layer, where the second gate electrode is located between the first gate electrode and the first source / drain electrode.

[0088] According to some embodiments of the present disclosure, a spintronic device, characterized in that it comprises a substrate, Ge 1-x Sn x channel layer, Ge 1-y Sn y barrier layer, Ge 1-z Sn z buffer layer, a first opening, a second opening, a first source / drain electrode, a second source / drain electrode, and a first gate electrode. Ge 1-x Sn x The channel layer is located on the substrate, wherein Ge 1-x Sn x The channel layer is in a metastable state. Ge 1- y Sn y The barrier layer is located on the Ge 1-x Sn x channel layer, such that Ge 1-x Sn x a two-dimensional hole gas is formed in the channel layer. Ge 1-z Sn z The buffer layer is located on the substrate, wherein Ge 1-x Sn x the channel layer is in contact with the Ge 1-z Sn z buffer layer. The first opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The second opening is located in the Ge 1-x Sn x channel layer and the Ge 1-y Sn y barrier layer. The first source / drain electrode is located in the first opening. The second source / drain electrode is located in the second opening. The first gate electrode is located on the Ge 1-y Sn y barrier layer.

[0089] In some embodiments, the percentage of tin atoms in the Ge 1-z Sn z buffer layer decreases along the depth direction.

[0090] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same purposes and / or obtaining the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A spintronic device, characterized in that: Include: a substrate; one 1-x Sn x The channel layer is located on the substrate, wherein the Ge 1-x Sn x The channel layer is in a metastable state; one 1-y Sn y The barrier layer is located at the Ge 1-x Sn x channel layer, so that the Ge 1-x Sn x A one- and two-dimensional hole gas is formed in the channel layer; A first opening is located at the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; A second opening, the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; a first source / drain electrode located in the first opening; a second source / drain electrode located in the second opening; and A first gate electrode is located on the Ge 1-y Sn y On the barrier layer.

2. The spintronic device according to claim 1, wherein: Where x>y.

3. The spintronic device according to claim 1, wherein: Where 0 <x≤30%。 4. The spintronic device according to claim 1, wherein: The Ge 1-y Sn y The barrier layer is in a metastable state.

5. The spintronic device according to claim 1, wherein: Also includes: one 1-z Sn z The buffer layer is located on the substrate.

6. The spintronic device according to claim 5, wherein: Among them, 1-x Sn x The channel layer and the Ge 1-z Sn z The buffer layers are in contact and x>z.

7. A spintronic device, characterized in that: Include: a substrate; one 1-x Sn x a channel layer, located on the substrate; one 1-y Sn y The barrier layer is located at the Ge 1-x Sn x channel layer, so that the Ge 1-x Sn x A two-dimensional hole gas is formed in the channel layer, where the Ge 1-y Sn y The barrier layer is in a metastable state; A first opening is located at the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; A second opening, the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; a first source / drain electrode located in the first opening; a second source / drain electrode located in the second opening; and A first gate electrode is located on the Ge 1-y Sn y On the barrier layer.

8. The spintronic device according to claim 7, wherein: Also includes: A second gate electrode is located on the Ge 1-y Sn y The second gate electrode is located on the barrier layer, wherein the second gate electrode is located between the first gate electrode and the first source / drain electrode.

9. A spintronic device, characterized in that: Include: a substrate; one 1-x Sn x a channel layer, located on the substrate; one 1-y Sn y The barrier layer is located at the Ge 1-x Sn x channel layer, so that the Ge 1-x Sn x A one- and two-dimensional hole gas is formed in the channel layer; one 1-z Sn z The buffer layer is located on the substrate, wherein the Ge 1-x Sn x The channel layer and the Ge 1-z Sn z Buffer layer contact; A first opening is located at the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; A second opening, the Ge 1-x Sn x Channel layer and the Ge 1-y Sn y In the barrier layer; a first source / drain electrode located in the first opening; a second source / drain electrode located in the second opening; and A first gate electrode is located on the Ge 1-y Sn y On the barrier layer.

10. The spintronic device according to claim 9, wherein: The Ge 1-z Sn z A tin atomic percentage of the buffer layer decreases along a depth direction.

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