Electrostatic protection device and terminal equipment

Abstract

The utility model discloses an electrostatic protection device and terminal equipment, and relates to the technical field of semiconductor devices. The electrostatic protection device comprises a substrate, a plurality of buried layers, an epitaxial layer, a plurality of first doped regions, a plurality of second doped regions, a short-circuit doped region, a plurality of groove isolation regions, a first electrode, a second electrode and a third electrode, wherein the first doped regions and the second doped regions are positioned in the epitaxial layer; the short-circuit doped region is positioned in the epitaxial layer; the plurality of functional areas comprise a first functional area, a second functional area and a third functional area; the first electrode is located on the epitaxial layer and connected with the short-circuit doped region, the second electrode is located on the epitaxial layer and connected with the second doped region of the second functional region, the first doped region of the third functional region and one first doped region, close to the second doped region, of the first doped regions, and the third electrode is located on the side, away from the epitaxial layer, of the substrate. The electrostatic protection device can realize the flyback characteristic through the short-circuit design, reduces the clamping voltage, and prevents the rear-end IC from losing efficacy due to the influence of static electricity or surge current.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, and more specifically, to an electrostatic protection device and a terminal device. Background Art

[0002] As the process size of semiconductor devices continues to shrink and the application environment of circuits becomes increasingly complex, the frequency and impact of integrated circuits facing electrostatic discharge (ESD) are increasing. At the interface end of consumer electronics applications, such as DVI (Digital Visual Interface), VGA (Video Graphics Array Interface), USB (Universal Serial Bus), HDMI (High Definition Multimedia Interface), etc., are often subject to ESD impacts. With the continuous improvement of the requirements for data transmission speed and information transmission integrity, the requirements for ESD protection devices are also getting higher and higher.

[0003] Figure 1 It is a four-channel low-capacitance ESD array structure. This device achieves the purpose of reducing capacitance by connecting the derating diodes D1 and Dz in series. The overall capacitance of this device is determined by the derating diode D1 and the derating diode D2. Figure 2 It is the cross-sectional structure of the four-channel low-capacitance ESD array structure (only two of the I / Os are shown). A surge discharge channel is formed between the I / O and GND through the P+ implantation region, N-epi epitaxial layer, NBL buried layer to the P-SUB substrate; a surge discharge channel is formed between different I / Os through P+, N-epi, NBL, P-SUB to the middle of the N-epi and N+ implantation regions; a surge discharge channel is formed between Vcc and GND through N+, N-epi, NBL to the middle of the substrate. However, in the currently commonly used four-channel low-capacitance ESD structure, when a positive surge is applied to Vcc, through N+, N-epi, NBL to P-SUB, although an inverse breakdown diode will be formed between NBL and P-SUB, due to passing through the N-epi high-resistance region, it will cause a relatively large dynamic resistance after the device is in the breakdown state, and further cause a relatively large clamping voltage, and finally it is easy to cause the IC to burn out during the subsequent protection process. Summary of the Utility Model

[0004] The purpose of the utility model is to provide an electrostatic protection device and a terminal device. The electrostatic protection device and the terminal device can achieve a flyback characteristic through a short-circuit design, reduce the clamping voltage, so as to avoid the failure of the backend IC affected by electrostatic or surge current.

[0005] The embodiments of the present utility model are implemented as follows:

[0006] On one hand, the present utility model provides an electrostatic protection device, which includes a substrate, a plurality of buried layers located on part of the substrate, an epitaxial layer located on the buried layers and the exposed substrate, a plurality of first doping regions and a plurality of second doping regions located in the epitaxial layer, a short-circuit doping region located in the epitaxial layer, a plurality of trench isolation regions for isolating a plurality of functional regions on the epitaxial layer, a first electrode, a second electrode and a third electrode; the plurality of functional regions include a first functional region, a second functional region and a third functional region, and the second functional region is located between the first functional region and the third functional region; two first doping regions and a short-circuit doping region located between the two first doping regions are provided in the first functional region, a second doping region is provided in the second functional region, and a first doping region is provided in the third functional region; the first electrode is located on the epitaxial layer and is connected to the short-circuit doping region, the second electrode is located on the epitaxial layer, and the second electrode is connected to the second doping region of the second functional region, the first doping region of the third functional region, and one of the first doping regions close to the second doping region, and the third electrode is located on the side of the substrate facing away from the epitaxial layer; the substrate and the first doping region adopt a first doping type, and the buried layer, the epitaxial layer and the second doping region adopt a second doping type. The electrostatic protection device can achieve a flyback characteristic and reduce the clamping voltage through a short-circuit design, so as to avoid the failure of the backend IC due to the influence of static electricity or surge current.

[0007] Optionally, the short-circuit doping region includes a third doping region and two fourth doping regions, and the two fourth doping regions are respectively connected to opposite sides of the third doping region; the doping type of the third doping region is the same as that of the substrate.

[0008] Optionally, the doping concentrations of the first doping region, the second doping region and the substrate are respectively greater than the doping concentration of the epitaxial layer.

[0009] Optionally, the ion implantation doses of the first doping region and the second doping region are respectively between 1×10 15 / cm 2 and 5×10 16 / cm 2 ; and / or, the ion implantation energies of the first doping region and the second doping region are respectively between 30 KeV and 120 KeV.

[0010] Optionally, the ion implantation dose of the buried layer is between 1×10 14 / cm 2 and 1×10 16 / cm 2 ; and / or, the ion implantation energy of the buried layer is between 20 KeV and 120 KeV.

[0011] Optionally, the trench depth of the trench isolation region is greater than the depletion layer width of the diode formed by the epitaxial layer and the substrate at reverse breakdown.

[0012] Optionally, the trench isolation region is made of undoped polysilicon or tetraethyl orthosilicate.

[0013] Optionally, the resistivity of the substrate is between 0.01 Ω·cm and 0.001 Ω·cm; and / or, the resistivity of the epitaxial layer is between 50 Ω·cm and 1000 Ω·cm; and / or, the thickness of the epitaxial layer is between 8 μm and 20 μm.

[0014] Optionally, the first doping type is P-type and the second doping type is N-type; or, the first doping type is N-type and the second doping type is P-type.

[0015] In another aspect of the present invention, a terminal device is provided. The terminal device includes the above-mentioned electrostatic protection device. The first electrode of the electrostatic protection device is used as the power port of the terminal device, the second electrode of the electrostatic protection device is used as the input port of the terminal device, and the third electrode of the electrostatic protection device is used as the ground port of the terminal device.

[0016] The beneficial effects of the present invention include:

[0017] In this application, a short-circuit doping region is arranged in the first functional region. In this way, a part of the short-circuit doping region can form a triode with an open base region with the epitaxial layer, the buried layer and the substrate; another part of the short-circuit doping region can form a diode with the epitaxial layer, the buried layer and the substrate. The parallel connection of the two can be realized through the first electrode above the short-circuit doping region. At this time, when a positive surge or static electricity is applied to the first electrode, the triode with an open base region works, and the flyback characteristic can be realized; when a negative surge or static electricity is applied to the first electrode, the diode can work. Through the above settings, this application can enable the electrostatic protection device to achieve the flyback characteristic and reduce the clamping voltage, so as to avoid the failure of the backend IC due to the influence of static electricity or surge current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of a four-channel low-capacitance ESD array structure in the background technology;

[0020] Figure 2is a four-channel low-capacitance ESD profile structure in the background art;

[0021] Figure 3 is a schematic structural diagram of an electrostatic protection device provided by some embodiments of the present application;

[0022] Figure 4 is one of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0023] Figure 5 is the second of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0024] Figure 6 is the third of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0025] Figure 7 is the fourth of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0026] Figure 8 is the fifth of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0027] Figure 9 is the sixth of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0028] Figure 10 is the seventh of the schematic diagrams of the preparation process of an electrostatic protection device provided by some embodiments of the present application;

[0029] Figure 11 is one of the equivalent circuit diagrams of an electrostatic protection device provided by some embodiments of the present application;

[0030] Figure 12 is the second of the equivalent circuit diagrams of an electrostatic protection device provided by some embodiments of the present application.

[0031] Icon: 10 - Substrate; 20 - Buried layer; 30 - Epitaxial layer; 41 - First doped region; 42 - Second doped region; 43 - Short-circuit doped region; 431 - Third doped region; 432 - Fourth doped region; 50 - Trench isolation region; 61 - First electrode; 62 - Second electrode; 63 - Third electrode; 70 - Passivation layer; A - First functional region; B - Second functional region; C - Third functional region. Detailed implementation manners

[0032] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concept of the present utility model and will recognize the applications of these concepts that are not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present utility model and the appended claims.

[0033] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present utility model, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extend onto another element, or there may also be intervening elements. In contrast, when an element is referred to as "directly on another element" or "directly extending onto another element", there are no intervening elements. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element", it can be directly above another element or directly extend above another element, or there may also be intervening elements. In contrast, when an element is referred to as "directly above another element" or "directly extending above another element", there are no intervening elements. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0035] Relative terms such as "below", "above", "upper", "lower", "horizontal", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It should be understood that these terms and those discussed above are intended to cover different orientations of the device other than the orientations depicted in the figures.

[0036] The terms used in this document are for the purpose of describing specific embodiments only and are not intended to limit the present utility model. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. It should also be understood that when used herein, the term "comprising" specifies the presence of the stated features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups of the above items.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. It should also be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0038] Please refer to Figure 3 , this embodiment provides an electrostatic protection device, which includes a substrate 10, a plurality of buried layers 20 located on a part of the substrate 10, an epitaxial layer 30 located on the buried layers 20 and the exposed substrate 10, a plurality of first doped regions 41 and a plurality of second doped regions 42 located in the epitaxial layer 30, a short-circuit doped region 43 located in the epitaxial layer 30, a plurality of trench isolation regions 50 for isolating a plurality of functional regions on the epitaxial layer 30, a first electrode 61, a second electrode 62 and a third electrode 63; the plurality of functional regions include a first functional region A, a second functional region B and a third functional region C, and the second functional region B is located between the first functional region A and the third functional region C; two first doped regions 41 and a short-circuit doped region 43 located between the two first doped regions 41 are provided in the first functional region A, a second doped region 42 is provided in the second functional region B, and a first doped region 41 is provided in the third functional region C; the first electrode 61 is located on the epitaxial layer 30 and is connected to the short-circuit doped region 43, the second electrode 62 is located on the epitaxial layer 30, and the second electrode 62 is connected to the second doped region 42 of the second functional region B, the first doped region 41 of the third functional region C, and a first doped region 41 of the first doped regions 41 close to the second doped region 42, and the third electrode 63 is located on the side of the substrate 10 facing away from the epitaxial layer 30; the substrate 10 and the first doped regions 41 adopt a first doping type, and the buried layers 20, the epitaxial layer 30 and the second doped regions 42 adopt a second doping type. This electrostatic protection device can achieve a flyback characteristic and reduce the clamping voltage through a short-circuit design, so as to avoid the failure of the backend IC due to the influence of electrostatic or surge current.

[0039] Among them, the above-mentioned buried layers 20 are located on the substrate 10, and the buried layers 20 include a plurality of them. Please refer to Figure 3As shown, in this embodiment, the doping type of the buried layer 20 is different from that of the substrate 10.

[0040] The epitaxial layer 30 is located on the buried layer 20, and the epitaxial layer 30 covers the buried layer 20 and the exposed substrate 10. The doping type of the epitaxial layer 30 is the same as that of the buried layer 20.

[0041] The above-mentioned multiple first doping regions 41, multiple second doping regions 42, and short-circuit doping region 43 are all formed within the epitaxial layer 30 and above the epitaxial layer 30, that is, the upper end surfaces of the multiple first doping regions 41, multiple second doping regions 42, and short-circuit doping region 43 are flush with the upper end surface of the epitaxial layer 30, as Figure 3 shown.

[0042] Multiple trench isolation regions 50 are further provided within the epitaxial layer 30. Among them, the multiple trench isolation regions 50 can isolate multiple functional regions on the epitaxial layer 30. The multiple functional regions include a first functional region A, a second functional region B, and a third functional region C. It should be noted that the specific number of the multiple functional regions is not limited in this application. For example, when multiple input / output ports I / O are required, correspondingly, multiple second functional regions B and third functional regions C are needed. This application Figure 3 illustrates with two input / output ports I / O as an example, and it is not a specific limitation on the number of input / output ports I / O.

[0043] In this embodiment, the second functional region B is located between the first functional region A and the third functional region C. Two first doping regions 41 and a short-circuit doping region 43 located between the two first doping regions 41 are provided within the first functional region A. A second doping region 42 is provided within the second functional region B, and a first doping region 41 is provided within the third functional region C, as Figure 3 shown.

[0044] Among them, the doping types of the above-mentioned first doping region 41 and second doping region 42 are different, and the doping type of the first doping region 41 is the same as that of the substrate 10, and the doping type of the second doping region 42 is the same as that of the epitaxial layer 30. That is to say, the substrate 10 and the first doping region 41 adopt the first doping type, and the buried layer 20, the epitaxial layer 30, and the second doping region 42 adopt the second doping type. For example, the first doping type is P-type, and the second doping type is N-type; or the first doping type is N-type, and the second doping type is P-type.

[0045] The first electrode 61 and the second electrode 62 are both located on the side of the epitaxial layer 30 away from the substrate 10, and the third electrode 63 is located on the side of the substrate 10 away from the epitaxial layer 30. In this embodiment, the first electrode 61 is located on the first functional region A and is connected to the short-circuit doping region 43. The second electrode 62 is located on the first functional region A, the second functional region B, and the third functional region C, and the second electrode 62 is respectively connected to the first doping region 41 near the second functional region B in the first functional region A, the second doping region 42 of the second functional region B, and the first doping region 41 of the third functional region C, as Figure 3 shown.

[0046] It should be noted that the second electrode 62 is used to connect the input port I / O. For example, if two parallel circuits are required, the second electrode 62 includes two, and the two second electrodes 62 are respectively used to connect the input ports I / O of the two circuits; if four parallel circuits are required, the second electrode 62 includes four, and the four second electrodes 62 are respectively used to connect the input ports I / O of the four circuits.

[0047] The above-mentioned first electrode 61 is used to connect the power supply port VCC, and the third electrode 63 is used to connect the ground port GND.

[0048] In this embodiment, the substrate 10 is heavily doped, and the epitaxial layer 30 is lightly doped. The first doping region 41, the second doping region 42, and the short-circuit doping region 43 are all heavily doped.

[0049] It should be noted that the short-circuit doping region 43 includes a first part and a second part that are short-circuited, and the doping types of the first part and the second part are different. Assuming that the first part is of the first doping type and the second part is of the second doping type, at this time, a triode with an open base region and a diode can be formed in parallel to form a forward surge and electrostatic discharge channel, as Figure 11 and Figure 12 . Among them, the first part of the short-circuit doping region 43 in the first functional region A, the epitaxial layer 30, the buried layer 20, and the substrate 10 form a triode with an open base region; the second part of the short-circuit doping region 43, the epitaxial layer 30, the buried layer 20, and the substrate 10 form a diode. The parallel connection of the two (i.e., the triode and the diode) can be realized through the first electrode 61 above the short-circuit doping region 43, as Figure 12 shown. When a forward surge or static electricity is applied to the first electrode 61, the triode with an open base region functions, and the flyback characteristic can be realized; when a negative surge or static electricity is applied to the first electrode 61, the diode functions.

[0050] In summary, the electrostatic protection device provided by the present application includes a substrate 10, a plurality of buried layers 20 located on a part of the substrate 10, an epitaxial layer 30 located on the buried layers 20 and the exposed substrate 10, a plurality of first doping regions 41 and a plurality of second doping regions 42 located in the epitaxial layer 30, a short-circuit doping region 43 located in the epitaxial layer 30, a plurality of trench isolation regions 50 for isolating a plurality of functional regions on the epitaxial layer 30, a first electrode 61, a second electrode 62, and a third electrode 63; the plurality of functional regions include a first functional region A, a second functional region B, and a third functional region C, and the second functional region B is located between the first functional region A and the third functional region C; two first doping regions 41 and a short-circuit doping region 43 located between the two first doping regions 41 are provided in the first functional region A, a second doping region 42 is provided in the second functional region B, and a first doping region 41 is provided in the third functional region C; the first electrode 61 is located on the epitaxial layer 30 and is connected to the short-circuit doping region 43, the second electrode 62 is located on the epitaxial layer 30, and the second electrode 62 is connected to the second doping region 42 of the second functional region B, the first doping region 41 of the third functional region C, and a first doping region 41 close to the second doping region 42 among the first doping regions 41, and the third electrode 63 is located on the side of the substrate 10 away from the epitaxial layer 30; the substrate 10 and the first doping region 41 adopt a first doping type, and the buried layer 20, the epitaxial layer 30, and the second doping region 42 adopt a second doping type. By providing the short-circuit doping region 43 in the first functional region A in the present application, thus, a part of the short-circuit doping region 43 can form a triode with an open base region with the epitaxial layer 30, the buried layer 20, and the substrate 10; another part of the short-circuit doping region 43 can form a diode with the epitaxial layer 30, the buried layer 20, and the substrate 10. The parallel connection of the two can be achieved through the first electrode 61 above the short-circuit doping region 43. At this time, when a positive surge or static electricity is applied to the first electrode 61, the triode with an open base region functions, and the flyback characteristic can be achieved; when a negative surge or static electricity is applied to the first electrode 61, the diode can function. Through the above settings, the present application can enable the electrostatic protection device to achieve the flyback characteristic and reduce the clamping voltage, so as to avoid the failure of the backend IC due to the influence of static electricity or surge current.

[0051] In a feasible implementation, the short-circuit doping region 43 includes a third doping region 431 and two fourth doping regions 432. The two fourth doping regions 432 are respectively connected to opposite sides of the third doping region 431; the doping type of the third doping region 431 is the same as that of the substrate 10. By providing the short-circuit doping region 43 within the first functional region A, a triode with an open base and a diode can be formed in parallel to form a forward surge and electrostatic discharge channel. Among them, the third doping region 431, the epitaxial layer 30, the buried layer 20, and the substrate 10 within the short-circuit doping region 43 in the first functional region A form a triode with an open base; the fourth doping region 432, the epitaxial layer 30, the buried layer 20, and the substrate 10 in the short-circuit doping region 43 form a diode. The parallel connection of the two can be achieved through the first electrode 61 above the short-circuit doping region 43, as Figure 12 shown. When a forward surge or static electricity is applied to the first electrode 61, the triode with an open base comes into play, and the flyback characteristic can be achieved; when a negative surge or static electricity is applied to the first electrode 61, the diode comes into play.

[0052] Optionally, the doping concentrations of the first doping region 41, the second doping region 42, and the substrate 10 are respectively greater than the doping concentration of the epitaxial layer 30. That is to say, in this embodiment, the first doping region 41, the second doping region 42, and the substrate 10 are all heavily doped, and the epitaxial layer 30 is lightly doped.

[0053] For example, optionally, the ion implantation doses of the first doping region 41 and the second doping region 42 are respectively in the range of 1×10 15 / cm 2 to 5×10 16 / cm 2 ; and / or, the ion implantation energies of the first doping region 41 and the second doping region 42 are respectively in the range of 30 keV to 120 keV. It should be noted that the ion implantation doses of the first doping region 41 and the second doping region 42 can be the same or different. Similarly, the ion implantation energies of the first doping region 41 and the second doping region 42 can also be the same or different, and the present application does not limit this.

[0054] The ion implantation dose of the buried layer 20 is in the range of 1×10 14 / cm 2 to 1×10 16 / cm 2 ; and / or, the ion implantation energy of the buried layer 20 is in the range of 20 keV to 120 keV. For example, the ion implantation dose of the buried layer 20 can be 1×10 14 / cm 2 , 1×10 15 / cm 2 or 1×10 16 / cm 2etc. The ion implantation energy of the buried layer 20 can be 20 KeV, 30 KeV, 50 KeV, or 120 KeV, etc.

[0055] Optionally, the resistivity of the substrate 10 is between 0.01 Ω·cm and 0.001 Ω·cm. For example, the resistivity of the substrate 10 is 0.001 Ω·cm, 0.002 Ω·cm, 0.005 Ω·cm, 0.008 Ω·cm, 0.01 Ω·cm, etc.

[0056] The resistivity of the epitaxial layer 30 is between 50 Ω·cm and 1000 Ω·cm. For example, the resistivity of the epitaxial layer 30 is 50 Ω·cm, 100 Ω·cm, 300 Ω·cm, 500 Ω·cm, 800 Ω·cm, or 1000 Ω·cm, etc.

[0057] The thickness of the epitaxial layer 30 is between 8 μm and 20 μm. For example, the thickness of the epitaxial layer 30 is 8 μm, 10 μm, 15 μm, or 20 μm, etc.

[0058] To make the performance of the electrostatic protection device better, in this embodiment, optionally, the trench depth of the trench isolation region 50 is greater than the depletion layer width of the diode formed by the epitaxial layer 30 and the substrate 10 at reverse breakdown.

[0059] Moreover, in a feasible implementation manner of this embodiment, the trench isolation region 50 is made of undoped polysilicon or tetraethyl orthosilicate. That is, the material of the trench isolation region 50 is undoped polysilicon or tetraethyl orthosilicate.

[0060] The electrostatic protection device provided by this application can be prepared through the following steps:

[0061] 1) Form a buried layer 20 with a second doping type on a substrate 10 with a first doping type, such as Figure 4 ;

[0062] 2) Form an epitaxial layer 30 with a second doping type on the surfaces of the substrate 10 and the buried layer 20, such as Figure 5 ;

[0063] 3) Form a third doping region 431 with a first doping type and a short-circuit doping region 43 in the epitaxial layer 30 through photolithography and ion implantation processes, such as Figure 6 ;

[0064] 4) Form a fourth doping region 432 with a second doping type and a short-circuit doping region 43 in the epitaxial layer 30 through photolithography and ion implantation processes, such as Figure 7 ;

[0065] 5) A plurality of trench isolation regions 50 are formed in the epitaxial layer 30, the buried layer 20, and the substrate 10, so as to isolate a plurality of functional regions on the epitaxial layer 30 by the plurality of channel isolation regions. Among them, the plurality of functional regions include a first functional region A, a second functional region B, and a third functional region C, and the second functional region B is located between the first functional region A and the third functional region C; two first doping regions 41 and a short-circuit doping region 43 located between the two first doping regions 41 are provided in the first functional region A, a second doping region 42 is provided in the second functional region B, and a first doping region 41 is provided in the third functional region C; as Figure 8 shown.

[0066] 6) A passivation layer 70 is formed on the surface of the epitaxial layer 30 by a chemical vapor deposition process, as Figure 8 shown;

[0067] 7) A contact hole region is formed on the surface of the passivation layer 70 by a photolithography and wet etching process, as Figure 9 shown;

[0068] 8) Metals are formed on the contacts above the first doping region 41 in the third functional region C, the contacts above the second doping region 42 in the second functional region B, and the contacts above the first doping region 41 in the first functional region A above the contact holes by evaporation or sputtering processes to form a second electrode 62; metals are formed on the contact hole above the short-circuit doping region 43 in the first functional region A to form a first electrode 61, as Figure 10 shown.

[0069] 9) The substrate 10 is thinned, and metals are evaporated on the back surface of the substrate 10 to form a third electrode 63, as Figure 3 shown.

[0070] On the other hand, the present utility model provides a terminal device, which includes the above-mentioned electrostatic protection device. The first electrode 61 of the electrostatic protection device is used as the power supply port VCC of the terminal device, the second electrode 62 of the electrostatic protection device is used as the input port I / O of the terminal device, and the third electrode 63 of the electrostatic protection device is used as the ground port GND of the terminal device. Among them, the specific structure and technical effects of the above-mentioned electrostatic protection device have been elaborated and described in detail in the foregoing text, so they will not be repeated herein.

[0071] It should be noted that the number of the second electrodes 62 of the electrostatic protection device can be determined according to the number of the input ports I / O. For example, when the input ports I / O include four (respectively I / O1, I / O2, I / O3, and I / O4), correspondingly, the second electrodes 62 are also four. Correspondingly, the second functional region B and the third functional region C also include four. Those skilled in the art can simply deduce according to the foregoing description and will not be repeated herein.

[0072] The terminal device provided by this application is provided with an electrostatic protection device, and this electrostatic protection device adopts a short-circuit design. In this way, the electrostatic protection device can form a parallel-connected diode and a triode with an open-base region. In this way, when a positive surge or static electricity is applied to the first electrode 61, the triode with an open-base region can function to achieve a flyback characteristic; when a negative surge or static electricity is applied to the first electrode 61, the diode can function. Through the above settings, this application can enable the terminal device to achieve a flyback characteristic and reduce the clamping voltage to avoid the failure of the backend IC due to the influence of static electricity or surge current.

[0073] The above are only optional embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0074] In addition, it should be noted that, in the case of no contradiction, the various specific technical features described in the above specific embodiments can be combined in any suitable manner. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

Claims

1. An electrostatic protection device, characterized in that: The invention comprises a substrate, a plurality of buried layers located on a part of the substrate, an epitaxial layer located on the buried layer and the exposed substrate, a plurality of first doped regions and a plurality of second doped regions located in the epitaxial layer, a short circuit doped region located in the epitaxial layer, a plurality of trench isolation regions for isolating a plurality of functional regions on the epitaxial layer, a first electrode, a second electrode and a third electrode; The multiple functional regions include a first functional region, a second functional region and a third functional region, the second functional region is located between the first functional region and the third functional region; the first functional region is provided with two first doped regions and the short-circuit doped region located between the two first doped regions, the second functional region is provided with the second doped region, and the third functional region is provided with the first doped region; the first electrode is located on the epitaxial layer and connected to the short-circuit doped region, the second electrode is located on the epitaxial layer, and the second electrode is connected to the second doped region of the second functional region, the first doped region of the third functional region and a first doped region of the first doped region close to the second doped region, and the third electrode is located on the side of the substrate away from the epitaxial layer; the substrate and the first doped region adopt a first doping type, and the buried layer, the epitaxial layer and the second doped region adopt a second doping type.

2. The electrostatic protection device according to claim 1, characterized in that: The short-circuit doping region includes a third doping region and two fourth doping regions, and the two fourth doping regions are respectively connected to opposite sides of the third doping region; the doping type of the third doping region is the same as the doping type of the substrate.

3. The electrostatic protection device according to claim 1, characterized in that: The doping concentrations of the first doping region, the second doping region and the substrate are respectively greater than the doping concentration of the epitaxial layer.

4. The electrostatic protection device according to claim 1, characterized in that: The trench depth of the trench isolation region is greater than the depletion layer width of the diode formed by the epitaxial layer and the substrate during reverse breakdown.

5. The electrostatic protection device according to claim 1, characterized in that: The trench isolation region is filled with non-doped polysilicon or tetraethyl orthosilicate.

6. The electrostatic protection device according to claim 1, characterized in that: The resistivity of the substrate is between 0.01Ω·cm and 0.001Ω·cm; and / or, the resistivity of the epitaxial layer is between 50 Ω·cm and 1000 Ω·cm; And / or, the epitaxial layer has a thickness between 8 μm and 20 μm.

7. The electrostatic protection device according to claim 1, characterized in that: The first doping type is P type, and the second doping type is N type; or, the first doping type is N type, and the second doping type is P type.

8. A terminal device, characterized in that: An electrostatic protection device comprising any one of claims 1 to 7, wherein the first electrode of the electrostatic protection device is used as a power port of the terminal device, the second electrode of the electrostatic protection device is used as an input port of the terminal device, and the third electrode of the electrostatic protection device is used as a ground port of the terminal device.

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