Circuit board and electronic equipment
By introducing a buried dielectric layer into the circuit board and a via structure formed by metallization of laser drilling, the problem of difficulty in maintaining high-density wiring and electrical performance in the circuit board thinning in the prior art is solved, and the ultimate thinning of the circuit board and signal quality improvement is achieved.
Patent Information
- Application Number
- CN202421620424.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-09
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-07-09
AI Technical Summary
It is difficult for existing circuit boards to maintain high-density wiring and good electrical performance at the same time during thinning, and the processing technology is complex and the cost is high.
By introducing a buried dielectric layer into the circuit board, and using laser drilling combined with metallization, the direct interconnection of the buried dielectric layer and the core layer is achieved, reducing signal transmission paths, and simplifying wiring design.
It achieves the ultimate thinning of the circuit board, while improving signal transmission quality, simplifying processing technology, reducing costs, and is suitable for high-density and high-performance electronic equipment.
Smart Images
Figure CN222996737U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of circuit boards, and more particularly, to a circuit board and an electronic device using the same. Background Art
[0002] As the thinning of electronic devices has increasingly become a core competitive point and selling point, the thinning of electronic components has become more and more important. For example, for mobile phones, the thickness of the printed circuit board (PCB) in the thickness stacking direction occupies an important part, and the thinning of the PCB plays an important role in the thinning of the whole machine. Summary of the Utility Model
[0003] In a first aspect of this application, a circuit board is provided. The circuit board includes a plurality of wiring layers and a plurality of insulating layers, and each insulating layer is located between two adjacent wiring layers. The plurality of insulating layers include a core insulating layer, a lower insulating layer, and a buried capacitor dielectric layer. The lower insulating layer is located between the core insulating layer and the buried capacitor dielectric layer. The lower insulating layer and the buried capacitor dielectric layer are located in the build-up layer, and the thickness of the buried capacitor dielectric layer is less than the thickness of the lower insulating layer. The plurality of wiring layers include a lower wiring layer, a first buried capacitor wiring layer, and a second buried capacitor wiring layer. The first buried capacitor wiring layer is located on the surface of the buried capacitor dielectric layer close to the core insulating layer, and the second buried capacitor wiring layer is located on the surface of the buried capacitor dielectric layer facing away from the core insulating layer. The lower wiring layer is located between the core insulating layer and the first buried capacitor wiring layer. Both the first buried capacitor wiring layer and the second buried capacitor wiring layer are non-impedance line routing layers. The circuit board further includes a first via hole, which is formed by laser drilling and then metallization. The first via hole penetrates through the buried capacitor dielectric layer and the lower insulating layer, and directly connects the second buried capacitor wiring layer, the first buried capacitor wiring layer, and the lower wiring layer.
[0004] For the circuit board of the first aspect of this application, by setting the buried capacitor dielectric layer as the insulating layer, compared with prepreg (PP) or resin coated copper (RCC) materials, the buried capacitor dielectric layer has a more obvious effect on the thinning of the circuit board, so it is beneficial to the thinning and lightening of the circuit board.
[0005] In addition, in the circuit board of the first aspect of this application, the first via hole formed by laser drilling combined with metallization realizes the direct interconnection of the first buried capacitor wiring layer, the second buried capacitor wiring layer, and the lower wiring layer after the buried capacitor dielectric layer is applied to the build-up layer (non-core layer) and laminated with the core layer, so that the lower wiring layer can be directly interconnected with the first buried capacitor wiring layer and / or the second buried capacitor wiring layer without passing through other wiring layers, which is beneficial to the miniaturization and thinning of the circuit board.
[0006] It should be noted that in the embodiments of the present application, the core layer refers to the central layer of the circuit board, which is used to provide the main structural support for the circuit board, and the build-up layer refers to the additional dielectric layer and / or wiring layer stacked above and / or below the core layer.
[0007] In addition, since the buried capacitor dielectric layer is a capacitive material and both the first buried capacitor wiring layer and the second buried capacitor wiring layer are non-impedance line routing layers, a capacitor can be formed between the first buried capacitor wiring layer, the buried capacitor dielectric layer, and the second buried capacitor wiring layer, which is conducive to reducing the number of physical capacitors connected on the circuit board, thereby facilitating further thinning of the circuit board.
[0008] In some embodiments, along the direction from the lower insulating layer to the buried capacitor dielectric layer, the size of the first via gradually increases. Thus, by setting the first via as a tapered via, the aperture change of the first via has a smooth transition, which is beneficial to reducing the local stress concentration caused by the sharp change of the aperture, and further improving the mechanical reliability and durability of the via.
[0009] In some embodiments, the first via is a stepped via, and the size of the first via at the position of the buried capacitor dielectric layer is larger than the size of the first via at the position of the lower insulating layer. Thus, by setting the first via as a stepped via, the larger aperture provides a larger contact area at the buried capacitor dielectric layer, which helps to disperse stress and reduce the risk of mechanical damage; the smaller aperture in the lower insulating layer part can reduce the risk of material damage during the drilling process, improve the processing accuracy, and at the same time reduce the processing time and cost.
[0010] In some embodiments, the multiple insulating layers further include an upper insulating layer, which is located on the side of the buried capacitor dielectric layer away from the core insulating layer. The multiple wiring layers further include an upper wiring layer, which is located on the side of the second buried capacitor wiring layer away from the core insulating layer. The circuit board further includes a second via, which penetrates the upper insulating layer, the buried capacitor dielectric layer, and the lower insulating layer and directly connects the upper wiring layer and the lower wiring layer. Thus, by setting the second via to directly connect the upper wiring layer and the lower wiring layer, it is avoided that the signal needs to pass through multiple intermediate layers, thereby reducing the signal transmission path length. This helps to reduce the signal transmission time and signal delay. Moreover, using the second via to directly connect the upper wiring layer and the lower wiring layer can simplify the wiring design and manufacturing process of the circuit board, reduce the complex wire routing and multi-layer via design, and reduce the design complexity and manufacturing cost.
[0011] In some embodiments, the circuit board further includes a third via hole that penetrates the upper insulating layer and the buried capacitor dielectric layer and directly connects the upper wiring layer and the first buried capacitor wiring layer. Thus, by providing the third via hole to directly connect the upper wiring layer and the first buried capacitor wiring layer, it helps to shorten the signal path, reduce signal delay and loss. In addition, by providing the third via hole, the wiring channels and interlayer connection options are increased, which is beneficial to optimizing space utilization and wiring design.
[0012] In some embodiments, the circuit board further includes a fourth via hole that penetrates the upper insulating layer and directly connects the second buried capacitor wiring layer and the upper wiring layer. Thus, by providing the fourth via hole to directly connect the second buried capacitor wiring layer and the upper wiring layer, it helps to shorten the signal path, reduce signal delay and loss. In addition, by providing the fourth via hole, the wiring channels and interlayer connection options are increased, which is beneficial to optimizing space utilization and wiring design.
[0013] In some embodiments, the circuit board further includes a fifth via hole that penetrates the buried capacitor dielectric layer and the lower insulating layer and directly connects the first buried capacitor wiring layer and the lower wiring layer. Thus, it is beneficial to increase the ability of the circuit board for vertical connection between layers, provide more wiring channels and options, optimize the space utilization of the circuit design, and meet the requirements of high-density circuit design.
[0014] In some embodiments, the circuit board further includes a sixth via hole that penetrates the buried capacitor dielectric layer and directly connects the first buried capacitor wiring layer and the second buried capacitor wiring layer. Thus, it is beneficial to realize the interconnection between any layers of the circuit board and achieve the high density, thinness and lightness of the circuit board.
[0015] In some embodiments, the total thickness of the buried capacitor dielectric layer, the first buried capacitor wiring layer and the second buried capacitor wiring layer ranges from 9 microns to 42 microns. The thickness of the buried capacitor dielectric layer ranges from 3 microns to 22 microns. The thicknesses of the first buried capacitor wiring layer and the second buried capacitor wiring layer both range from 3 microns to 18 microns. Thus, it is beneficial to maintain good electrical performance and mechanical strength while meeting the requirements of high-density wiring of the circuit board, and it is applicable to complex high-performance electronic devices.
[0016] In some embodiments, the lower wiring layer is located on the surface of the core insulating layer. Thus, it helps to shorten the signal transmission path, reduce signal delay, and improve signal transmission efficiency. Moreover, this design reduces the number of layers in the signal path, which helps to reduce the overall impedance and parasitic capacitance of the circuit and improve the electrical performance of the circuit. Since the need for intermediate layers is reduced, this design can simplify the manufacturing process of the circuit board, reduce material and manufacturing costs, and improve production efficiency at the same time.
[0017] In some embodiments, at least one insulating layer is provided between the lower wiring layer and the core insulating layer. Thus, by adding an insulating layer between the lower wiring layer and the core insulating layer, the arrangement of the wiring layers between the lower wiring layer and the core insulating layer can be flexibly selected.
[0018] The second aspect of the present application provides an electronic device. The electronic device includes electronic components and the circuit board of the first aspect of the present application, and the electronic components are electrically connected to the circuit board.
[0019] The electronic device of the second aspect of the present application has at least the same advantages as the circuit board of the first aspect of the present application, and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic cross-sectional view of the circuit board according to the first embodiment of the present application.
[0021] Figure 2A , Figure 2B and Figure 2C They are respectively schematic cross-sectional views of circuit boards of different related technologies.
[0022] Figure 3 It is a schematic cross-sectional view of the circuit board according to the second embodiment of the present application.
[0023] Figure 4 It is a schematic cross-sectional view of forming a core layer in the method for manufacturing a circuit board according to an embodiment of the present application.
[0024] Figure 5 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 3 It is a schematic cross-sectional view of adding a layer on the stacked structure in
[0025] Figure 6A It is a schematic cross-sectional view of providing a buried capacitor board in the method for manufacturing a circuit board according to an embodiment of the present application.
[0026] Figure 6B It is a schematic cross-sectional view of a buried capacitor substrate in the method for manufacturing a circuit board according to an embodiment of the present application.
[0027] Figure 7 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 6B It is a schematic cross-sectional view after pressing the buried capacitor substrate in Figure 4 to the stacked structure in
[0028] Figure 8 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 7 It is a schematic cross-sectional view after laser drilling on the stacked structure shown in
[0029] Figure 9 In the method for manufacturing a circuit board according to an embodiment of the present application,Figure 8 Schematic cross-sectional view after metallization on the laminated structure shown.
[0030] Figure 10 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 9 Schematic cross-sectional view after circuit etching on the laminated structure shown.
[0031] Figure 11 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 10 Schematic cross-sectional view of adding a layer on the laminated structure shown.
[0032] Figure 12 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 11 Schematic cross-sectional view after laser drilling on the laminated structure shown.
[0033] Figure 13 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 12 Schematic cross-sectional view after metallization on the laminated structure shown.
[0034] Figure 14 In the method for manufacturing a circuit board according to an embodiment of the present application, Figure 13 Schematic cross-sectional view after circuit etching and forming a solder mask layer on the laminated structure shown.
[0035] Figure 15 Schematic cross-sectional views of each step for manufacturing a first via in a stepped hole shape in the method for manufacturing a circuit board according to an embodiment of the present application.
[0036] Main element symbol description:
[0037] Circuit boards 10, 10', 20, 20', 30'
[0038] Core layer 11
[0039] First core wiring layer 11a
[0040] Second core wiring layer 11b
[0041] Core insulation layer 11c
[0042] First added layer 12a
[0043] Second added layer 12b
[0044] First solder mask layer 13a, 13a', 23a
[0045] Second solder mask layer 13b, 13b', 23b
[0046] Wiring layers L1 to L14, L1' to L12'
[0047] Insulation layers I1 to I13, I1' to I11'
[0048] First surface S1
[0049] Second surface S2
[0050] Core layer via V0
[0051] First vias V1, V1a, V1b
[0052] Second via V2
[0053] Third via V3
[0054] Fourth via V4
[0055] Fifth via V5
[0056] Sixth via V6
[0057] First openings H1a, H1b
[0058] Second opening H2
[0059] Third opening H3
[0060] Fourth opening H4
[0061] Fifth opening H5
[0062] Sixth opening H6
[0063] Large hole P1
[0064] Small hole P2
[0065] Embedded capacitor substrates C1, C2, C3, C4
[0066] Embedded capacitor board 100
[0067] Embedded capacitor dielectric layer 110
[0068] First embedded capacitor wiring layer 111
[0069] Second embedded capacitor wiring layer 112
[0070] Conductive layers 120, 130, 310, 320, 410, 420, 510, 520
[0071] Temporary carrier board 200 Detailed implementation manner
[0072] Figure 1 It is a cross-sectional schematic diagram of a circuit board according to the first embodiment of the present application. AsFigure 1 As shown in Figure 1 , the circuit board 10 includes a plurality of wiring layers (labeled L1 to L14) and a plurality of insulating layers (labeled I1 to I13). Each insulating layer is located between two adjacent wiring layers to space the two adjacent wiring layers apart from each other. Hereinafter, an example in which the circuit board 10 includes 14 wiring layers and 13 insulating layers will be described. In other embodiments, the number of wiring layers and insulating layers in the circuit board is not limited to this.
[0073] Specifically, in the thickness direction of the circuit board 10, the 14 wiring layers are, in sequence, wiring layer L1, wiring layer L2, wiring layer L3,..., wiring layer L14, and the 13 insulating layers are, in sequence, insulating layer I1, insulating layer I2, insulating layer I3,..., insulating layer I13. Among them, insulating layers I1 to I6 and wiring layers L1 to L6 form the first build-up layer 12a. Insulating layer I7, wiring layer L7, and wiring layer L8 form the core layer 11. Insulating layers I8 to I13 and wiring layers L9 to L14 form the second build-up layer 12b.
[0074] The core layer 11 can be formed by patterning a core substrate having an intermediate dielectric layer and conductive layers on both sides. Insulating layer I7 includes opposite first surface S1 and second surface S2. The first build-up layer 12a can be formed by building up on the side where the first surface S1 of the core layer 11 is located, and the second build-up layer 12b can be formed by building up on the side where the second surface S2 of the core layer 11 is located. Thus, hereinafter, the core wiring layer L7 located on the first surface S1 is also referred to as the first core wiring layer 11a, the core wiring layer L8 located on the second surface S2 is also referred to as the second core wiring layer 11b, and insulating layer I7 is also referred to as the core insulating layer 11c. In addition, insulating layers I1 to I6 and insulating layers I8 to I13 are referred to as build-up insulating layers, and wiring layers L1 to L6 and wiring layers L9 to L14 are referred to as build-up wiring layers.
[0075] Among the plurality of build-up insulating layers, the materials of some insulating layers are buried capacitor materials to reduce the thickness of the circuit board. Specifically, in the circuit board 10, the materials of insulating layer I3 and insulating layer I11 are buried capacitor materials, while the materials of other build-up insulating layers (i.e., insulating layers I1, I2, I4 to I6, I8 to I10, I12, I13) can be PP, and the thicknesses of both insulating layer I3 and insulating layer I11 are less than those of other build-up insulating layers.
[0076] More specifically, the insulating layer I3 and the wiring layers L3 and L4 located on the opposite sides of the insulating layer I3 can be formed by laminating a buried capacitor plate on the side where the first surface S1 of the core layer 11 is located and then patterning the buried capacitor plate. The insulating layer I11 and the wiring layers L11 and L12 located on the opposite sides of the insulating layer I11 can be formed by laminating a buried capacitor plate on the side where the second surface S2 of the core layer 11 is located and then patterning the buried capacitor plate.
[0077] Thus, for convenience of description hereinafter, the stack composed of the wiring layer L3, the insulating layer I3, and the wiring layer L4 is also referred to as the buried capacitor substrate C1, and the stack composed of the wiring layer L11, the insulating layer I11, and the wiring layer L12 is also referred to as the buried capacitor substrate C2.
[0078] In addition, hereinafter, the insulating layer I3 and the insulating layer I11 are also referred to as the buried capacitor dielectric layer 110, the wiring layer L4 and the wiring layer L11 are referred to as the first buried capacitor wiring layer 111, and the wiring layer L3 and the wiring layer L12 are referred to as the second buried capacitor wiring layer 112.
[0079] That is, the first buried capacitor wiring layer 111 is located on the surface of the buried capacitor dielectric layer 110 close to the core insulating layer 11c, and the second buried capacitor wiring layer 112 is located on the surface of the buried capacitor dielectric layer 110 facing away from the core insulating layer 11c.
[0080] Furthermore, hereinafter, the insulating layer located between the core insulating layer 11c and the buried capacitor dielectric layer 110 (i.e., any one of the insulating layers I4 to I6, I8 to I10) is defined as the lower insulating layer, and the insulating layer located on the side of the buried capacitor dielectric layer 110 facing away from the core insulating layer 11c (i.e., any one of the insulating layers I1, I2, I12, and I13) is defined as the upper insulating layer.
[0081] The wiring layer located between the first buried capacitor wiring layer 111 and the core insulating layer 11c (i.e., any one of the wiring layers L5 to L7, L8 to L10) is defined as the lower wiring layer, and the wiring layer located on the side of the second buried capacitor wiring layer 112 away from the core insulating layer 11c (i.e., any one of the wiring layers L1 to L2, L13 to L14) is defined as the upper wiring layer. That is to say, in the embodiment of the present application, the lower wiring layer can be a core wiring layer located on the surface of the core insulating layer (such as the wiring layers L7 and L8), or an additional wiring layer spaced from the core insulating layer I7 by at least one insulating layer (such as the wiring layers L5, L6, L9, L10).
[0082] In this embodiment, the circuit board 10 includes a plurality of vias with different depths to achieve interconnection between any wiring layers.
[0083] Specifically, the circuit board 10 includes a core layer via V0. The core layer via V0 penetrates through the core insulating layer 11c and directly connects the first core wiring layer 11a and the second core wiring layer 11b.
[0084] The circuit board 10 further includes a first via V1. The first via V1 can be formed by laser drilling followed by metallization. In the first build-up layer 12a, the first via V1 penetrates through the buried capacitor dielectric layer 110 in the buried capacitor substrate C1 and the insulating layer I4 in the lower insulating layer, and directly connects the second buried capacitor wiring layer 112, the first buried capacitor wiring layer 111, and the wiring layer L5 in the lower wiring layer.
[0085] In this embodiment, the first via V1 includes a first via V1a and a first via V1b. Among them, the sizes of the first via V1a and the first via V1b at the position of the buried capacitor dielectric layer 110 are both larger than the size of the first via V1a at the position of the insulating layer I4.
[0086] The difference between the first via V1a and the first via V1b is that the first via V1a is a tapered via. Along the direction from the lower insulating layer to the buried capacitor dielectric layer 110, the size of the first via V1a gradually increases. While the first via V1b is a stepped via.
[0087] By setting the first via V1a as a tapered via, the aperture change of the first via V1a has a smooth transition, which is beneficial to reducing the local stress concentration caused by the sharp change of the aperture, and thus improving the mechanical reliability and durability of the via.
[0088] By setting the first via V1b as a stepped via, the larger aperture provides a larger contact area in the buried capacitor dielectric layer 110, which helps to disperse stress and reduce the risk of mechanical damage; the smaller aperture in the lower insulating layer part can reduce the risk of material damage during the drilling process, improve the processing accuracy, and at the same time reduce the processing time and cost.
[0089] The circuit board 10 further includes a second via V2. In the first build-up layer 12a, the second via V2 penetrates through the insulating layer I2 in the upper insulating layer, the buried capacitor dielectric layer 110, and the insulating layer I4 in the lower insulating layer, and directly connects the wiring layer L2 in the upper wiring layer and L5 in the lower wiring layer.
[0090] By setting the second via V2 to directly connect the upper wiring layer and the lower wiring layer, it avoids the signal needing to pass through multiple intermediate layers, thereby reducing the signal transmission path length. This helps to reduce the signal transmission time and signal delay. Moreover, using the second via V2 to directly connect the upper wiring layer and the lower wiring layer can simplify the wiring design and manufacturing process of the circuit board, reduce the complex wire winding and multi-layer via design, and reduce the design complexity and manufacturing cost.
[0091] The circuit board 10 further includes a third via V3. In the first build-up layer 12a, the third via V3 penetrates through the insulating layer I2 in the upper insulating layer and the buried capacitor dielectric layer 110, and is directly connected to the wiring layer L2 in the upper wiring layer and the first buried capacitor wiring layer 111.
[0092] The circuit board 10 further includes a fourth via V4. In the first build-up layer 12a, the fourth via V4 penetrates through the insulating layer I1 in the upper insulating layer, and is directly connected to the second buried capacitor wiring layer 112 and the wiring layer L1 in the upper wiring layer.
[0093] The circuit board 10 further includes a fifth via V5. In the first build-up layer 12a, the fifth via V5 penetrates through the buried capacitor dielectric layer 110 and the insulating layer I4 in the lower insulating layer, and is directly connected to the first buried capacitor wiring layer 111 and the wiring layer L5 in the lower wiring layer.
[0094] The circuit board 10 further includes a sixth via V6. In the first build-up layer 12a, the sixth via V6 penetrates through the buried capacitor dielectric layer 110, and is directly connected to the first buried capacitor wiring layer 111 and the second buried capacitor wiring layer 112.
[0095] In summary, by providing the first via V1, a direct connection among the first buried capacitor wiring layer 111, the second buried capacitor wiring layer 112, and the lower wiring layer can be achieved; by providing the second via V2, a direct connection between the upper wiring layer and the lower wiring layer can be achieved; by providing the third via V3, a direct connection between the upper wiring layer and the first buried capacitor wiring layer 111 can be achieved; by providing the fourth via V4, a direct connection between two upper wiring layers can be achieved; by providing the fifth via, a direct connection between the second buried capacitor wiring layer and the lower wiring layer can be achieved; by providing the sixth via V6, a direct connection between the first buried capacitor wiring layer 111 and the second buried capacitor wiring layer 112 can be achieved.
[0096] In addition, in the circuit board 10, there are also vias for directly connecting the first buried capacitor wiring layer 111 and the lower wiring layer, vias for directly connecting the second buried capacitor wiring layer 112 and the upper wiring layer, and vias for directly connecting any two lower wiring layers.
[0097] Understandably, in the second build-up layer 12b, one or more of the above vias can also be formed to interconnect any different-layer wiring layers on the side where the second surface S2 of the core insulating board 11c is located.
[0098] In the embodiment of the present application, the total thickness range of the buried capacitor dielectric layer 110, the first buried capacitor wiring layer 111, and the second buried capacitor wiring layer 112 is from 9 micrometers to 42 micrometers. The thickness range of the buried capacitor dielectric layer 110 is from 3 micrometers to 22 micrometers. The thickness ranges of the first buried capacitor wiring layer 111 and the second buried capacitor wiring layer 112 are both from 3 micrometers to 18 micrometers.
[0099] The materials of the buried capacitor dielectric layer 110 include resin and filler. The materials of the first buried capacitor wiring layer 111 and the second buried capacitor wiring layer 112 are, for example, copper foil, but are not limited thereto.
[0100] It should be noted that at present, the thinning of the circuit boards of electronic devices such as mobile phones mainly relies on introducing ultra-thin PP or RCC materials. However, the thinnest thickness of the currently known mass-produced PP or RCC materials is 15 μm, and it is necessary to use thin copper (≤12 μm), which greatly limits the extreme thinning of the PCB and will also cause problems such as increased DC voltage drop and trace insertion loss. In the circuit board of the embodiment of the present application, the buried capacitor dielectric layer 110 can be made as thin as 3 μm. Compared with the PP or RCC materials, the buried capacitor dielectric layer 110 has a more obvious effect on the thinning of the circuit board.
[0101] Figure 2A is a circuit board 10’ (12 wiring layers) of a traditional PP system. Among them, 13a’ and 13b’ are the first solder mask layer at the top and the second solder mask layer at the bottom, respectively. L1’ to L12’ are all wiring layers, and I1’ to I11’ are all insulating layers, and the materials of I1’ to I11’ are all PP. Compared with Figure 2A the circuit board 10’ (12-layer wiring layer), the circuit board 10 (14-layer wiring layer) of the embodiment of the present application increases two layers of wiring resources under basically the same thickness. Moreover, although the circuit board 10 has two more wiring layers than the circuit board 10’, the thickness only increases by 20 μm. In addition, compared with the traditional PP system circuit board (14-layer wiring layer), the circuit board 10 of the embodiment of the present application is thinned by about 0.07 mm under the same number of wiring layers.
[0102] It should be noted that although buried capacitor materials are applied in the circuit boards of related technologies. However, the incoming buried capacitor materials are basically composed of an intermediate buried capacitor dielectric layer and copper foils on the opposite sides of the buried capacitor dielectric layer. Therefore, the application scenarios of the buried capacitor materials in the circuit board are mainly for the core layer of the circuit board to realize the processing of the PCB or the carrier board to be compatible with the convenience of process processing (such as Figure 2B the buried capacitor dielectric layer 110 of the circuit board 20’ in), or using the Core stacking method to first make double-sided circuits with thicker buried capacitor materials, and then cooperate with PP and mechanical drilling to realize the processing of the PCB, that is, the thicker buried capacitor materials are applied to the PP layer with mechanical vias (such as Figure 2C the buried capacitor dielectric layer 110 of the circuit board 30’ in).
[0103] Among them, arbitrary-order PCBs are widely used in the circuit boards of electronic devices such as mobile phones, tablet computers, and laptop computers, and there is a strong demand for PCB thinning. However, in the circuit boards of electronic devices such as mobile phones, tablet computers, and laptop computers, important signal lines need to be set at the core layer position. Since the buried capacitance dielectric layer has a high dielectric constant, it cannot be applied to the core layer position of the circuit board, but can only be applied between the PPs of the power layer, non-important signal line layer, and ground line layer. However, there is currently no structure and processing technology for applying a double-layer copper foil buried capacitance material with laser drilling to the PP layer in an arbitrary-order PCB.
[0104] In the circuit board 10 of the embodiment of the present application, the buried capacitance dielectric layer 110 is applied to the build-up (non-Core layer). Compared with using PP material or RCC material in the related art, it is beneficial to reduce the thickness of the circuit board 10 under the same number of wiring layers, and under a substantially same thickness, it is beneficial to increase the number of wiring layers. The increased wiring layers can be used as non-impedance trace layers to make full use of the trace space inside the circuit board.
[0105] In addition, since the buried capacitance dielectric layer 110 is a capacitive material, it is also beneficial to increase the local capacitive characteristics between the first buried capacitance trace layer 111 and the second buried capacitance trace layer 112, and improve the characteristics of the power supply distribution network (PDN) of the power supply.
[0106] Specifically, non-impedance lines and impedance lines are two different types of signal transmission lines. An impedance line (Impedance Controlled Line) refers to a transmission line whose impedance is precisely calculated and controlled. Impedance lines are often used to handle high-speed data transmission, such as signal lines for interfaces such as USB, HDMI, and PCI Express. A non-impedance line (Non-Impedance Controlled Line) refers to a transmission line without specially designed or controlled impedance. These lines do not require precise calculation of impedance values during design and are usually used for low-speed or less sensitive signal transmission, such as power lines, ground lines, and control lines connecting physical buttons (such as power buttons and volume buttons).
[0107] Specifically, in the first build-up 12a of the circuit board 10, both the first buried capacitance trace layer 111 and the second buried capacitance trace layer 112 are non-impedance line trace layers. More specifically, in the first build-up 12a of the circuit board 10, the wiring layers L2 to L7 are successively a signal line layer, a power layer, a ground layer, a power layer, a signal line layer, and a signal line layer. That is, the first buried capacitance trace layer 111 and the second buried capacitance trace layer 112 are used to respectively construct the power layer / ground layer to improve the direct current (DC) characteristics of the power supply, and the direct current resistance (DCR) can be reduced by 10%.
[0108] Thus, for the circuit board according to the embodiments of the present application, through the settings of the buried capacitor dielectric layer, the first buried capacitor wiring layer, and the second buried capacitor wiring layer, it is beneficial to reduce the thickness of the circuit board without affecting the electrical performance indexes of the circuit board, which plays an important role in the thinning of electronic devices applying the same.
[0109] In addition, it should be noted that since copper foils already exist on the opposite two surfaces of the ultra-thin buried capacitor material when it is received, it is difficult in the aspects of circuit processing and via interconnection processing on both sides of the buried capacitor material. Different from Figure 2C the way of realizing electrical connection by matching the buried capacitor dielectric layer 110 with mechanical drilling in
[0110] Specifically, Figure 3 for the circuit board 20 of the second embodiment of the present application. The following will be combined with Figures 3 to 15 to specifically illustrate how the circuit board according to the embodiments of the present application realizes the processing and interconnection of the buried capacitor dielectric layer on the build-up by laser drilling and then metallization at the buried capacitor dielectric layer.
[0111] As Figure 1 and Figure 3 shown, the circuit board 20 of the second embodiment is substantially the same as the circuit board 10 of the first embodiment, the difference being that: the number of wiring layers in the circuit board 20 is 10, and the number of insulating layers is 9.
[0112] More specifically, the circuit board 20 includes a core layer 21, a first build-up layer 22a, a second build-up layer 22b, a first solder mask layer 23a, and a second solder mask layer 23b. The first build-up layer 22a and the second build-up layer 22b are respectively formed by build-up on the opposite two sides of the core layer 21. The first solder mask layer 23a is on the side of the first build-up layer 22a away from the core layer 21, and the second solder mask layer 23b is located on the side of the second build-up layer 22b away from the core layer 21.
[0113] In the circuit board 20, the wiring layer L2, the wiring layer L3, and the insulating layer I2 form a buried capacitor substrate C3, and the wiring layer L8, the wiring layer L9, and the insulating layer I8 form a buried capacitor substrate C4. The functions of the core layer vias V0, the first via V1 to the sixth via V6 in the circuit board 20 refer to the description of the circuit board 10 above. The structure of the core layer 21 can refer to the description of the core layer 11 above.
[0114] The difference between the first build-up layer 22a and the first build-up layer 12a is that the first build-up layer 22a has one less upper wiring layer, one less upper insulating layer, one less lower wiring layer, and one less lower insulating layer than the first build-up layer 12a.
[0115] The difference between the second build-up layer 22b and the second build-up layer 12b is that the second build-up layer 22b has one less upper wiring layer, one less upper insulating layer, one less lower wiring layer, and one less lower insulating layer than the second build-up layer 12b.
[0116] In the circuit board 10, between the first surface S1 of the core insulating layer 11c and the buried capacitor dielectric layer 110, the insulating layer I6 and the wiring layer L6 are formed through the first build-up, the insulating layer I5 and the wiring layer L5 are formed through the second build-up, the buried capacitor substrate C1 is formed through the third build-up, then the insulating layer I2 and the wiring layer L2 are formed through the fourth build-up, and the insulating layer I1 and the wiring layer L1 are formed through the fifth build-up. In the circuit board 20, between the first surface S1 of the core insulating layer 11c and the buried capacitor dielectric layer 110, the insulating layer I4 and the wiring layer L4 are formed through the first build-up, the buried capacitor substrate C3 is formed through the second build-up, and then the insulating layer I1 and the wiring layer L1 are formed through the third build-up.
[0117] In other embodiments, the number of build-ups between the first surface S1 of the core insulating layer 11c and the buried capacitor dielectric layer 110 can be 1 time, 2 times, multiple times, or there can be none; in the first build-up, the number of build-ups between the buried capacitor dielectric layer 110 and the first solder mask layer can be 1 time, 2 times, multiple times, or there can be none.
[0118] Similarly, the number of build-ups between the second surface S2 of the core insulating layer 11c and the buried capacitor dielectric layer 110 can be 1 time, 2 times, multiple times, or there can be none; in the second build-up, the number of build-ups between the buried capacitor dielectric layer 110 and the second solder mask layer can be 1 time, 2 times, multiple times, or there can be none.
[0119] The following specifically describes the manufacturing method of the circuit board 20. Among them, the manufacturing method of the circuit board 20 includes the following steps (1) to (11). According to different requirements, the order of some steps or sub-steps of the manufacturing method of the circuit board can be changed, and some steps or sub-steps can be omitted or combined.
[0120] Step (1): Form the core layer.
[0121] As Figure 4 shown, step (1) can provide a core layer substrate composed of a middle resin insulating layer and two side conductive layers, penetrate the two side conductive layers through laser processing, mechanical processing, or etching to form openings, and metallize the inside of the openings, so that core layer vias V0 are formed at the positions corresponding to the openings, the two side conductive layers form the wiring layer L5 and the wiring layer L6, and the middle resin insulating layer forms the insulating layer I5, thereby obtaining the core layer 21.
[0122] Step (2): Conventional build-up manufacturing.
[0123] Specifically, after the conventional PP is laminated onto the core layer 21, laser drilling and circuit fabrication are performed. Among them, in step (2), build-up layers can be respectively formed on opposite sides of the core layer 21, and the number of build-up layers on each side of the core layer 21 can be 1 time, multiple times, or 0 times.
[0124] As Figure 5 shown, on one side where the first surface S1 of the core layer 21 is located, a build-up layer is formed once to obtain the insulating layer I4 and the wiring layer L4. On the other side where the second surface S2 of the core layer 21 is located, a build-up layer is formed once to obtain the insulating layer I6 and the wiring layer L7.
[0125] Step (3): Processing of the buried capacitor substrate.
[0126] Specifically, as Figure 6A shown, a buried capacitor board 100 is provided. The buried capacitor board 100 includes a buried capacitor dielectric layer 110 and conductive layers 120 and 130 on opposite surfaces of the buried capacitor dielectric layer 110.
[0127] As Figure 6B shown, after the buried capacitor board 100 is bonded to a relatively thick temporary carrier board 200 or a so-called detachable core board, single-sided circuit fabrication is performed on the buried capacitor board 100. Among them, the conductive layer 120 forms the wiring layer L3.
[0128] It should be noted that since the thickness of the buried capacitor dielectric layer 110 is very thin, performing single-sided circuit fabrication on the buried capacitor board 100 using the temporary carrier board 200 is beneficial to avoiding damage to the buried capacitor dielectric layer 110 or the conductive layers 120 and 130.
[0129] Step (4): The temporary carrier board 200 of the buried capacitor board 100 with the fabricated circuit is laminated onto the stack fabricated in step (2) together with copper-free PP, and then the temporary carrier board 200 is removed.
[0130] As Figure 5 and Figure 7 shown, in step (4), a buried capacitor board 100 is laminated onto one side where the first surface S1 of the core layer 21 is located through copper-free PP. The copper-free PP forms the insulating layer I3, the buried capacitor dielectric layer 110 in the buried capacitor board 100 forms the insulating layer I2, and the circuit formed by the conductive layer 120 serves as the wiring layer L3.
[0131] In step (4), another buried capacitor plate 100 is laminated to the side where the second surface S2 of the core layer 21 is located through copper-free PP. The copper-free PP forms an insulating layer I7, the buried capacitor dielectric layer 110 in the another buried capacitor plate 100 forms an insulating layer I8, and the circuit formed by the conductive layer 120 serves as a wiring layer L8. It should be noted that in other embodiments, the buried capacitor plate 100 can be laminated on one side of the core layer 21. Or, the number of buried capacitor plates 100 laminated on one side of the core layer 21 is greater than 1.
[0132] Step (5): Laser drilling: Based on the requirements of circuit and hole interconnection, openings with different depths are formed by laser drilling.
[0133] As Figure 8 shown, in step (5), the depth of the sixth opening H6 is less than that of the fifth opening H5, the first opening H1a, and the first opening H1b. The sixth opening H6 exposes the first buried capacitor wiring layer 111. The second opening H5 on the side where the second surface S2 is located exposes the wiring layer L7 in the lower wiring layer. The fifth opening H5, the first opening H1a, and the first opening H1b on the side where the first surface S1 is located all expose the wiring layer L4 in the lower wiring layer.
[0134] The differences between the fifth opening H5, the first opening H1a, and the first opening H1b on the side where the first surface S1 is located are as follows: The first opening H1a and the first opening H1b also penetrate through the first buried capacitor wiring layer 111.
[0135] The difference between the first opening H1a and the first opening H1b is that the first opening H1a is a tapered hole, and the first opening H1b is a stepped hole.
[0136] It should be noted that during the process of forming the first opening H1a in step (5), ultraviolet laser or carbon dioxide laser can be used for drilling, or first use carbon dioxide laser for drilling, and then use ultraviolet laser for further drilling until the wiring layer L4 is exposed.
[0137] Step (6): Metallization treatment.
[0138] Specifically, the metallization treatment includes copper plating treatment and electroplating treatment. As Figure 9 shown, the laminated structure obtained after laser drilling in step (5) is subjected to copper plating treatment, and then each opening is electroplated completely to obtain the conductive layer 310 and the conductive layer 320.
[0139] Step (7): Circuit etching.
[0140] As Figure 9 and Figure 10As shown, after the circuit is fabricated on the conductive layer 310, the wiring layer L1 is obtained, and on the side where the first surface S1 is located, the sixth via V6, the fifth via V5, the first via V1a, and the first via V1b are respectively obtained at the sixth opening H6, the fifth opening H5, the first opening H1a, and the first opening H1b. The sixth via V6 is used to achieve the direct electrical connection between the wiring layer L2 and the wiring layer L3. The fifth via V5 is used to achieve the direct electrical connection between the wiring layer L2 and the wiring layer L4. The first opening H1a and the first opening H1b are used to achieve the direct electrical connection among the wiring layer L2, the wiring layer L3, and the wiring layer L4. After the circuit is fabricated on the conductive layer 320, the wiring layer L9 is obtained. On the side where the second surface S2 is located, the fifth via V5 is obtained at the fifth opening H5, and the fifth via V5 connects the wiring layer L7 and the wiring layer L9.
[0141] Step (8): Build-up layer.
[0142] As Figure 11 shown, the build-up layer is performed on the stacked structure as Figure 10 shown. Among them, the build-up layer can be performed by laminating a PP layer with copper foil. Figure 11 In the embodiment as
[0143] shown, the conductive layer 410 and the conductive layer 420 can be copper foils, and the insulating layer I1 and the insulating layer I9 can be PP.
[0144] As Figure 12 shown, on the side where the first surface S1 is located, after laser drilling, the second opening H2, the third opening H3, and a plurality of fourth openings H4 are formed. Among them, the depth of the second opening H2 is greater than the depth of the third opening H3, and the depth of the third opening H3 is greater than the depth of the fourth opening H4. The second opening H2 exposes the wiring layer L5, the third opening H3 exposes the wiring layer L3, and the fourth opening H4 exposes the wiring layer L2. On the side where the second surface S2 is located, after laser drilling, the fourth opening H4 is formed, and this fourth opening H4 exposes the wiring layer L9.
[0145] Step (10): Metallization.
[0146] Specifically, the metallization includes copper plating treatment and electroplating treatment. As Figure 12 and Figure 13 shown, the stacked structure obtained after laser drilling in step (9) is subjected to copper plating treatment, and then after each opening is electroplated completely, the conductive layer 510 and the conductive layer 520 are obtained.
[0147] Step (11): Circuit etching and solder mask fabrication.
[0148] As Figure 13 andFigure 14 As shown, after etching the conductive layer 510 circuit, the wiring layer L1 is obtained. After etching the conductive layer 520 circuit, the wiring layer L10 is obtained. The first solder mask layer 23a covers the wiring layer L1, and the second solder mask layer 23b covers the wiring layer L10. In addition, the second via V2, the third via V3, and the fourth via V4 are also formed in this step.
[0149] Thus, by combining the Detach core and the multi-layer laser drilling process, the processing of the circuit board with an ultra-thin buried capacitor dielectric layer is realized, and the circuit board 20 is obtained.
[0150] It should be noted that the above first via V1b is a stepped via, and its preparation can be carried out step by step.
[0151] As Figure 15 shown in FIGS. (a) and (b) therein, the large hole P1 can be formed by laser drilling first, where the large hole P1 penetrates through the conductive layer 130 and the buried capacitor dielectric layer 110 and exposes the wiring layer L3.
[0152] As Figure 15 shown in FIG. (c) therein, at the bottom of the large hole P1, the small hole P2 can be formed by laser drilling, where the small hole P2 penetrates through the insulating layer I3 and exposes the wiring layer L4, and the size of the small hole P2 is smaller than that of the large hole P1. The small hole P2 and the large hole P1 together form the first opening H1b. As Figure 15 shown in FIG. (d) therein, after metallization (such as copper plating treatment and electroplating treatment), the conductive layer 310 and the conductive layer 320 are formed to fill the first opening H1b.
[0153] With reference to Figure 10 and Figure 15 , after circuit etching, the conductive layer 310 and the conductive layer 320 respectively form wiring layers, and the first via V1b is formed at the first opening H1b.
[0154] In summary, the circuit board of the embodiment of the present application applies the buried capacitor dielectric layer to the build-up (non-core) layer, and meets the processing and design requirements of the circuit board through the detach core process and the design of different laser hole structures, improving the convenience and usability of the PCB of the electronic device. While maintaining the electrical performance of the circuit board, the circuit board can be extremely thinned, which is beneficial to the realization of the thin and light of the electronic device and the improvement of competitiveness.
[0155] It should be noted that in the embodiments of the present application, the first via formed by laser drilling combined with metallization realizes the direct interconnection of the first buried capacitor wiring layer, the second buried capacitor wiring layer and the lower wiring layer after the buried capacitor dielectric layer is laminated with the core layer when the buried capacitor dielectric layer is applied to the build-up (non-core layer). This enables the lower wiring layer to directly interconnect with the first buried capacitor wiring layer and / or the second buried capacitor wiring layer without passing through the upper wiring layer, thereby facilitating the improvement of the signal transmission quality in the circuit board and the miniaturized design of the circuit board.
[0156] An embodiment of the present application further provides an electronic device. The electronic device includes electronic components and the above-mentioned circuit board. The electronic components are electrically connected to the circuit board. The electronic components include, but are not limited to, a power management chip, a radio frequency chip, etc. The electronic device can be, but is not limited to, consumer electronic products such as mobile phones, wearable electronic devices (such as watches, bracelets, earphones), tablet computers, laptop computers, etc. Since the electronic device includes the above-mentioned circuit board, it is thus conducive to meeting the application scenarios such as miniaturization, high density, and thinness of the electronic device.
[0157] For the circuit board of the above embodiments of the present application, since the thickness of the buried capacitor dielectric layer can be made as thin as 3μm at the thinnest, compared with PP or RCC materials, the buried capacitor dielectric layer has a more obvious effect on thinning the circuit board. Therefore, it is conducive to increasing the number of wiring layers (such as adding a power layer and a ground layer to increase the power plane) while maintaining the thinness of the circuit board. In addition, since the buried capacitor dielectric layer is a capacitive material, it is thus conducive to optimizing the AC impedance.
[0158] In summary, the circuit board of the above embodiments of the present application is conducive to realizing the optimization of DC and AC impedances under a thin and light PCB.
[0159] The above embodiments are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. A circuit board, characterized in that: It comprises a plurality of wiring layers and a plurality of insulating layers, each of the insulating layers being located between two adjacent wiring layers; The multiple insulating layers include a core insulating layer, a lower insulating layer and a buried dielectric layer, the lower insulating layer is located between the core insulating layer and the buried dielectric layer, the lower insulating layer and the buried dielectric layer are located in the build-up layer, and the buried dielectric layer has a thickness less than that of the lower insulating layer; The multiple wiring layers include a lower wiring layer, a first buried wiring layer, and a second buried wiring layer, wherein the first buried wiring layer is located on a surface of the buried dielectric layer close to the core insulating layer, and the second buried wiring layer is located on a surface of the buried dielectric layer away from the core insulating layer, the lower wiring layer is located between the core insulating layer and the first buried wiring layer, and both the first buried wiring layer and the second buried wiring layer are non-impedance wiring layers; The circuit board also includes a first via hole, which is formed by laser drilling and then metallization. The first via hole passes through the buried capacitance dielectric layer and the lower insulating layer and directly connects the second buried capacitance wiring layer, the first buried capacitance wiring layer and the lower wiring layer.
2. The circuit board according to claim 1, characterized in that: Along the direction from the lower insulating layer to the buried dielectric layer, the size of the first via hole gradually increases.
3. The circuit board according to claim 1, characterized in that: The first via hole is a stepped hole, and a size of the first via hole at the buried dielectric layer is greater than a size of the first via hole at the lower insulating layer.
4. The circuit board according to claim 1, characterized in that: The plurality of insulating layers further comprises an upper insulating layer, the upper insulating layer being located on a side of the buried dielectric layer away from the core insulating layer; The plurality of wiring layers further comprises an upper wiring layer, the upper wiring layer being located on a side of the second buried wiring layer away from the core insulating layer; The circuit board further includes a second via hole, which penetrates the upper insulating layer, the embedded dielectric layer and the lower insulating layer and directly connects the upper wiring layer and the lower wiring layer.
5. The circuit board according to claim 1, characterized in that: The plurality of insulating layers further comprises an upper insulating layer, the upper insulating layer being located on a side of the buried dielectric layer away from the core insulating layer; The plurality of wiring layers further comprises an upper wiring layer, the upper wiring layer being located on a side of the second buried wiring layer away from the core insulating layer; The circuit board further includes a third via hole, which penetrates the upper insulating layer and the buried dielectric layer and directly connects the upper wiring layer and the first buried wiring layer.
6. The circuit board according to claim 1, characterized in that: The plurality of insulating layers further comprises an upper insulating layer, the upper insulating layer being located on a side of the buried dielectric layer away from the core insulating layer; The plurality of wiring layers further comprises an upper wiring layer, the upper wiring layer being located on a side of the second buried wiring layer away from the core insulating layer; The circuit board further includes a fourth via hole, which penetrates the upper insulating layer and directly connects the second buried capacitance wiring layer and the upper wiring layer.
7. The circuit board according to claim 1, characterized in that: The circuit board further includes a fifth via hole, the fifth via hole penetrates the buried capacitance dielectric layer and the lower insulating layer and directly connects the first buried capacitance wiring layer and the lower wiring layer; and / or, The circuit board further includes a sixth via hole, which penetrates the embedded capacitance dielectric layer and directly connects the first embedded capacitance wiring layer and the second embedded capacitance wiring layer.
8. The circuit board according to claim 1, characterized in that: The total thickness of the buried dielectric layer, the first buried wiring layer and the second buried wiring layer is in a range of 9 micrometers to 42 micrometers; The thickness of the buried dielectric layer ranges from 3 microns to 22 microns; The thickness of the first buried wiring layer and the second buried wiring layer are both in a range of 3 micrometers to 18 micrometers.
9. The circuit board according to any one of claims 1 to 8, characterized in that: The lower wiring layer is located on the surface of the core insulating layer; or, at least one insulating layer is provided between the lower wiring layer and the core insulating layer.
10. An electronic device, characterized in that: include: Electronic devices; as well as The circuit board according to any one of claims 1 to 9, wherein the electronic device is electrically connected to the circuit board.