Semiconductor device
By using an atomic layer deposition process to form a uniform and void connection cushion layer within the bitline structure intervals of the semiconductor device, the challenges in the reliability and performance of semiconductor devices in the prior art are solved, and higher quality connection structures and better device performance are achieved.
Patent Information
- Application Number
- CN202422082710.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-08-27
AI Technical Summary
In the process of miniaturization of sizes, existing semiconductor devices have challenges in reliability and performance, especially in the difficulty of forming a uniform and high-quality connection structure within the intervals between bit line structures.
Through the atomic layer deposition process, a first connecting pad layer with uniform thickness is formed in the first interval between adjacent bit line structures, and a connecting pad structure with gaps inside is formed in the interval where the depth and width ratio gradually increases to improve the reliability and performance of the semiconductor device.
The high-quality connection structure is achieved in semiconductor devices, which improves the reliability and performance of the device, especially when the depth and aspect ratio is increased.
Smart Images
Figure CN222996953U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor device. Background Art
[0002] Dynamic random access memory (DRAM) is a volatile memory, which includes an array area composed of multiple memory cells and a peripheral area composed of control circuits. Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can locate each memory cell through word lines (WLs) and bit lines (BLs) that span the array area and are electrically connected to each memory cell to control the access of its data. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a semiconductor device to improve the reliability and performance of the semiconductor device.
[0004] To solve the above technical problems, the utility model provides a semiconductor device, which specifically may include:
[0005] A substrate;
[0006] A plurality of bit line structures, which are arranged on the substrate separately from each other;
[0007] Sidewall structures, which are located on the sidewalls of the bit line structures;
[0008] A plurality of contact structures, which are located between adjacent bit line structures, cover a part of the sidewalls of the sidewall structures, and define a first interval between adjacent bit line structures with the sidewall structures;
[0009] A plurality of connection pad structures, which are located on the contact structures, and the connection pad structures include:
[0010] A first connection pad layer, part of which is located in the first interval and is connected to the contact structure;
[0011] And a second connection pad layer, which is located on the first connection pad layer, wherein the bottom surface of the second connection pad layer is higher than the top surface of the bit line structure.
[0012] In some optional examples, the semiconductor device may further include:
[0013] Multiple isolation structures are located between adjacent connection pad structures and are in direct contact with the first connection cushion layer through the second connection cushion layer and the bit line structure.
[0014] In some alternative examples, the bottom surface of the isolation structure can be completely covered by the bit line structure and the first connection cushion layer.
[0015] In some alternative examples, the first connection cushion layer in the corresponding first interval can fill the first interval.
[0016] In some alternative examples, the first connection cushion layer located in the corresponding first interval can have voids.
[0017] In some alternative examples, the isolation structure is in direct contact with the voids and can extend to different depths of the voids.
[0018] In some alternative examples, the voids can be located on the vertical center line of the first connection cushion layer.
[0019] In some alternative examples, the semiconductor device may further include:
[0020] Multiple gate structures are arranged on the substrate separately from each other, and there is a second interval between adjacent gate structures;
[0021] The second connection cushion layer includes a first part located above the first interval and a second part located within the second interval. The bottom surface of the first part is higher than the top surface of the bit line structure, and the bottom surface of the second part is lower than the top surface of the gate structure.
[0022] In some alternative examples, the lower surface of the second connection cushion layer located on the first connection cushion layer is recessed in the direction close to the bottom of the isolation structure.
[0023] In some alternative examples, the semiconductor device may further include:
[0024] A silicide layer is interposed between the contact structure and the first connection cushion layer.
[0025] In the present utility model, by utilizing the film formation uniformity of the atomic layer deposition process, a first connection cushion layer with uniform thickness and corresponding connection pad structures can be formed in the first interval between adjacent bit line structures. Moreover, as the semiconductor structure size is scaled down, a first connection cushion layer with voids inside and uniform thickness and corresponding connection pad structures can be formed in the first interval between adjacent bit line structures with an increasing aspect ratio, so as to improve the reliability and performance of the semiconductor device. Description of the Drawings
[0026] Figure 1A top view of a substrate for forming a semiconductor device provided in an embodiment of the present invention.
[0027] Figures 2 to 6 A schematic structural diagram during the preparation process of a manufacturing method of a semiconductor device provided in an embodiment of the present invention.
[0028] Among them, the reference numerals are:
[0029] 100 - Substrate, 100A - First region, 100B - Second region, 101 - Trench isolation, 110 - Insulating layer, SP1 - First spacer, 120 - Bit line structure, 121 - Semiconductor layer, 122 - Barrier layer, 123 - Metal layer, 124 - Capping layer, 130 - Sidewall structure, 131 - First sidewall, 132 - Second sidewall, 140 - Contact structure, 150 - Silicide layer, 160 - Contact pad structure, 161 - First contact pad layer, 162 - Second contact pad layer, OP - Void, INT - Vertical midline of the first contact pad layer, 170 - Isolation structure, 220 - Gate structure, SP2 - Second spacer, R - Groove, 230 - First dielectric layer, 240 - Second dielectric layer. Detailed implementation manners
[0030] The semiconductor device proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways different from those described herein, and thus the present invention is not limited by the specific embodiments disclosed below.
[0031] For the convenience of understanding, the horizontal direction and the vertical direction are defined below. The horizontal direction is the direction parallel to the surface of the substrate 100; the vertical direction is the direction perpendicular to the surface of the substrate 100; and in Figures 1 to 6 the X - direction, Y - direction and Z - direction are defined, where the X - direction corresponds to the horizontal direction, the Y - direction corresponds to the vertical direction, and moreover, the horizontal direction and the vertical direction are perpendicular to each other, the X - direction and the Y - direction are perpendicular to each other, and the Z - direction is perpendicular to the plane where the X - direction and the Y - direction are located.
[0032] Please refer to Figure 1As shown, the figure is a top view of a substrate for forming a semiconductor device provided in an embodiment of the present invention. The substrate in the embodiment of the present invention may include a first region 100A and a second region 100B. In one embodiment, the first region 100A is, for example, a memory region (cell region) of the semiconductor device, and the second region 100B is, for example, a peripheral region (periphery region) of the semiconductor device, and the second region 100B surrounds the outside of the first region 100A, but is not limited thereto. Since the main inventive point of the semiconductor device provided in the embodiment of the present invention lies in the first region 100A of the substrate, those of ordinary skill in the art to which the present invention pertains can understand that most of the drawings provided in the embodiment of the present invention only show the preparation process of the corresponding semiconductor structure and its manufacturing method on the first region 100A, while a small part of the other drawings show the preparation process of the corresponding semiconductor structure and its manufacturing method on the second region 100B.
[0033] Please refer to Figure 6 , the figure is a cross-sectional view of a semiconductor device provided in an embodiment of the present invention. As Figure 6As shown, the semiconductor device includes a substrate 100, a plurality of bit line structures 120, sidewall structures 130, a plurality of contact structures 140, a silicide layer 150, a plurality of connection pad structures 160, and a plurality of isolation structures 170. Among them, the substrate 100 is any suitable substrate material well known in the art. For example, it can be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), a silicon-on-insulator substrate, or a substrate composed of other suitable materials, but not limited thereto. A plurality of trench isolations 101 are further provided in the substrate 100 to define a plurality of active areas (AA, not shown in the figure) in the substrate 100. Specifically, the trench isolation 101 may include a single layer or multiple layers of dielectric materials. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or a combination of the above materials, but not limited thereto. Exemplarily, the trench isolation 101 in this embodiment may be elongated and the long axis extends along the Y direction. In addition, an insulating layer 110 is further provided on the substrate 100. Specifically, the insulating layer 110 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but not limited thereto.
[0034] In one embodiment, a plurality of bit line structures 120 are disposed on the first region 100A separately from each other and have multiple layers of bit line material layers, such as a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and a capping layer 124 stacked in sequence from bottom to top. Among them, the material of the semiconductor layer 121 may include crystalline silicon, polysilicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 122 may include a metal, a metal silicide, or a metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the conductive layer 123 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and / or composite layer of the foregoing metal materials, but is not limited thereto. The capping layer 124 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination of the above materials, but is not limited thereto. Exemplarily, the material of the semiconductor layer 121 is polysilicon, the material of the barrier layer 122 is cobalt silicide (CoSi), the material of the conductive layer 123 is tungsten (W), and the material of the capping layer 124 is silicon nitride (SiN). It should be understood that forming the multiple layers of bit line material layers on the first region 100A of the substrate 100 further includes forming the multiple layers of bit line material layers on the second region 100B of the substrate 100, and then forming a gate structure 220 on the second region 100B of the substrate 100. It should be understood that in the embodiments of the present invention, the interval between adjacent bit line structures 120 is exemplary referred to as a first interval and is denoted by the reference numeral SP1, while the interval between adjacent gate structures 220 is referred to as a second interval and is denoted by the reference numeral SP2.
[0035] The sidewall structure 130 is located on the sidewalls of the bit line structure 120 and the gate structure 220 and may have a multi-layer structure, such as Figure 2The first sidewall 131 and the second sidewall 132 arranged in sequence along the X direction as shown, and the first sidewall 131 is in direct contact with the sidewall of the bit line structure 120 or the gate structure 220. Specifically, the first sidewall 131 and the second sidewall 132 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination of the above materials, but not limited thereto. Exemplarily, the material of the first sidewall 131 is silicon oxide (SiO2), and the material of the second sidewall 132 is silicon nitride (SiN). The contact structure 140 is located in the first interval SP1 between adjacent bit line structures 120 (in combination with Figure 2Inside the structure shown in the figure, and it is separated from the bit line structure 120 by the side wall structure 130 on both sides without direct contact, and the bottom is in direct contact with the end of the active region (substrate 100). Among them, the material of the contact structure 140 may include crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable silicon-containing semiconductor materials, but is not limited thereto. In one embodiment, the material of the contact structure 140 is phosphorus-doped silicon (SiP). The silicide layer 150 is located above the contact structure 140, and the connection pad structure 160 conformally covers the top surface of the contact structure 140, the top surface of the side wall structure 130, and the top surface of the bit line structure 120. Moreover, the connection pad structure 160 in this embodiment includes a first connection pad layer 161 and a second connection pad layer 162 stacked in sequence from bottom to top, and the bottom surface of the second connection pad layer 162 is higher than the top surface of the bit line structure 120; specifically, the first connection pad layer 161 in the connection pad structure 160 can wrap the outer surface of the bit line structure 120 and the silicide layer 150, and its top surface is higher than the top surface of the bit line structure 120, while the second connection pad layer 162 in the connection pad structure 160 covers the first connection pad layer 161. In one embodiment, the material of the first connection pad layer 161 may include conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), etc., and is preferably titanium nitride (TiN), but is not limited thereto. The material of the second connection pad layer 162 may include metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys of the foregoing materials, and / or composite layers, and is preferably tungsten (W), but is not limited thereto. Exemplarily, since the structure of the second connection pad layer 162 of the connection pad structure 160 is different in the first region 100A and the second region 100B, in order to facilitate distinction, in the embodiment of the present invention, the second connection pad layer 162 located above the corresponding first interval SP1 in the first region 100A may be defined as the first part of the second connection pad layer 162, and the second connection pad layer 162 located above the corresponding second interval SP2 in the second region 100B may be defined as the second part of the second connection pad layer 162.
[0036] It should be particularly noted that for the first region 100A, since the first connection pad layer 161 and the second connection pad layer 162 in this embodiment are formed by atomic layer deposition process, and the film formation uniformity characteristic of the atomic layer deposition process and the aspect ratio of the first interval SP1 between adjacent bit line structures 120 result in the formation of a first connection pad layer 161 with voids and uniform thickness inside the first interval SP1 between adjacent bit line structures 120. In one embodiment, as Figure 6as shown and in combination with Figure 4 , a void OP is provided within a first interval SP1 between some adjacent bit line structures 120, while no void OP is provided within the first interval SP1 between some adjacent bit line structures 120. Specifically, when no void OP is provided within the first interval SP1 between adjacent bit line structures 120, the first connection cushion layer 161 filled therein fills the first interval SP1. When a void OP is provided within the first interval SP1 between adjacent bit line structures 120, the void OP may be located on the vertical midline INT of the first connection cushion layer 161, and the void OP may be a circular structure, such as an elliptical structure, symmetrically arranged left and right along the vertical midline INT of the first connection cushion layer 161 within the corresponding first interval SP1, but not limited thereto. Moreover, since the second connection cushion layer 162 in the embodiment of the present utility model is also deposited by an atomic layer deposition process, the top surface of the first portion of the second connection cushion layer 162 with or without a void OP within the first interval SP1 between adjacent bit line structures 120 has a seam recessed towards the surface of the substrate 100 near the vertical midline INT, and the bottom surface of the first portion is higher than the top surface of the bit line structure 120, but not limited thereto.
[0037] For the second region 100B, a first dielectric layer 230 and a second dielectric layer 240 are further provided on the substrate 100, and a connection pad structure 160 is also provided. At this time, the connection pad structure 160 includes a first connection cushion layer 161 and a second connection cushion layer 162 arranged in sequence. Specifically, the first dielectric layer 230 fills the second interval SP2 between adjacent gate structures 220, and its top surface is flush with the top surface of the gate structure 220. The second dielectric layer 240 is located on the gate structure 220 and the first dielectric layer 230. The connection pad structure 160 is located within the second interval SP2 between adjacent gate structures 220 and extends to cover the top surface of the second dielectric layer 240 above the gate structure 220. Since the width of the second interval SP2 in the X direction is greater than the width of the first interval SP1 in the X direction, the first connection cushion layer 161 of the connection pad structure 160 formed by the atomic layer deposition process within the corresponding second interval SP2 has a groove R, so that the second connection cushion layer 162 of the connection pad structure 160 not only lies on the first connection cushion layer 161 but also fills the groove R. Moreover, the bottom surface of the second portion of the second connection cushion layer 162 above the second interval SP2 between adjacent gate structures 220 in the second region 100B is lower than the top surface of the gate structure 220.
[0038] The isolation structure 170 is disposed between adjacent connection pad structures 160. Among them, the isolation structure 170 located on the first region 100A passes through the second connection cushion layer 162 of the corresponding connection pad structure 160 and the bit line structure 120 and is in direct contact with the first connection cushion layer 161 of the corresponding connection pad structure 160. That is, the bottom surface of the isolation structure 170 on the first region 100A is completely covered by the corresponding bit line structure 120 and the first connection cushion layer 161. And the isolation structure 170 located on the second region 100B passes through the corresponding connection pad structure 160 and the second dielectric layer 240 and is isolated from the gate structure 220 located below it. Moreover, when there is a gap OP in the first connection cushion layer 161 within the corresponding first interval SP1 on the first region 100A, the isolation structure 170 is also in direct contact with the corresponding gap OP, and different isolation structures 170 can extend in the Y direction to different depths of the corresponding gap OP. In an embodiment, the material of the isolation structure 190 may include nitrides, such as silicon nitride, and may also include oxides, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.
[0039] It should be understood that the "co-type" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and relevance in the morphology between two or more shapes.
[0040] In order to enable those of ordinary skill in the technical field to which the present invention belongs to easily understand the manufacturing method of the semiconductor device in the embodiments of the present invention, the manufacturing method of the semiconductor device proposed by the present invention will be further described below in combination with the respective structural schematic diagrams in the preparation process of the manufacturing method.
[0041] Please refer to Figures 2 to 6 As shown, what is illustrated is the structural schematic diagram in the preparation process of the manufacturing method of the semiconductor device provided in the embodiments of the present invention.
[0042] As Figure 2 shown, and in combination with Figure 6, first, a substrate 100 is provided, and a plurality of trenches are formed in the substrate 100 by an etching process. Then, by using a deposition process, such as at least one of physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled in the plurality of trenches to form a plurality of trench isolations 101, and the plurality of trench isolations 101 define a plurality of active regions in the substrate 100. Next, an insulating layer 110 (such as a silicon oxide layer or a silicon nitride layer) is formed on the substrate 100 and a multi-layer bit line material layer is formed on the insulating layer 110. Specifically, forming the multi-layer bit line material layer may include sequentially forming a semiconductor layer 121, a barrier layer 122, a conductive layer 123 and a capping layer 124 on the substrate 100 from bottom to top. Exemplarily, the material of the semiconductor layer 121 is polysilicon, the material of the barrier layer 122 is cobalt silicide (CoSi), the material of the conductive layer 123 is tungsten (W), and the material of the capping layer 124 is silicon nitride (SiN). Subsequently, an etching process is used to sequentially etch the multi-layer structure of the bit line material layer along the Y direction, so as to form a plurality of mutually separated bit line structures 120 and a gate structure 220 on the second region 100B therein. Among them, there is a first interval SP1 between adjacent bit line structures 120, a second interval SP2 between adjacent gate structures 220, and the width of the second interval SP2 in the X direction is greater than the width of the first interval SP1 in the X direction. Then, sidewall structures 130 self-aligned with the sidewalls of the bit line structures 120 are respectively formed on both sides of the bit line structures 120; in one embodiment, the sidewall structures 130 have a multi-layer structure, for example, a first sidewall 131 (such as silicon oxide) and a second sidewall 132 (such as silicon nitride) stacked in sequence along the X direction.
[0043] such as Figure 3 shown, and in combination with Figure 6, then, using an etching process, etch downward along the Y direction on the first region 100A to form a storage node contact groove (not shown) on the outer side of the sidewall structure 130 after removing the insulating layer 110 and part of the substrate 100. Then, form a contact material layer (not shown) to comprehensively cover the substrate 100 and fill the storage node contact groove, and then use an etching or planarization process to remove the contact material layer outside the storage node contact groove until the top surfaces of the bit line structure 120 and the sidewall structure 130 are exposed, thereby obtaining contact structures 140 respectively located in the storage node contact grooves. Among them, the contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, deposit a metal material layer (not shown) on the substrate 100, and perform a silicidation process on the metal material layer and structures such as the substrate 100, so that the top of the contact structure 140 made of a silicon-containing semiconductor material, such as phosphorus-doped silicon, reacts with the metal material layer to form a silicide layer 150. Moreover, on the second region 100B, use a deposition process to sequentially form a first dielectric layer 230 that fills the second spacer SP2 between adjacent gate structures 220 and has a top surface flush with the top surface of the gate structure 220, and a second dielectric layer 240 located on the first dielectric layer 230 and the gate structure 220.
[0044] As Figures 4 to 5 shown, and in combination with Figure 6, then, by using a deposition process, a first connection pad material layer (such as titanium nitride) and a second connection pad material layer (such as tungsten metal) of the connection pad structure 160 are deposited on the first region 100A and the second region 100B of the substrate 100, and are etched to form a first connection pad layer 161 that wraps around the surfaces of the silicide layer 150 and the bit line structure 120 on the first region 100A, and a second connection pad layer 162 that fills the first spacer SP1 between adjacent bit line structures 120 and has a bottom surface higher than the top surface of the bit line structure 120. Thus, a connection pad structure 160 including the first connection pad layer 181 and the second connection pad layer 162 arranged in sequence from bottom to top is formed, and a connection pad structure 160 is formed on the second region 100B, which is composed of a first connection pad layer 161 having a groove R in the second spacer SP2 between adjacent gate structures 220 and a second connection pad layer 162 that fills the groove R and covers the first connection pad layer 161. Thereafter, a mask layer (not shown in the figure) is formed on the connection pad structure 160, wherein the mask layer has an isolation structure pattern, and using the mask layer as a mask, an isolation structure 170 arranged between adjacent connection pad structures 160 is formed on the first region 100A and the second region 100B by using an etching process and related manufacturing processes such as filling. Specifically, the isolation structure 170 located on the first region 100A passes through the second connection pad layer 162 of the corresponding connection pad structure 160 and the bit line structure 120 and is in direct contact with the first connection pad layer 161 of the corresponding connection pad structure 160, that is, the bottom surface of the isolation structure 170 on the first region 100A is completely covered by the corresponding bit line structure 120 and the first connection pad layer 161; while the isolation structure 170 located on the second region 100B passes through the corresponding connection pad structure 160 and the second dielectric layer 240 and is isolated from the gate structure 220 below it, but not limited thereto.
[0045] In summary, a semiconductor device provided by the present utility model includes: a substrate, a plurality of bit line structures disposed on the substrate separately from each other, sidewall structures located on the sidewalls of the bit line structures, a plurality of contact structures located between adjacent ones of the bit line structures, covering a part of the sidewalls of the sidewall structures and defining a first gap between adjacent ones of the bit line structures with the sidewall structures, and a plurality of connection pad structures located on the contact structures, and the connection pad structures include: a first connection pad layer located between the bit line structures, connected to the contact structures, and filling the first gap; and a second connection pad layer located on the first connection pad layer, wherein the bottom surface of the second connection pad layer is higher than the top surface of the bit line structures. In the present utility model, by utilizing the film formation uniformity of the atomic layer deposition process, a first connection pad layer with uniform thickness and corresponding connection pad structures can be formed in the first gap between adjacent bit line structures, and as the size of the semiconductor structure is miniaturized, a first connection pad layer with voids inside and uniform thickness and corresponding connection pad structures can be formed in the first gap between adjacent bit line structures with an increasing aspect ratio, so as to improve the reliability and performance of the semiconductor device.
[0046] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.
[0047] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the embodiments of the device, electronic device and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.
[0048] The above description is only a preferred embodiment of the present utility model and is not intended to limit the protection scope of the present utility model. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model are included in the protection scope of the present utility model.
Claims
1. A semiconductor device, characterized in that: include: substrate; A plurality of bit line structures are disposed on the substrate in a spaced-apart manner; A sidewall structure, located on a sidewall of the bit line structure; A plurality of contact structures are located between adjacent bit line structures, cover a portion of the sidewalls of the sidewall structure and define a first interval between adjacent bit line structures with the sidewall structure; A plurality of connection pad structures are located on the contact structure, and the connection pad structures include: A first connection pad layer, partially located in the first interval and connected to the contact structure; and a second connection pad layer, located on the first connection pad layer, wherein a bottom surface of the second connection pad layer is higher than a top surface of the bit line structure.
2. The semiconductor device according to claim 1, wherein Also includes: A plurality of isolation structures are located between adjacent connection pad structures and pass through the second connection pad layer and the bit line structure to directly contact the first connection pad layer.
3. The semiconductor device according to claim 2, wherein: The bottom surface of the isolation structure is completely covered by the bit line structure and the first connection pad layer.
4. The semiconductor device according to claim 2, wherein: The first connection pad layer in the corresponding first space fills up the first space.
5. The semiconductor device according to claim 2, wherein: The first connection pad layers located in the corresponding first spaces have gaps.
6. The semiconductor device according to claim 5, characterized in that The isolation structure is in direct contact with the void and extends to different depths of the void.
7. The semiconductor device according to claim 5, characterized in that The gap is located on the vertical midline of the first connection pad layer.
8. The semiconductor device according to claim 1, wherein Also includes: A plurality of gate structures are disposed on the substrate in a mutually separated manner, and a second interval is provided between adjacent gate structures; The second connection pad layer includes a first portion located above the first spacer and a second portion located within the second spacer, the bottom surface of the first portion is higher than the top surface of the bit line structure, and the bottom surface of the second portion is lower than the top surface of the gate structure.
9. The semiconductor device according to claim 2, wherein: The lower surface of the second connection pad layer located on the first connection pad layer is recessed toward the bottom of the isolation structure.
10. The semiconductor device according to claim 1, wherein Also includes: The silicide layer is between the contact structure and the first connection pad layer.