Reliability testing device of storage chip

Abstract

The utility model discloses a reliability testing device for a storage chip, which comprises a testing main board and a plurality of testing sub-boards, and each testing sub-board is provided with a to-be-tested storage chip with a packaging structure; the test mainboard comprises a control area, a thermal insulation area and a first connection area, the control area is provided with a control module, the first connection area is provided with a first connection module, and each test daughter board is provided with a second connection module; a first data end of the control module is electrically connected with the first connection module; the first connection module is in pluggable connection with the second connection module, and the second connection module is further electrically connected with the data end of the to-be-tested storage chip; the thermal insulation area is provided with a thermal insulation device, and the thermal insulation device isolates the control area and the test daughter board in different temperature areas of the incubator. Because the test mainboard is connected with the test daughter board in a plugging manner, only one test mainboard and one thermal insulation device are needed, the vacancy of the thermal insulation device after the test is finished is avoided, and the utilization rate and the test efficiency of the memory chip reliability test device are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip testing, and particularly relates to a reliability testing device for a storage chip. Background Art

[0002] With the increasingly widespread use of electronic storage products, as a basic module for the operation of the entire information system, the reliability of storage chips represented by non-volatile flash memory chips and related storage products has received more attention.

[0003] When various storage chips on the market need to be subjected to reliability testing during design and manufacturing, currently, a reliability testing circuit board is used for the reliability testing of storage chips. The reliability testing circuit board is provided with a test controller and a chip base for the chip under test. The chip under test is inserted into the chip base. The package structures of storage chips include Tosp48, BGA100, BGA132, BGA152, BGA154, etc., and storage chips with a main controller such as eMMC, UFS, BGA SSD, etc. Different package structures use different chip bases. The reliability testing circuit board is a PCB board. The signals of the chip under test are connected to the test controller through the wiring on the PCB board. Since the positions of the data pins of the chips under test with different package structures are different, therefore, for each type of chip under test with a different package structure, a test circuit board needs to be redesigned and manufactured.

[0004] When a storage chip is subjected to reliability testing, the storage chip on the test circuit board needs to be placed in the temperature control area of the incubator, and the rest of the test circuit board is placed in the normal temperature area. Therefore, a heat insulation device is installed on the test circuit board. Different storage chips with different packages use different test circuit boards. Due to the different package structures of the storage chips, the shapes of different test circuit boards may be different, and different heat insulation devices are installed on test circuit boards with different shapes. After the reliability testing is completed, the test circuit board and the heat insulation device matching the test circuit board may be idle, resulting in relatively low utilization rate and relatively low test efficiency of the reliability testing device for storage chips. Summary of the Utility Model

[0005] In view of this, the utility model provides a reliability testing device for a storage chip, mainly aiming to solve the problems of relatively low utilization rate and relatively low test efficiency of the existing reliability testing device for storage chips.

[0006] To solve the above problems, the present application provides a reliability testing device for a storage chip, including: a test main board and a plurality of test sub-boards, and each test sub-board is provided with a storage chip under test of a certain package structure;

[0007] The test main board includes a control area, a heat insulation area, and a first connection area. The control area is provided with a control module, and the first connection area is provided with a first connection module. Each test sub-board is provided with a second connection module. The first data terminal of the control module is electrically connected to the first connection module. The first connection module is plugged and unplugged with the second connection module, and the second connection module is also electrically connected to the data terminal of the storage chip to be tested.

[0008] The heat insulation area is provided with a heat insulation device, and the heat insulation device isolates the control area and the test sub-board in different temperature areas of the incubator.

[0009] In an embodiment of the present invention, optionally, the control area and the first connection area are arranged on both sides of the heat insulation area. Among them, the control area is arranged in the normal temperature area of the incubator, and the first connection area and the test sub-board are arranged in the temperature control area of the incubator.

[0010] In an embodiment of the present invention, optionally, the heat insulation device is provided with a through hole and a clamping component. The first connection area of the test main board passes through the through hole, the heat insulation area is clamped in the through hole, and the clamping components are respectively clamped and connected to the control area and the first connection area.

[0011] In an embodiment of the present invention, optionally, the connection line between the control module and the first connection module passes through the heat insulation area.

[0012] In an embodiment of the present invention, optionally, each test sub-board is provided with a plurality of chip bases with the same package structure. The storage chip to be tested is arranged on the chip base, and the storage chip to be tested is electrically connected to the second connection module through the chip base.

[0013] In an embodiment of the present invention, optionally, the second connection module is a gold finger arranged on the test sub-board. The first end of the gold finger is electrically connected to the storage chip to be tested through the chip base, and the second end of the gold finger is plugged and unplugged with the first connection module.

[0014] In an embodiment of the present invention, optionally, the first connection module is a connector. The first end of the connector is electrically connected to the first data terminal of the control module, and the second end of the connector is plugged and unplugged with the second connection module.

[0015] In an embodiment of the present invention, optionally, the control area is further provided with a communication module. The first data terminal of the communication module is electrically connected to the serial port data terminal of the control module, and the second data terminal of the communication module is electrically connected to the data terminal of the server.

[0016] In an embodiment of the present utility model, optionally, a data storage module and an analog-to-digital conversion module are further provided in the control area. A first data terminal of the analog-to-digital conversion module is electrically connected to a second data terminal of the control module, and a second data terminal of the analog-to-digital conversion module is electrically connected to a data terminal of the data storage module.

[0017] For a reliability test device for a storage chip provided by the present utility model, a test indication module is further provided in the control area. A data input terminal of the test indication module is electrically connected to a third data terminal of the control module.

[0018] Beneficial effects in this application: A reliability test device for a storage chip provided by the present utility model includes a test main board and a plurality of test sub-boards. A test sub-board is provided for a storage chip to be tested with different package structures. The test main board is provided with a control area, a heat insulation area, and a connection area. A first connection module on the connection area is pluggably connected to a second connection module on the test sub-board to realize the connection between the control module in the control area and the storage chip to be tested on the test sub-board. The heat insulation area is provided with a heat insulation device, and the heat insulation device isolates the control area and the test sub-board in different temperature areas of the incubator. When testing storage chips to be tested with different package structures, the test sub-board corresponding to the package structure is connected to the first connector of the test main board. Since the test main board and the test sub-board can be pluggably connected and there is only one test main board, only one heat insulation device is needed, avoiding the need for dedicated test circuit boards and heat insulation devices for the reliability tests of different storage chips, improving the utilization rate of the test main board and the heat insulation device, and improving the utilization rate and test efficiency of the reliability test device for storage chips.

[0019] The above description is only an overview of the technical solution of the present utility model. In order to be able to understand the technical means of the present utility model more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present utility model more obvious and understandable, the following specifically describes the embodiments of the present utility model. Description of the Drawings

[0020] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present utility model. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0021] Figure 1 It is a structural block diagram of a reliability test device for a storage chip according to an exemplary embodiment of the present utility model;

[0022] Figure 2The structural block diagram of the control area of a storage chip according to an exemplary embodiment of the present utility model.

[0023] Among them,

[0024] Figure 1 - Figure 2 The reference numerals are as follows: 10 - test main board; 102 - control module; 104 - heat insulation area; 106 - first connection module; 107 - communication module; 108 - test indication module; 20 - test daughter board; 202 - second connection module; 204 - storage chip under test; 30 - heat insulation device; 40 - screen display module. Detailed implementation manners

[0025] The present utility model will be described in detail below with reference to the drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present utility model and the features in the embodiments can be combined with each other.

[0026] To further elaborate on the technical means and effects adopted by the present utility model to achieve the predetermined utility model purpose, the following will describe in detail the specific implementation manners, structures, features, and effects of the present utility model application in conjunction with the drawings and preferred embodiments. In the following description, different "one embodiment" or "embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0027] The following will describe in conjunction with Figures 1 to 2 A reliability test device for a storage chip according to some embodiments of the present utility model.

[0028] In one embodiment, as Figure 1 shown, a reliability test device for a storage chip includes a test main board 10 and a plurality of test daughter boards 20, and each test daughter board 20 is provided with a storage chip under test 204 of a certain package structure;

[0029] The test main board 10 includes a control area, a heat insulation area 104, and a first connection area. The control area is provided with a control module 102, and the first connection area is provided with a first connection module 106. Each test daughter board 20 is provided with a second connection module 202; the first data terminal of the control module 102 is electrically connected to the first connection module 106; the first connection module 106 is pluggably connected to the second connection module 202, and the second connection module 202 is also electrically connected to the data terminal of the storage chip under test 204;

[0030] The heat insulation area 102 is provided with a heat insulation device 30, and the heat insulation device 30 isolates the control area and the test daughter board 20 in different temperature areas of the incubator.

[0031] Specifically, the existing reliability test circuit board uses a single PCB board. The signals of the chips to be tested are connected to the test controller through the wiring on the PCB board. Since the positions of the data pins of the chips to be tested with different package structures are different, every time a chip to be tested with a different package structure is tested, a new test circuit board needs to be redesigned and manufactured.

[0032] Moreover, the shapes of the test circuit boards for memory chips with different package structures are different, and heat insulation devices need to be customized for test circuit boards of different shapes. Once the heat insulation device is assembled, it is not convenient to disassemble and replace; it is even more impossible to be compatible with other test circuit boards of different shapes for use, resulting in some heat insulation devices being left unused.

[0033] In this application, the original integrated test circuit board is divided into a test main board and a test sub-board that can be pluggably connected to it. There is only one test main board, and different test sub-boards are designed and manufactured for memory chips with different package structures. When testing, the test sub-board corresponding to the memory chip to be tested is plugged into the test main board, avoiding the need to redesign and manufacture the entire test circuit board.

[0034] The heat insulation device is fixedly connected to the test main board, and only one heat insulation device is needed. By replacing test sub-boards with different shapes (the test functions on different test sub-boards are different, some can measure NAND, some can measure eMMC, etc.), different test requirements can be met, achieving the reuse of the same set of test circuit boards and supporting mechanical parts (such as test racks and incubators).

[0035] The test main board is divided into a control area, a heat insulation area, and a connection area. A control module is set on the control area. For example, the control module uses a general-purpose high-performance multi-channel programmable control chip FPGA, which can support the sending of working instructions and signal collection for multiple memory chips through low-level compilation. By burning different types of test software into the test main board where the control module is located, the purpose of testing different types of memory chips can be achieved. A first connection module is set on the connection area, and a memory chip to be tested and a second connection module matching the first connection module are provided on each test sub-board. The connection between the test main board and the test sub-board is realized through the pluggable connection of the first connection module and the second connection module.

[0036] The control area and the connection area are arranged on both sides of the heat insulation area, and a heat insulation device is installed in the heat insulation area, so that the control area of the test main board is fixed in the normal temperature area of the incubator, and the connection area on the test main board and the test sub-board are arranged in the temperature-controlled area of the incubator.

[0037] When testing different memory chips to be tested, the test firmware in the control module on the test main board is replaced, the test sub-board corresponding to the memory chip to be tested is plugged and unplugged from the test main board, and the test is carried out according to the test instructions issued by the host computer.

[0038] The test daughter board needs to design a test base for corresponding PCB signal transmission and corresponding package Pin pins according to the package format and communication lines of the chip under test.

[0039] In this embodiment, it should be noted that the functions implemented by the control module for the memory chip test can be realized by programs in the prior art. The technical effects achieved by this application mainly depend on the connection relationships among the modules.

[0040] Compared with the prior art, a reliability test device for a memory chip provided by the present utility model includes a test main board and a plurality of test daughter boards. A test daughter board is provided for a memory chip under test with a different package structure. The test main board is provided with a control area, a heat insulation area, and a connection area. The first connection module on the connection area is plugged and unplugged with the second connection module on the test daughter board to realize the connection between the control module in the control area and the memory chip under test on the test daughter board. The heat insulation area is provided with a heat insulation device, and the heat insulation device isolates the control area and the test daughter board in different temperature areas of the incubator. When testing memory chips under test with different package structures, the test daughter board corresponding to the package structure is connected to the first connector of the test main board. Since the test main board and the test daughter board can be plugged and unplugged, and there is only one test main board, only one heat insulation device is needed, avoiding the need for dedicated test circuit boards and heat insulation devices for the reliability tests of different memory chips, improving the utilization rate of the test main board and the heat insulation device, and improving the utilization rate and test efficiency of the memory chip reliability test device.

[0041] In one embodiment, the heat insulation device 30 is provided with through holes and clamping components. The first connection area of the test main board 10 passes through the through holes, and the heat insulation area 104 is clamped in the through holes. The clamping components are respectively clamped and connected to the control area and the first connection area.

[0042] Specifically, the heat insulation device is similar to a wall with heat insulation function (the body of the wall is made of materials with good heat insulation performance). Through holes are provided on the heat insulation wall, and the test main board passes through the through holes to the other side of the heat insulation wall, and the heat insulation area is clamped on the heat insulation wall. In order to fix the test main board, there will be clamping plates on both sides of the heat insulation wall to fix the test main board. Only one test main board is used in this application, so only one heat insulation device is used, and the heat insulation device will not be left unused.

[0043] In one embodiment, the control area and the first connection area are arranged on both sides of the heat insulation area 104. Among them, the control area is arranged in the normal temperature area of the incubator, and the first connection area and the test daughter board 20 are arranged in the temperature-controlled area of the incubator.

[0044] Specifically, the test main board penetrates to the other side of the heat insulation device, the heat insulation area is stuck on the heat insulation device, the first connection module and the test daughter board are plugged and unplugged and connected, the first connection module and the test daughter board are placed in the temperature control area of the temperature chamber, and according to the test requirements, the temperature control area is adjusted to different temperatures. The control module of the test main board is placed in the normal temperature area of the temperature chamber, and the control module and the test daughter board are isolated by the heat insulation device so as to perform high and low temperature tests on the test daughter board.

[0045] In one embodiment, the connection line between the control module 104 and the first connection module 106 passes through the heat insulation area 104.

[0046] Specifically, the heat insulation area is a blank area without component layout on the PCB board of the test main board. The connection line between the first data output pin of the control module and the first connection module is the wiring on the PCB board of the test main board. Since the control module and the first connection module are respectively arranged on both sides of the heat insulation area, the wiring between the first data output pin of the control module and the first connection module passes through the heat insulation area.

[0047] In one embodiment, each test daughter board 20 is provided with a plurality of chip bases of the same package structure, and the storage chip under test 204 is arranged on the chip base. The storage chip under test 204 is electrically connected to the second connection module 202 through the chip base.

[0048] Specifically, different types of chips and different package structures require different chip bases. Therefore, a plurality of chip bases for the chips under test of the same package structure or the same type are arranged on a test daughter board. The storage chip under test is placed on the chip base, and the data pins of the chip base are connected to the second connection module through the wiring on the PCB board.

[0049] The conventional test circuit board is of an integral structure. If it is necessary to meet the requirements of automatic loading and unloading (placing the chip into the base or pulling it out of the base through a manipulator on the workbench), only normal temperature tests can be performed; if it is necessary to meet the requirements of high and low temperature tests, the test circuit board is fixed on the corresponding heat insulation device and cannot be placed on the workbench for automatic loading and unloading, and only manual loading and unloading can be performed. When performing high and low temperature tests in this application, the test daughter board can be unplugged from the test main board, the test daughter board is placed on the workbench, and automatic loading and unloading is performed through a manipulator, improving the test efficiency.

[0050] In one embodiment, the second connection module 202 is a gold finger arranged on the test daughter board 20. The first end of the gold finger is electrically connected to the storage chip under test 204 through the chip base, and the second end of the gold finger is plugged and unplugged and connected to the first connection module 106.

[0051] Specifically, when testing a memory chip with a certain packaging structure, the chip to be tested is placed on the chip base of the corresponding test daughter board, and then the gold fingers on the test daughter board are inserted into the first connection module of the test main board. Through the docking of the gold fingers and the first connection module, the connection between the memory chip to be tested and the control module is realized.

[0052] In one embodiment, the first connection module 106 is a connector. The first end of the connector is electrically connected to the first data end of the control module 102, and the second end of the connector is pluggably connected to the second connection module 202.

[0053] Specifically, the first connection module is a high-speed connector. The high-speed connector is welded on the test main board, and the gold fingers of the test daughter board are placed in the card slot of the high-speed connector to realize the connection between the high-speed connector and the gold fingers, thereby realizing data transmission between the memory chip to be tested and the control module for functional testing of the memory chip to be tested.

[0054] In one embodiment, as Figure 2 shown, a communication module 107 is further provided in the control area. The first data end of the communication module 107 is electrically connected to the serial port data end of the control module 102, and the second data end of the communication module 107 is electrically connected to the data end of the server 40.

[0055] Specifically, the server is a host computer. The host computer is connected to the communication module on the test main board through the serial port and exchanges data with the control module through the communication module. For example, the host computer sends a start test instruction or a test instruction for a certain function to the control module or obtains the execution result from the control module, etc., so as to perform analysis and calculation based on the test execution result and output the test result.

[0056] The communication module is mainly composed of a serial communication chip and its peripheral circuits, such as an RS232 communication chip or an RS485 communication chip.

[0057] In one embodiment, as Figure 2 shown, a test indication module 108 is further provided in the control area. The data input end of the test indication module 108 is electrically connected to the second data end of the control module 102.

[0058] Specifically, the second data terminal of the control module has multiple ports, and the test indication module is composed of multiple indicator lamp circuits. One end of each indicator lamp is electrically connected to a second data port of the control module, the other end of each indicator lamp is electrically connected to one end of a current-limiting resistor, and the other end of each current-limiting resistor is connected to the negative power supply on the test main board. When the control module receives a successful function test of the storage chip to be tested, it sends a signal to the second data port corresponding to this function, and the indicator lamp connected to this second data port lights up, indicating that the function test is successful, enabling the tester to determine which function tests are successful and which are not according to the indicator lamps, and promptly finding the cause of the test failure.

[0059] It should be understood that various modifications can be made to the embodiments claimed herein. Therefore, the above specification should not be construed as limiting, but merely as an exemplification of the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present application.

[0060] The drawings included in and forming a part of this specification illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0061] These and other features of the present application will become apparent from the following description of the preferred forms of the embodiments, given by way of non-limiting example with reference to the accompanying drawings.

[0062] It should also be understood that, although the present application has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present application.

[0063] When taken in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of the present application will become more apparent in view of the following detailed description.

[0064] Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the present application and can be implemented in various ways. Well-known and / or repetitive functions and structures have not been described in detail to avoid obscuring the present application with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely as a basis and representative basis for the claims to teach those skilled in the art to use the present application in substantially any suitable detailed structure in a variety of ways.

[0065] This specification may use the phrases "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", which may each refer to one or more of the same or different embodiments according to the present application.

[0066] The above embodiments are only exemplary embodiments of the present application and are not used to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements within the essence and protection scope of the present application, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present application.

Claims

1. A reliability test device for a memory chip, characterized in that: include: A test main board and a plurality of test sub-boards, each test sub-board being provided with a memory chip to be tested in a packaging structure; The test mainboard includes a control area, a temperature-insulating area and a first connection area, the control area is provided with a control module, the first connection area is provided with a first connection module, and each of the test sub-boards is provided with a second connection module; the first data end of the control module is electrically connected to the first connection module; the first connection module is plug-in-connected to the second connection module, and the second connection module is also electrically connected to the data end of the memory chip to be tested; The temperature-isolating area is provided with a temperature-isolating device, and the temperature-isolating device isolates the control area and the test sub-board in different temperature areas of the temperature box.

2. The reliability testing device for a memory chip according to claim 1, characterized in that: The control area and the first connection area are arranged on both sides of the temperature insulation area, wherein the control area is arranged in the normal temperature area of ​​the temperature box, and the first connection area and the test sub-board are arranged in the temperature control area of ​​the temperature box.

3. The reliability testing device for a memory chip according to claim 2, characterized in that: The thermal insulation device is provided with a through hole and a clamping component, the first connection area of ​​the test mainboard passes through the through hole, the thermal insulation area is clamped in the through hole, and the clamping component is respectively clamped and connected to the control area and the first connection area.

4. The reliability testing device for a memory chip according to claim 2, characterized in that: A connection line between the control module and the first connection module passes through the temperature insulation area.

5. The reliability testing device for a memory chip according to claim 1, characterized in that: Each of the test sub-boards is provided with a plurality of chip bases with the same packaging structure, the memory chip to be tested is arranged on the chip base, and the memory chip to be tested is electrically connected to the second connection module through the chip base.

6. The reliability testing device for a memory chip according to claim 5, characterized in that: The second connection module is a gold finger disposed on the test sub-board, a first end of the gold finger is electrically connected to the memory chip to be tested through the chip base, and a second end of the gold finger is plug-in connected to the first connection module.

7. The reliability testing device for a memory chip according to any one of claims 1 to 6, characterized in that: The first connection module is a connector, a first end of the connector is electrically connected to a first data end of the control module, and a second end of the connector is pluggably connected to the second connection module.

8. The reliability testing device for a memory chip according to any one of claims 1 to 6, characterized in that: The control area is further provided with a communication module, a first data terminal of the communication module is electrically connected to a serial port data terminal of the control module, and a second data terminal of the communication module is electrically connected to a data terminal of a server.

9. The reliability testing device for a memory chip according to any one of claims 1 to 6, characterized in that: The control area is further provided with a test indication module, and a data input terminal of the test indication module is electrically connected to a second data terminal of the control module.

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