Semiconductor structure

Abstract

The utility model relates to a semiconductor structure, the semiconductor structure comprises a substrate, a chip, a heat dissipation structure and a first packaging layer, the chip is arranged on one side of the substrate in the thickness direction, the heat dissipation structure is arranged on one side, away from the substrate, of the chip, and the outer contour of the substrate covers and exceeds the orthographic projection of the heat dissipation structure on the substrate. The first packaging layer is arranged on the side, away from the substrate, of the chip, the first packaging layer covers the chip and the substrate, the first packaging layer comprises a first opening, and the heat dissipation structure is exposed to the first opening. According to the semiconductor structure, the heat dissipation capability of the semiconductor structure can be improved, and efficient work of the semiconductor structure is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure. Background Art

[0002] A semiconductor structure generally includes a chip capable of realizing a preset function, a packaging shell, and other parts. The packaging shell plays a key role in aspects such as the performance, reliability of the semiconductor structure, and connection with an external system.

[0003] When a semiconductor structure is working, heat is generated. If the heat cannot be dissipated in time, the continuously rising temperature may cause the performance of the semiconductor structure to decline, fail, or even be damaged. In order to ensure the reliability of the normal operation of the semiconductor structure, how to dissipate heat from the semiconductor structure well is an issue that the industry has been researching. Utility Model Content

[0004] The semiconductor structure provided by the embodiments of this application can improve the heat dissipation ability of the semiconductor structure and ensure the efficient operation of the semiconductor structure.

[0005] In a first aspect, the embodiments of this application provide a semiconductor structure, including:

[0006] A substrate;

[0007] A chip disposed on one side of the substrate in the thickness direction,

[0008] A heat dissipation structure disposed on the side of the chip facing away from the substrate, and the outer contour of the substrate covers and extends beyond the orthographic projection of the heat dissipation structure on the substrate;

[0009] A first encapsulation layer disposed on the side of the chip facing away from the substrate, the first encapsulation layer covers the chip and the substrate and includes a first opening, and the heat dissipation structure is exposed at the first opening.

[0010] In some embodiments, it further includes a frame structure, the frame structure includes a first frame and a second frame that are separately disposed, the chip includes a first pole and a second pole that are connected to each other, the first frame is connected to the first pole, and the second frame is connected to the second pole.

[0011] In some embodiments, the projected area of the first pole in the thickness direction of the substrate is larger than the projected area of the second pole in the thickness direction of the substrate;

[0012] The projection of the heat dissipation structure in the thickness direction of the substrate and the projection of the first pole in the thickness direction of the substrate are overlapped.

[0013] In some embodiments, the first frame includes a first connecting portion, which is stacked and connected to the first pole along the thickness direction of the substrate, and the projection of the heat dissipation structure in the thickness direction of the substrate is inside the projection of the first connecting portion in the thickness direction of the substrate, and the heat dissipation structure is stacked and connected to the first connecting portion.

[0014] In some embodiments, the first frame further includes a first lead-out portion connected to the first connecting portion, and one end of the first lead-out portion extends to the outside of the first encapsulation layer;

[0015] One end of the second frame extends to the outside of the first packaging layer, and the first lead-out portion and a portion of the second frame are spaced apart along a width direction of the substrate.

[0016] In some embodiments, a pin structure is further included, one end of the pin structure is connected to the substrate, and the other end of the pin structure extends to the outside of the first packaging layer;

[0017] A portion of the lead structure outside the first packaging layer, the first lead portion, and a portion of the second frame outside the first packaging layer are arranged in parallel with each other at intervals along a width direction of the substrate.

[0018] In some embodiments, a second packaging layer is further included. The second packaging layer is disposed on a side of the substrate facing away from the chip. The second packaging layer includes a second opening. At least a portion of the substrate is exposed to the second opening.

[0019] In some embodiments, a connection packaging layer is further included, wherein the connection packaging layer is disposed on the peripheral side of the substrate, and the connection packaging layer connects the first packaging layer and the second packaging layer.

[0020] In some embodiments, a projection of the chip in a thickness direction of the substrate overlaps with a projection of the first opening in a thickness direction of the substrate;

[0021] And / or, a projection of the chip in the thickness direction of the substrate overlaps with a projection of the second opening in the thickness direction of the substrate.

[0022] In some embodiments, the substrate includes a first insulating layer, a first metal layer, and a second insulating layer connected to each other in sequence along the thickness direction thereof, and the chip is disposed on one side of the first insulating layer or the second insulating layer along the thickness direction of the substrate;

[0023] And / or, the heat dissipation structure includes a third insulating layer, a second metal layer and a fourth insulating layer which are interconnected in sequence along the thickness direction of the substrate, and the chip is arranged on one side of the third insulating layer or the fourth insulating layer along the thickness direction of the substrate.

[0024] According to the semiconductor structure provided by the present application, it includes a substrate as the basis of the overall structure, a chip as the core of the overall structure, a heat dissipation structure for dissipating heat from the chip, and a first packaging layer for packaging the overall structure. The chip is arranged on one side of the substrate in the thickness direction, and the heat dissipation structure is arranged on the side of the chip away from the substrate. The heat dissipation structure is used to dissipate the heat generated by the chip when it is working from the side away from the substrate. At the same time, the substrate can not only serve as the basis of the overall structure in the semiconductor structure, but also as a heat dissipation element for the chip, and the heat generated by the chip when it is working is dissipated from the side away from the heat dissipation structure. Under the premise of achieving packaging protection, the first packaging layer considers the heat dissipation capacity of the semiconductor structure, forms a first opening on the first packaging layer, and the heat dissipation structure is exposed to the first opening. During the operation of the semiconductor structure, the heat generated by the chip is transferred to the heat dissipation structure, and the heat dissipation is performed by the heat dissipation structure; exposing the heat dissipation structure to the first opening can enable all the heat transferred from the chip to the heat dissipation structure to be directly transferred from the first opening to the external environment, thereby improving the heat dissipation capacity of the semiconductor structure and ensuring the efficient operation of the semiconductor structure. 。 BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0026] Figure 1 A first internal structure schematic diagram of a semiconductor structure provided in some embodiments of the present application;

[0027] Figure 2 A schematic diagram of a structure on one side of a first packaging layer on a semiconductor structure provided in some embodiments of the present application;

[0028] Figure 3 A second internal structure schematic diagram of a semiconductor structure provided in some embodiments of the present application;

[0029] Figure 4 A schematic structural diagram of a substrate in a semiconductor structure provided in some embodiments of the present application;

[0030] Figure 5 A schematic diagram of a chip structure in a semiconductor structure provided in some embodiments of the present application;

[0031] Figure 6 A schematic diagram of the matching relationship between a substrate and a chip in a semiconductor structure provided in some embodiments of the present application;

[0032] Figure 7 Schematic diagram of the frame structure in a semiconductor structure provided by some embodiments of the present application;

[0033] Figure 8 Schematic diagram of the heat dissipation structure in a semiconductor structure provided by some embodiments of the present application;

[0034] Figure 9 Schematic diagram of one side of the second encapsulation layer on a semiconductor structure provided by some embodiments of the present application;

[0035] Figure 10 Schematic diagram of the structure of the chip and the substrate in the thickness direction in a semiconductor structure provided by some embodiments of the present application.

[0036] Marking description:

[0037] 10. Substrate; 11. First insulating layer; 12. First metal layer; 13. Second insulating layer;

[0038] 20. Chip; 21. First pole; 22. Second pole;

[0039] 30. Heat dissipation structure;

[0040] 40. First encapsulation layer; 41. First opening;

[0041] 50. Frame structure; 51. First frame; 511. First connection part; 512. First lead-out part; 52. Second frame; 521. Second connection part; 522. Second lead-out part;

[0042] 60. Pin structure;

[0043] 70. Second encapsulation layer; 71. Second opening;

[0044] 80. Connection encapsulation layer;

[0045] H1. First solder paste layer; H2. Second solder paste layer; H3. Third solder paste layer; H4. Fourth solder paste layer; H5. Fifth solder paste layer;

[0046] X. Width direction; Z. Thickness direction.

[0047] In the drawings, like parts are denoted by like reference numerals. The drawings are not drawn to actual scale. Detailed implementation manners

[0048] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than limiting the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0049] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0050] A semiconductor structure generally includes a chip capable of realizing a preset function and a package housing and other parts. The package housing plays a key role in aspects such as the performance, reliability of the semiconductor structure, and connection with an external system.

[0051] When the semiconductor structure is working, heat will be generated. If the heat cannot be dissipated in time, the continuously rising temperature may cause the performance of the semiconductor structure to decline, fail or even be damaged. In order to ensure the reliability of the normal operation of the semiconductor structure, how to dissipate heat from the semiconductor structure well is a problem that the industry has been researching.

[0052] In view of this, in a first aspect, please refer to Figures 1 to 3 , an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes a substrate 10, a chip 20, a heat dissipation structure 30, and a first encapsulation layer 40. Among them, the chip 20 is disposed on one side in the thickness direction Z of the substrate 10, the heat dissipation structure 30 is disposed on the side of the chip 20 facing away from the substrate 10, and the outer contour of the substrate 10 covers and exceeds the orthographic projection of the heat dissipation structure 30 on the substrate 10. The first encapsulation layer 40 is disposed on the side of the chip 20 facing away from the substrate 10, the first encapsulation layer 40 covers the chip 20 and the substrate 10, and the first encapsulation layer 40 includes a first opening 41, and the heat dissipation structure 30 is exposed to the first opening 41.

[0053] The semiconductor structure provided by this application includes a substrate 10 that serves as the foundation of the overall structure, a chip 20 that is the core of the overall structure, a heat dissipation structure 30 for dissipating heat from the chip 20, and a first encapsulation layer 40 for encapsulating the overall structure.

[0054] Specifically, the chip 20 is disposed on one side in the thickness direction Z of the substrate 10, and the heat dissipation structure 30 is disposed on the side of the chip 20 facing away from the substrate 10. It can be understood that the substrate 10 serves as the foundation of the overall structure, and the projected area of the substrate 10 in its thickness direction Z can be larger than the projected area of the chip 20 in the thickness direction Z of the substrate 10. That is to say, when the chip 20 is connected to the substrate 10, the volume of the chip 20 is smaller than the volume of the substrate 10, which is convenient for the installation of the chip 20. The heat dissipation structure 30 is on the side of the chip 20 facing away from the substrate 10, and the heat dissipation structure 30 is used to dissipate the heat generated when the chip 20 operates from the side facing away from the substrate 10, thereby improving the heat dissipation capacity of the semiconductor structure and ensuring the normal and efficient operation of the semiconductor structure.

[0055] Preferably, the substrate 10 in the semiconductor structure can not only serve as the foundation of the overall structure but also as a heat dissipation element for the chip 20, dissipating the heat generated when the chip 20 operates from the side facing away from the heat dissipation structure 30. When the substrate 10 and the heat dissipation structure 30 dissipate heat from the chip 20 simultaneously, the substrate 10 and the heat dissipation mechanism are respectively on both sides of the chip 20, which can improve the heat dissipation capacity of the entire semiconductor structure. In this case, the structures of the substrate 10 and the heat dissipation structure 30 can be exactly the same.

[0056] When connecting the chip 20 to the substrate 10 and connecting the heat dissipation structure 30 to the chip 20, soldering can be used for connection to ensure the strength and stability after connection. Specifically, please refer to Figures 1 to 4 , during the process of connecting the chip 20 to the substrate 10, a suitable position on the substrate 10 can be selected to dot or brush a first solder paste layer H1, cover the chip 20 on the first solder paste layer H1, and connect the chip 20 and the substrate 10 by soldering. The process of connecting the heat dissipation structure 30 to the chip 20 is exactly the same as the process of connecting the chip 20 to the substrate 10, and will not be elaborated here.

[0057] Considering the different functions of the substrate 10 and the heat dissipation structure 30 in the entire semiconductor structure, on the premise of ensuring that the heat dissipation structure 30 efficiently dissipates heat from the chip 20 and reducing production costs, the volume of the heat dissipation structure 30 can be set according to the size of the chip 20. That is to say, the heat dissipation structure 30 can have exactly the same structure as the substrate 10, but their volume sizes are different. In this application, taking into account both the heat dissipation efficiency and production costs, the outer contour of the substrate 10 covers and extends beyond the orthographic projection of the heat dissipation structure 30 on the substrate 10. Through the above setting, it is also convenient to connect the entire heat dissipation structure 30 to the chip 20 or the substrate 10.

[0058] Specifically, when the projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 does not exceed the projection of the chip 20 in the thickness direction Z of the substrate 10, the heat dissipation structure 30 can be directly connected to the chip 20. In this case, since the projected area of the chip 20 is larger than the projected area of the heat dissipation structure 30, it is convenient for technicians to operate when applying solder paste by dotting or brushing. Or, when the projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 exceeds the projection of the chip 20 in the thickness direction Z of the substrate 10, the heat dissipation structure 30 can be connected to the substrate 10. Since the area of the substrate 10 is larger than the projected area of the heat dissipation structure 30 in the thickness direction Z of the substrate 10, technicians can also conveniently apply solder paste by dotting or brushing on the substrate 10 to connect the heat dissipation structure 30 to the substrate 10.

[0059] In addition, the first encapsulation layer 40 is used to encapsulate the semiconductor structure to a certain extent and provide a certain degree of protection for the semiconductor structure. The first encapsulation layer 40 is disposed on the side of the chip 20 facing away from the substrate 10, and the first encapsulation layer 40 covers the chip 20 and the substrate 10. Focusing the encapsulation of the first encapsulation layer 40 on the side of the chip 20 facing away from the substrate 10 can improve the connection stability between the chip 20 and the substrate 10.

[0060] At the same time, on the premise of realizing encapsulation protection, considering the heat dissipation ability of the semiconductor structure, a first opening 41 is formed on the first encapsulation layer 40, and the heat dissipation structure 30 is exposed to the first opening 41. During the operation of the semiconductor structure, the heat generated by the chip 20 is transferred to the heat dissipation structure 30, and the heat dissipation structure 30 dissipates the heat. The setting of the first opening 41 enables some heat to be directly dissipated to the external environment through the first opening 41 without passing through the first encapsulation layer 40, improving the heat dissipation efficiency of the semiconductor structure. Exposing the heat dissipation structure 30 to the first opening 41 enables all the heat transferred from the chip 20 to the heat dissipation structure 30 to be directly transferred to the external environment through the first opening 41, improving the heat dissipation ability of the semiconductor structure and ensuring the efficient operation of the semiconductor structure.

[0061] In summary, in the embodiments of the present application, the semiconductor structure includes a substrate 10 serving as the basis of the overall structure, a chip 20 serving as the core of the overall structure, a heat dissipation structure 30 for dissipating heat from the chip 20, and a first encapsulation layer 40 for encapsulating the overall structure. The chip 20 is disposed on one side in the thickness direction Z of the substrate 10, and the heat dissipation structure 30 is disposed on the side of the chip 20 facing away from the substrate 10. The heat dissipation structure 30 is used to dissipate the heat generated when the chip 20 operates from the side facing away from the substrate 10. At the same time, the substrate 10 can not only serve as the basis of the overall structure in the semiconductor structure, but also serve as a heat dissipation element for the chip 20 to dissipate the heat generated when the chip 20 operates from the side facing away from the heat dissipation structure 30. On the premise of realizing encapsulation protection, considering the heat dissipation capacity of the semiconductor structure, a first opening 41 is formed on the first encapsulation layer 40, and the heat dissipation structure 30 is exposed to the first opening 41. During the operation of the semiconductor structure, the heat generated by the chip 20 is transferred to the heat dissipation structure 30, and the heat dissipation structure 30 dissipates the heat. Exposing the heat dissipation structure 30 to the first opening 41 can enable all the heat transferred from the chip 20 to the heat dissipation structure 30 to be directly transferred to the external environment through the first opening 41, improving the heat dissipation capacity of the semiconductor structure and ensuring the efficient operation of the semiconductor structure.

[0062] In some embodiments, referring to Figures 1 to 5 , the semiconductor structure further includes a frame structure 50. The frame structure 50 includes a first frame 51 and a second frame 52 that are separately provided. The chip 20 includes a first pole 21 and a second pole 22 that are connected to each other. The first frame 51 is connected to the first pole 21, and the second frame 52 is connected to the second pole 22.

[0063] During the actual operation of the semiconductor structure, it is necessary to electrically connect the chip 20 to the outside of the semiconductor structure to connect and conduct with the rest of the structure. Exemplarily, the semiconductor structure usually needs to be connected to a circuit board to complete its specific work. In the related art, wires made of aluminum are usually used to connect the chip 20 and the external pins of the semiconductor structure. During the production process, the processes are numerous and the connection with the chip 20 is not stable. In this embodiment, it is directly connected to the chip 20 by setting the frame structure 50, and the electricity of the chip 20 is led out to the outside of the semiconductor structure.

[0064] Specifically, the chip 20 usually includes a first pole 21 and a second pole 22 that are connected to each other. Correspondingly, the frame structure 50 in the present application includes a first frame 51 and a second frame 52. The first frame 51 is connected to the first pole 21 of the chip 20, and the second frame 52 is connected to the second pole 22 of the chip 20. The connection between the frame structure 50 and the chip 20 is also soldered by means of dotting or brushing solder paste. Considering the electrical conductivity of the frame structure 50, the frame structure 50 is preferably made of copper.

[0065] To avoid the generation of internal stress due to misaligned welding positions during the connection of the frame structure 50 to the chip 20, which may affect the connection between the two parts of the frame structure 50 and the two levels on the chip 20, the first frame 51 and the second frame 52 are set in a split form, such that the connection between the first frame 51 and the first pole 21 and the connection between the second frame 52 and the second pole 22 do not interfere with each other. During the actual connection process, please refer to Figures 1 to 6 , the second solder paste layer H2 can be dotted or brushed on the first pole 21, and the first frame 51 is connected to the first pole 21 through the second solder paste layer H2; the third solder paste layer H3 can be dotted or brushed on the second pole 22, and the second frame 52 is connected to the second pole 22 through the third solder paste layer H3.

[0066] In some embodiments, the projected area of the first pole 21 in the thickness direction Z of the substrate 10 is larger than the projected area of the second pole 22 in the thickness direction Z of the substrate 10. The projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 overlaps with the projection of the first pole 21 in the thickness direction Z of the substrate 10.

[0067] In the chip 20 provided in the embodiment of the present application, the projected area of the first pole 21 on the chip 20 in the thickness direction Z of the substrate 10 is larger than the projected area of the second pole 22 in the thickness direction Z of the substrate 10. That is to say, the circuit structure on the first pole 21 is complex and undertakes more work, and the heat generated during its operation is relatively large. Relatively speaking, the heat generated by the second pole 22 during operation is smaller.

[0068] To specifically improve the heat dissipation efficiency of the heat dissipation structure 30 for the chip 20, the positions of the heat dissipation structure 30 and the first pole 21 are made to correspond to each other, so that the projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 overlaps with the projection of the first pole 21 in the thickness direction Z of the substrate 10, thereby enabling the heat dissipation structure 30 to efficiently dissipate the heat generated by the first pole 21. While reducing the area of the heat dissipation structure 30 to control costs, by utilizing the structural characteristics of the chip 20, the heat dissipation structure 30 is arranged on the first pole 21 where more heat is generated to ensure the heat dissipation ability for the chip 20.

[0069] In some embodiments, please refer to Figure 7 , the first frame 51 includes a first connecting portion 511, and the first connecting portion 511 is stacked and connected to the first pole 21 along the thickness direction Z of the substrate 10. The projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 is inside the projection of the first connecting portion 511 in the thickness direction Z of the substrate 10, and the heat dissipation structure 30 is stacked and connected to the first connecting portion 511.

[0070] Since the area of the first pole 21 on the chip 20 is relatively large, the first connecting portion 511 in the first frame 51 is correspondingly provided. The first connecting portion 511 is stacked and connected to the first pole 21 along the thickness direction Z of the substrate 10 to ensure the connection stability between the first frame 51 and the first pole 21. At the same time, in order to facilitate the alignment of the heat dissipation structure 30 with the first pole 21, the heat dissipation structure 30 is connected to the first connecting portion 511.

[0071] Furthermore, in order to facilitate the connection of the heat dissipation structure 30 to the first connecting portion 511 and reduce the projected area of the heat dissipation structure 30 in the thickness direction Z of the substrate 10, so that the projection of the heat dissipation structure 30 in the thickness direction Z of the substrate 10 is inside the projection of the first connecting portion 511 in the thickness direction Z of the substrate 10, the heat dissipation structure 30 is stacked and connected to the first connecting portion 511.

[0072] Similarly, please refer to Figures 1 to 8 , in order to ensure the connection stability between the heat dissipation structure 30 and the first connecting portion 511, a fourth solder paste layer H4 is dotted or brushed on the first connecting portion 511, and the heat dissipation structure 30 is soldered to the first connecting portion 511 through the fourth solder paste layer H4.

[0073] In some embodiments, please refer to Figures 1 to 7 , the first frame 51 further includes a first lead-out portion 512 connected to the first connecting portion 511, and one end of the first lead-out portion 512 extends outside the first encapsulation layer 40. One end of the second frame 52 extends outside the first encapsulation layer 40, and the first lead-out portion 512 and a part of the second frame 52 are arranged at intervals along the width direction X of the substrate 10.

[0074] The first frame 51 directly leads out the electrical property of the first pole 21 on the chip 20 to the outside of the first encapsulation layer 40. Specifically, the first frame 51 includes a first lead-out portion 512 connected to the first connecting portion 511, and one end of the first lead-out portion 512 extends outside the first encapsulation layer 40. The first encapsulation layer 40 only encapsulates the first connecting portion 511 and a part of the first lead-out portion 512, and one end of the first lead-out portion 512 outside the first encapsulation layer 40 is used to connect to other structures.

[0075] The second frame 52 also directly leads out the electrical property of the second pole 22 on the chip 20 to the outside of the first encapsulation layer 40. One end of the second frame 52 is connected to the second pole 22, and the other end of the second frame 52 extends to the outside of the first encapsulation layer 40. The part of the second frame 52 outside the first encapsulation layer 40 is spaced apart from the first lead-out part 512 in the width direction X of the substrate 10. The part of the second frame 52 outside the first encapsulation layer 40 is used to connect with other structures. The chip 20 is connected to other structures through the first frame 51 and the second frame 52 to form a complete circuit for the chip 20 to work, enabling the chip 20 to achieve complete operation. At the same time, by leading out the electrical property of the chip 20 through the frame structure 50, the connection stability between the chip 20 and other structures can be improved, ensuring the reliability of the chip 20 during operation.

[0076] Based on the first frame 51 and the second frame 52 which are separately arranged and connected respectively, the first frame 51 is connected to the first pole 21, and the heat dissipation structure 30 is connected to the first frame 51, which can cut off the influence of the connection stability of the second frame 52 on the heat dissipation structure 30. Compared with setting the frame structure 50 as a whole and then connecting the heat dissipation structure 30 at the position corresponding to the first pole 21, the setting stability of the heat dissipation structure 30 is affected by the entire frame structure 50. If there is a certain connection stress in the frame structure 50 itself, it will directly affect the connection stability of the heat dissipation structure 30. The structural setting in this application is beneficial to reducing the influence of the heat dissipation structure 30 by the remaining structures, improving the connection stability of the heat dissipation structure 30, and ensuring the efficient heat dissipation of the heat dissipation structure 30 to the chip 20.

[0077] In some embodiments, please refer to Figures 1 to 7 , the semiconductor structure further includes a pin structure 60. One end of the pin structure 60 is connected to the substrate 10, and the other end of the pin structure 60 extends to the outside of the first encapsulation layer 40. The part of the pin structure 60 outside the first encapsulation layer 40, the first lead-out part 512, and the part of the second frame 52 outside the first encapsulation layer 40 are arranged in parallel along the width direction X of the substrate 10.

[0078] To improve the adaptability of the semiconductor structure, the semiconductor structure provided in this application further includes a pin structure 60. The pin structure 60 and the first frame 51 and the second frame 52 form three pins outside the first encapsulation layer 40 to be adapted to other semiconductor products in the field.

[0079] Specifically, one end of the pin structure 60 is connected to the substrate 10, and the other end of the pin structure 60 extends to the outside of the first encapsulation layer 40. For the connection between the pin structure 60 and the substrate 10, a fifth solder paste layer H5 can be dotted or brushed on the substrate 10, and the pin structure 60 is soldered to the substrate 10 through the fifth solder paste layer H5.

[0080] Considering that the area of the first pole 21 on the chip 20 is larger than that of the second pole 22, the first lead-out portion 512 on the first frame 51 and the second frame 52 are respectively arranged on both sides in the width direction X of the substrate 10, and the pin structure 60 is arranged between the first lead-out portion 512 and the second frame 52. The part of the pin structure 60 outside the first encapsulation layer 40 and the parts of the first lead-out portion 512 and the second frame 52 outside the first encapsulation layer 40 are arranged in parallel along the width direction X of the substrate 10.

[0081] In some embodiments, the second frame 52 includes a second connection portion 521 and a second lead-out portion 522 that are connected to each other. At least part of the second connection portion 521 is stacked and connected to the second pole 22 of the chip 20 along the thickness direction Z of the substrate 10. One end of the second lead-out portion 522 is connected to the second connection portion 521, and the other end of the second lead-out portion 522 extends outside the first encapsulation layer 40. The second connection portion 521 has an L-shaped structure, and the second connection portion 521 and the second lead-out portion 522 as a whole have a Z-shaped structure. In the width direction X of the substrate 10, the second lead-out portion 522 is located between the first lead-out portion 512 and the second connection portion 521.

[0082] In some embodiments, please refer to Figures 1 to 9 , the semiconductor structure further includes a second encapsulation layer 70. The second encapsulation layer 70 is arranged on the side of the substrate 10 facing away from the chip 20. The second encapsulation layer 70 includes a second opening 71, and at least part of the substrate 10 is exposed to the second opening 71.

[0083] Considering the convenience of the encapsulation process, the second encapsulation layer 70 is formed on the side of the substrate 10 facing away from the chip 20. The first encapsulation layer 40 and the second encapsulation layer 70 are respectively on both sides in the thickness direction Z of the semiconductor structure, so as to be suitable for encapsulation by an encapsulation mold. In some embodiments, the semiconductor structure further includes a connecting encapsulation layer 80. The connecting encapsulation layer 80 is arranged on the peripheral side of the substrate 10. The connecting encapsulation layer 80 connects the first encapsulation layer 40 and the second encapsulation layer 70 to form protection for the side surface of the semiconductor structure.

[0084] In order to facilitate the heat generated by the chip 20 to be dissipated from one side of the substrate 10, a second opening 71 is formed on the second encapsulation layer 70, and at least part of the substrate 10 is exposed to the second opening 71, so that the heat generated by the chip 20 is directly dissipated from the second opening 71 after being transferred to the substrate 10. Specifically, the substrate 10 includes a body portion and an edge portion connected to the peripheral side of the body portion along the thickness direction Z of the substrate 10. The projection of the chip 20 in the thickness direction Z of the substrate 10 is inside the projection of the body portion in the thickness direction Z of the substrate 10. The chip 20 is connected to one side of the body portion along the thickness direction Z of the substrate 10, and the body portion is exposed to the second opening 71.

[0085] In some embodiments, the projection of the chip 20 in the thickness direction Z of the substrate 10 overlaps with the projection of the first opening 41 in the thickness direction Z of the substrate 10, and / or the projection of the chip 20 in the thickness direction Z of the substrate 10 overlaps with the projection of the second opening 71 in the thickness direction Z of the substrate 10.

[0086] In order to enable the heat generated by the chip 20 to dissipate quickly, by setting the positional relationship of the first opening 41 and the second opening 71 relative to the chip 20, the positions of the chip 20 in the thickness direction Z of the substrate 10 correspond to those of the first opening 41 and the second opening 71.

[0087] The relative positional relationship between the chip 20 and the first opening 41 is specifically manifested in that the projection of the chip 20 in the thickness direction Z of the substrate 10 overlaps with the projection of the first opening 41 in the thickness direction Z of the substrate 10. Based on the heat dissipation structure 30 being exposed to the first opening 41, the middle part of the first pole 21 on the chip 20, the middle part of the heat dissipation structure 30, and the middle part of the first opening 41 can be made to correspond to each other in the thickness direction Z of the substrate 10.

[0088] The relative positional relationship between the chip 20 and the second opening 71 is specifically manifested in that the projection of the chip 20 in the thickness direction Z of the substrate 10 overlaps with the projection of the second opening 71 in the thickness direction Z of the substrate 10. Based on the volume of the substrate 10 being larger than the volume of the chip 20, it is preferred that the size of the second opening 71 is larger than the size of the chip 20, and the chip 20 is completely inside the projection of the second opening 71 in the thickness direction Z of the substrate 10.

[0089] In some embodiments, please refer to Figures 1 to 10 , on the basis of realizing heat dissipation, the substrate 10 and the heat dissipation structure 30 provide better protection for the chip 20. The substrate 10 and the heat dissipation structure 30 at least include an insulating layer to achieve insulation between the chip 20 and the external environment, reduce the risk of short - circuit of the chip 20, and ensure the normal operation of the chip 20.

[0090] Specifically, the substrate 10 sequentially includes a first insulating layer 11, a first metal layer 12, and a second insulating layer 13 that are connected to each other along its thickness direction Z. The chip 20 is disposed on one side of the first insulating layer 11 or the second insulating layer 13 along the thickness direction Z of the substrate 10. Among them, the first insulating layer 11 is preferably set as a ceramic layer, the first metal layer 12 is preferably made of copper, the second insulating layer 13 is preferably set as a ceramic layer, and the first insulating layer 11, the first metal layer 12, and the second insulating layer 13 form a ceramic double-sided copper-clad substrate. It should be noted that the ceramic double-sided copper-clad substrate is preferably integrally formed, that is, the first insulating layer 11, the first metal layer 12, and the second insulating layer 13 are directly formed and connected without any other welding layers. The method of directly forming the first insulating layer 11, the first metal layer 12, and the second insulating layer 13 can avoid heat passing through the welding layer, accelerate the heat dissipation speed, and improve the heat dissipation efficiency of the substrate 10 for the chip 20 compared with the method of connecting the first insulating layer 11, the first metal layer 12, and the second insulating layer 13 through a welding layer.

[0091] Similarly, the heat dissipation structure 30 sequentially includes a third insulating layer, a second metal layer, and a fourth insulating layer that are connected to each other along the thickness direction Z of the substrate 10. The chip 20 is disposed on one side of the third insulating layer or the fourth insulating layer along the thickness direction Z of the substrate 10. Among them, the third insulating layer is preferably set as a ceramic layer, the second metal layer is preferably made of copper, the fourth insulating layer is preferably set as a ceramic layer, and the third insulating layer, the second metal layer, and the fourth insulating layer form a ceramic double-sided copper-clad substrate. It should be noted that the ceramic double-sided copper-clad substrate is preferably integrally formed, that is, the third insulating layer, the second metal layer, and the fourth insulating layer are directly formed and connected without any other welding layers. The method of directly forming the third insulating layer, the second metal layer, and the fourth insulating layer can avoid heat passing through the welding layer, accelerate the heat dissipation speed, and improve the heat dissipation efficiency of the heat dissipation structure 30 for the chip 20 compared with the method of connecting the third insulating layer, the second metal layer, and the fourth insulating layer through a welding layer.

[0092] Although the present invention has been described with reference to the preferred embodiments, various improvements can be made to it and components therein can be replaced with equivalents without departing from the scope of the present invention. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A chip is arranged on one side of the substrate in the thickness direction. A heat dissipation structure is arranged on a side of the chip facing away from the substrate, and an outer contour of the substrate covers and exceeds an orthographic projection of the heat dissipation structure on the substrate; The first packaging layer is arranged on a side of the chip away from the substrate. The first packaging layer covers the chip and the substrate and comprises a first opening. The heat dissipation structure is exposed in the first opening.

2. The semiconductor structure according to claim 1, characterized in that: It also includes a frame structure, which includes a first frame and a second frame that are separately arranged. The chip includes a first pole and a second pole that are connected to each other. The first frame is connected to the first pole, and the second frame is connected to the second pole.

3. The semiconductor structure according to claim 2, characterized in that: The projection area of ​​the first pole in the thickness direction of the substrate is larger than the projection area of ​​the second pole in the thickness direction of the substrate; A projection of the heat dissipation structure in the thickness direction of the substrate is overlapped with a projection of the first pole in the thickness direction of the substrate.

4. The semiconductor structure according to claim 3, characterized in that: The first frame includes a first connecting portion, which is stacked and connected to the first pole along the thickness direction of the substrate, the projection of the heat dissipation structure in the thickness direction of the substrate is inside the projection of the first connecting portion in the thickness direction of the substrate, and the heat dissipation structure is stacked and connected to the first connecting portion.

5. The semiconductor structure according to claim 4, characterized in that: The first frame further includes a first lead-out portion connected to the first connecting portion, one end of the first lead-out portion extending to the outside of the first packaging layer; One end of the second frame extends to the outside of the first packaging layer, and the first lead-out portion and a portion of the second frame are spaced apart along a width direction of the substrate.

6. The semiconductor structure according to claim 5, characterized in that: It also includes a pin structure, one end of which is connected to the substrate, and the other end of which extends to the outside of the first packaging layer; A portion of the lead structure outside the first packaging layer, the first lead portion, and a portion of the second frame outside the first packaging layer are arranged in parallel with each other at intervals along a width direction of the substrate.

7. The semiconductor structure according to claim 1, characterized in that: The device further comprises a second packaging layer, wherein the second packaging layer is arranged on a side of the substrate facing away from the chip, and the second packaging layer comprises a second opening, and at least a portion of the substrate is exposed to the second opening.

8. The semiconductor structure according to claim 7, characterized in that: It also includes a connection packaging layer, which is arranged on the peripheral side of the substrate and connects the first packaging layer and the second packaging layer.

9. The semiconductor structure according to claim 7, characterized in that: A projection of the chip in a thickness direction of the substrate overlaps with a projection of the first opening in the thickness direction of the substrate; And / or, a projection of the chip in the thickness direction of the substrate overlaps with a projection of the second opening in the thickness direction of the substrate.

10. The semiconductor structure according to claim 1, characterized in that The substrate comprises a first insulating layer, a first metal layer and a second insulating layer connected to each other in sequence along the thickness direction thereof, and the chip is arranged on one side of the first insulating layer or the second insulating layer along the thickness direction of the substrate; And / or, the heat dissipation structure includes a third insulating layer, a second metal layer and a fourth insulating layer which are interconnected in sequence along the thickness direction of the substrate, and the chip is arranged on one side of the third insulating layer or the fourth insulating layer along the thickness direction of the substrate.

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