Composite battery pack equalization circuit

Abstract

The utility model discloses a composite battery pack equalization circuit which comprises a battery pack, a microprocessor, an MOS tube switch array, a switch power supply module and an energy storage capacitor array. The battery pack comprises a plurality of battery monomers connected in series; the microprocessor is electrically connected with the MOS tube switch array and the switch power supply module respectively; the battery pack is connected with the energy storage capacitor array through the MOS tube switch array; the switching power supply module is connected with the battery pack and the energy storage capacitor array. According to the composite battery pack equalization circuit, equalization strategies can be adjusted according to different electric quantity states of the single batteries in the battery pack, the equalization effect is good, and the equalization efficiency is high.

Description

Technical Field

[0001] The utility model relates to the technical field of battery charging, in particular to a composite battery pack balancing circuit. Background Art

[0002] Lithium-ion batteries have the advantages of long cycle life, high charge and discharge efficiency, etc. Due to differences in battery manufacturing processes and environmental factors during the use of the battery pack, there are voltage and power imbalances among the battery cells in the battery pack, which in turn leads to accelerated battery aging, shortens the overall life of the battery pack, and reduces the use efficiency of the battery pack.

[0003] This application designs an active balancing circuit for a composite battery pack, which not only supports energy exchange between battery cells through energy storage capacitors, but also supports energy compensation for a certain low-voltage cell by the battery pack through a DC-DC module. Different balancing methods are applicable to different battery voltage distribution situations. By reasonably designing the balancing strategy, an efficient and fast battery balancing process can be achieved, with good balancing effect and high balancing efficiency. Summary of the Utility Model

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a composite battery pack balancing circuit that can adjust the balancing strategy according to the different power states of each battery cell in the battery pack, with good balancing effect and high balancing efficiency.

[0005] A composite battery pack balancing circuit provided by the utility model includes a battery pack, a microprocessor, a MOS transistor switch array, a switching power supply module, and an energy storage capacitor array;

[0006] The battery pack includes a plurality of serially connected battery cells;

[0007] The microprocessor is electrically connected to the MOS transistor switch array and the switching power supply module respectively;

[0008] The battery pack is connected to the energy storage capacitor array through the MOS transistor switch array; the MOS transistor switch array is used to connect and disconnect each battery cell from the energy storage capacitor array respectively;

[0009] The switching power supply module is connected to the battery pack and the energy storage capacitor array respectively.

[0010] Further, the MOS transistor switch array includes a plurality of switching circuits, and the switching circuits are respectively arranged between the positive electrode of the battery cell and the first end of the energy storage capacitor array and between the negative electrode of the battery cell and the second end of the energy storage capacitor array.

[0011] Further, the switching circuit includes a MOS transistor drive circuit and a MOS transistor switching circuit.

[0012] Further, the MOS transistor driving circuit includes:

[0013] An optocoupler OC, whose pin 1 and pin 3 are connected to the battery cell;

[0014] A resistor R1, whose first end is connected to the microprocessor and whose second end is connected to pin 2 of the optocoupler OC;

[0015] A triode Q1, whose base is connected to pin 4 of the optocoupler OC and whose collector is connected to pin 3 of the optocoupler OC;

[0016] A triode Q2, whose base is connected to pin 4 of the optocoupler OC and whose collector is grounded;

[0017] A resistor R2, whose first end is connected to pin 4 of the optocoupler OC and whose second end is grounded.

[0018] Further, the MOS transistor switching circuit includes:

[0019] A MOS transistor Q3, whose gate is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose drain is connected to the battery cell;

[0020] A MOS transistor Q4, whose gate is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose drain is connected to the energy storage capacitor array;

[0021] A resistor R3, whose first end is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose second end is respectively connected to the source of the MOS transistor Q3 and the source of the MOS transistor Q4.

[0022] Further, the energy storage capacitor array includes capacitors C1, C2, C3 and C4 connected in parallel.

[0023] Further, a MOS transistor switch Q is arranged between the switching power supply module and the energy storage capacitor array, and the MOS transistor switch Q is electrically connected to the microprocessor.

[0024] Compared with the prior art, the beneficial effects of the present utility model are:

[0025] The composite battery pack equalization circuit of the present utility model is provided with a MOS transistor switch array, a switching power supply module and an energy storage capacitor array; the equalization strategy can be adjusted according to the different power states of each battery cell in the battery pack, so as to achieve fast equalization, with good equalization effect and high equalization efficiency.

[0026] It should be understood that the content described in the utility model content part is not intended to limit the key or important features of the embodiments of the present utility model, nor is it used to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. Description of the Drawings

[0027] Other features, objects, and advantages of the present utility model will become more apparent by reading the following detailed description of non - restrictive embodiments with reference to the accompanying drawings:

[0028] Figure 1 It is a structural block diagram of a composite battery pack balancing circuit;

[0029] Figure 2 It is a structural schematic diagram of a composite battery pack balancing circuit;

[0030] Figure 3 It is a circuit schematic diagram of a switching circuit.

[0031] Reference numerals in the figures: 100, battery pack; 200, microprocessor; 300, MOS transistor switch array; 400, switching power supply module; 500, energy storage capacitor array;

[0032] 110, battery cell;

[0033] 310, switching circuit; 311, MOS transistor drive circuit; 312, MOS transistor switching circuit. Detailed Embodiments

[0034] The present utility model will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the relevant utility model and not for limiting the utility model. Additionally, it should be noted that for the sake of description, only the parts related to the utility model are shown in the drawings.

[0035] It should be noted that, without conflict, the embodiments and features in the embodiments of the present utility model can be combined with each other. The present utility model will be described in detail below with reference to the drawings and embodiments.

[0036] Please refer to Figures 1 to 3 , an embodiment of the present utility model provides a composite battery pack balancing circuit, including a battery pack 100, a microprocessor 200, a MOS transistor switch array 300, a switching power supply module 400, and an energy storage capacitor array 500;

[0037] The battery pack 100 includes a plurality of serially connected battery cells 110;

[0038] The microprocessor 200 is electrically connected to the MOS transistor switch array 300 and the switching power supply module 400 respectively;

[0039] The battery pack 100 is connected to the energy storage capacitor array 500 through the MOS transistor switch array 300; the MOS transistor switch array 300 is used to connect and disconnect each battery cell 110 to the energy storage capacitor array 500 respectively;

[0040] The MOS transistor switch array 300 includes a plurality of switch circuits 310. Switch circuits 310 are respectively arranged between the positive electrode of the battery cell 110 and the first end of the energy storage capacitor array 500, and between the negative electrode of the battery cell 110 and the second end of the energy storage capacitor array 500.

[0041] The switch circuit 310 includes a MOS transistor drive circuit 311 and a MOS transistor switch circuit 312.

[0042] The MOS transistor drive circuit 311 includes:

[0043] An optocoupler OC, whose pin 1 and pin 3 are connected to the battery cell 110.

[0044] A resistor R1, whose first end is connected to the microprocessor and whose second end is connected to pin 2 of the optocoupler OC.

[0045] A triode Q1, whose base is connected to pin 4 of the optocoupler OC and whose collector is connected to pin 3 of the optocoupler OC.

[0046] A triode Q2, whose base is connected to pin 4 of the optocoupler OC and whose collector is grounded.

[0047] A resistor R2, whose first end is connected to pin 4 of the optocoupler OC and whose second end is grounded.

[0048] The MOS transistor switch circuit 312 includes:

[0049] A MOS transistor Q3, whose gate is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose drain is connected to the battery cell 110.

[0050] A MOS transistor Q4, whose gate is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose drain is connected to the energy storage capacitor array 500.

[0051] A resistor R3, whose first end is respectively connected to the emitter of the triode Q1 and the emitter of the triode Q2, and whose second end is respectively connected to the source of the MOS transistor Q3 and the source of the MOS transistor Q4.

[0052] The switching power supply module 400 is respectively connected to the battery pack 100 and the energy storage capacitor array 500. A MOS transistor switch Q is arranged between the switching power supply module 400 and the energy storage capacitor array 500. The MOS transistor switch Q is electrically connected to the microprocessor 200.

[0053] The energy storage capacitor array 500 includes a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4 connected in parallel.

[0054] In this embodiment, in the switching circuit 310, when the end of the resistor R1 connected to the microprocessor 200 is at a low level, the gates of the MOS transistors Q3 and Q4 are at a high voltage, the MOS transistors Q3 and Q4 are turned on, and the A end is connected to the B end, that is, the switching circuit 310 is connected.

[0055] The microprocessor 200 collects the voltage information of each battery cell 110 through the MOS transistor switch array 300. When there is a situation where the remaining power of a single or multiple battery cells 110 in the battery pack 100 is much higher than that of other battery cells 110, the "cell-cell" equalization method is adopted. The battery cell 110 with the highest remaining power is connected to the energy storage capacitor array 500, so that the battery cell 110 charges the energy storage capacitor array 500. After the voltage of the energy storage capacitor array 500 is charged to the same as the voltage of the battery cell 110, the charging ends and the channel is closed; then the energy storage capacitor array 500 is connected to the battery cell 110 with the lowest remaining power, and at this time the energy storage capacitor array 500 starts to discharge to the battery cell 110 with the lowest power. Repeat the above process until the voltage difference between the battery cells 110 is less than the equalization termination threshold, and the equalization process of the battery pack 100 is completed.

[0056] When there is a situation where the power of a certain battery cell 110 in the battery pack 100 is significantly lower than that of other battery cells 110, the "battery pack-cell" equalization method is adopted. The microprocessor 200 starts the switching power supply module 400, takes power from the entire battery pack 100 through the switching power supply module 400; then opens the channel between the battery cell 110 with the lowest power and the energy storage capacitor array 500 through the MOS transistor switch array 300, and charges the battery cell 110 with serious power shortage until the voltage difference between the battery cells 110 is less than the equalization termination threshold, and the equalization process of the battery pack 100 is completed.

[0057] This application can adjust the equalization strategy according to the different power states of the battery cells 110 in the battery pack 100, achieve fast equalization, have good equalization effect and high equalization efficiency.

[0058] Embodiment 1

[0059] Please refer to Figure 2 , taking the battery pack 100 composed of n battery cells 110 connected in series as an example. Assume that there is a single or multiple battery cells 110 with much higher power than other battery cells 110, and Cell j has the highest battery power, and Cell k has the lowest battery power.

[0060] The equalization method at this time is:

[0061] First, the microprocessor 200 issues a command to turn on S j+ and S j-, the remaining switch circuits 310 are all in the off state. Cell j Charge the capacitors C1, C2, C3, and C4 of the energy storage capacitor array 500. When the voltage across the positive and negative electrodes of the capacitor is the same as the voltage of Cell j , the charging stage is completed.

[0062] Then S j+ and S j- are turned off; S k+ and S k- are closed. Since the capacitor voltage is higher than that of Cell k , the capacitor will charge Cell k . When the voltage across the capacitor is the same as the voltage of Cell k , S k+ and S k- are turned off, and the capacitor discharge is completed. This equalization is completed, and then this process is continuously repeated until the voltage difference between the battery cells 110 is less than the threshold for terminating equalization, and the equalization process of the battery pack 100 is completed.

[0063] Embodiment 2

[0064] Please refer to Figure 2 , taking the battery pack 100 composed of n series-connected battery cells 110 as an example. Assume that the battery power of Cell k is relatively low, and the remaining power of the other battery cells 110 is relatively high.

[0065] The equalization method at this time is as follows:

[0066] First, send a command through the microprocessor 200 to close the MOS transistor switches Q, S j+ and S j- , connect the positive pole of the output terminal of the switching power supply module 400 to the positive pole of Cell k , and connect the negative pole of the output terminal of the switching power supply module 400 to the negative pole of Cell k . Then start the switching power supply module 400 to charge Cell k through the battery pack 100, and equalization starts. When the voltage of Cell k reaches the preset voltage value, turn off the switching power supply module 400 and turn off the MOS transistor switches Q, S j+ and S j- , and the equalization ends.

[0067] In the description of this specification, the descriptions of the terms "one embodiment", "some embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0068] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A composite battery pack equalization circuit, characterized in that: It comprises a battery pack (100), a microprocessor (200), a MOS tube switch array (300), a switch power supply module (400) and an energy storage capacitor array (500); The battery pack (100) comprises a plurality of battery cells (110) connected in series; The microprocessor (200) is electrically connected to the MOS tube switch array (300) and the switch power supply module (400) respectively; The battery pack (100) is connected to the energy storage capacitor array (500) via the MOS transistor switch array (300); the MOS transistor switch array (300) is used to connect and disconnect each of the battery cells (110) from the energy storage capacitor array (500); The switching power supply module (400) is respectively connected to the battery pack (100) and the energy storage capacitor array (500).

2. The composite battery pack equalization circuit according to claim 1, characterized in that: The MOS transistor switch array (300) comprises a plurality of switch circuits (310), wherein the switch circuits (310) are respectively arranged between the positive electrode of the battery cell (110) and the first end of the energy storage capacitor array (500), and between the negative electrode of the battery cell (110) and the second end of the energy storage capacitor array (500).

3. The composite battery pack equalization circuit according to claim 2, characterized in that: The switch circuit (310) comprises a MOS tube drive circuit (311) and a MOS tube switch circuit (312).

4. The composite battery pack equalization circuit according to claim 3, characterized in that: The MOS tube driving circuit (311) comprises: An optical coupler OC, whose pins 1 and 3 are connected to the battery cell (110); A resistor R1, a first end of which is connected to the microprocessor, and a second end of which is connected to pin 2 of the optical coupler OC; A transistor Q1, whose base is connected to the 4th pin of the optical coupler OC, and whose collector is connected to the 3rd pin of the optical coupler OC; The transistor Q2 has a base connected to the 4th pin of the optical coupler OC and a collector connected to the ground; The resistor R2 has a first end connected to the 4th pin of the optical coupler OC, and a second end connected to the ground.

5. The composite battery pack equalization circuit according to claim 4, characterized in that: The MOS tube switch circuit (312) comprises: A MOS transistor Q3, whose gate is respectively connected to the emitter of the transistor Q1 and the emitter of the transistor Q2, and whose drain is connected to the battery cell (110); A MOS transistor Q4, whose gate is respectively connected to the emitter of the transistor Q1 and the emitter of the transistor Q2, and whose drain is connected to the energy storage capacitor array (500); The resistor R3 has a first end connected to the emitter of the transistor Q1 and the emitter of the transistor Q2, and a second end connected to the source of the MOS transistor Q3 and the source of the MOS transistor Q4.

6. The composite battery pack equalization circuit according to claim 1, characterized in that: The energy storage capacitor array (500) comprises a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4 connected in parallel.

7. The composite battery pack equalization circuit according to claim 1, characterized in that: A MOS tube switch Q is provided between the switching power supply module (400) and the energy storage capacitor array (500), and the MOS tube switch Q is electrically connected to the microprocessor (200).

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