Driving circuit and system

Abstract

The utility model discloses a drive circuit and system, and the drive circuit comprises a PMOS drive circuit which is used for receiving a drive signal and a drive turn-on voltage, controlling a PMOS switch tube to be switched on and outputting the drive turn-on voltage when the drive signal is at a low level, and controlling the PMOS switch tube to be switched off when the drive signal is at a high level; and the NMOS driving circuit is used for receiving the driving signal and the driving disconnection voltage, controlling the NMOS switch tube to be disconnected when the driving signal is at a low level, and controlling the NMOS switch tube to be connected and outputting the driving disconnection voltage when the driving signal is at a high level. The PMOS switch tube is used for providing driving turn-on voltage for the power switch tube so as to conduct the power switch tube; and the NMOS switch tube is used for providing drive disconnection voltage for the power switch tube to disconnect the power switch tube. That is to say, the on-off of the PMOS switch tube is controlled through the PMOS drive circuit, and the on-off of the NMOS switch tube is controlled through the NMOS drive circuit, so that the on-off of the power switch tube is controlled.

Description

Technical Field

[0001] The utility model relates to the technical field of drive circuits, and particularly relates to a drive circuit and a system. Background Art

[0002] With the rapid development of new energy technologies, power switching transistors are widely used in fields such as photovoltaic inverters, new energy vehicle motor controllers, and in-vehicle DC-DC converters. For example, power switching transistors include Si MOSFET (silicon-based power devices) and SiC MOSFET (silicon carbide power devices). As the power requirement increases, a single power switching transistor is limited by current stress. Therefore, in related technologies, multiple power switching transistors are connected in parallel to reduce the limitation of current stress on a single power switching transistor.

[0003] However, in related technologies, a set of push-pull circuits is used to drive multiple power switching transistors connected in parallel. Due to uneven gate traces of the power switching transistors connected in parallel, the turn-on and turn-off times of different power switching transistors are inconsistent, resulting in uneven current sharing among different power switching transistors, and further causing oscillation of the power switching transistors and low efficiency. Summary of the Utility Model

[0004] The utility model provides a drive circuit and a system to solve the problem in the prior art that the turn-on and turn-off times of different power switching transistors are inconsistent, resulting in uneven current sharing among different power switching transistors.

[0005] In a first aspect, the present application provides a drive circuit, including: a PMOS drive circuit, an NMOS drive circuit, a PMOS switching transistor, and an NMOS switching transistor;

[0006] The PMOS drive circuit is configured to receive a drive signal and a drive turn-on voltage. When the drive signal is at a low level, it controls the PMOS switching transistor to conduct and output the drive turn-on voltage. When the drive signal is at a high level, it controls the PMOS switching transistor to turn off;

[0007] The NMOS drive circuit is configured to receive the drive signal and a drive turn-off voltage. When the drive signal is at a low level, it controls the NMOS switching transistor to turn off. When the drive signal is at a high level, it controls the NMOS switching transistor to conduct and output the drive turn-off voltage;

[0008] The PMOS switching transistor is configured to provide the drive turn-on voltage to the power switching transistor in a conducting state, so as to turn on the power switching transistor;

[0009] The NMOS switching transistor is configured to provide the drive turn-off voltage to the power switching transistor in a conducting state, so as to turn off the power switching transistor.

[0010] In a possible implementation, the PMOS driving circuit includes a first capacitor, a first charging branch, and a first discharging branch;

[0011] A first end of the first capacitor is electrically connected to a driving turn-on voltage terminal and a drain of the PMOS switching transistor, a second end of the first capacitor is electrically connected to a first end of the first charging branch and a third end of the first discharging branch, a second end of the first charging branch is electrically connected to a second end of the first discharging branch and a gate of the PMOS switching transistor, and a third end of the first charging branch is electrically connected to a first end of the first discharging branch and a driving signal terminal;

[0012] The first charging branch is configured to conduct a path between the first end and the second end of the first charging branch when the driving signal is at a low level, so as to charge the first capacitor and provide a first turn-on voltage for the gate of the PMOS switching transistor;

[0013] The first discharging branch is configured to conduct a path between the first end and the second end of the first discharging branch when the driving signal is at a high level, so as to discharge the first capacitor and provide a first turn-off voltage for the gate of the PMOS switching transistor.

[0014] In a possible implementation, the first charging branch includes a first resistor and a first diode;

[0015] A first end of the first resistor is electrically connected to the third end of the first charging branch, and a second end of the first resistor is electrically connected to the second end of the first charging branch and a cathode of the first diode;

[0016] An anode of the first diode is electrically connected to the first end of the first charging branch.

[0017] In a possible implementation, the first discharging branch includes a second resistor and a second diode;

[0018] A first end of the second resistor is electrically connected to the third end of the first discharging branch, and a second end of the second resistor is electrically connected to the second end of the first discharging branch and a cathode of the second diode;

[0019] An anode of the second diode is electrically connected to the first end of the first discharging branch.

[0020] In a possible implementation, the NMOS driving circuit includes a second capacitor, a second charging branch, and a second discharging branch;

[0021] The first end of the second capacitor is electrically connected to the drive disconnection voltage terminal and the source of the NMOS switch transistor. The second end of the second capacitor is electrically connected to the first end of the second charging branch and the third end of the second discharging branch. The second end of the second charging branch is electrically connected to the second end of the second discharging branch and the gate of the NMOS switch transistor. The third end of the second charging branch is electrically connected to the first end of the second discharging branch and the drive signal terminal;

[0022] The second charging branch is configured to, when the drive signal is at a high level, conduct the path between the first end and the second end of the second charging branch, so as to charge the second capacitor and provide a second conduction voltage for the gate of the NMOS switch transistor;

[0023] The second discharging branch is configured to, when the drive signal is at a low level, conduct the path between the first end and the second end of the second discharging branch, so as to discharge the second capacitor and provide a second disconnection voltage for the gate of the NMOS switch transistor.

[0024] In a possible implementation manner, the second charging branch includes a third resistor and a third diode;

[0025] The first end of the third resistor is electrically connected to the first end of the second charging branch. The second end of the third resistor is electrically connected to the second end of the second charging branch and the cathode of the third diode;

[0026] The anode of the third diode is electrically connected to the third end of the second charging branch.

[0027] In a possible implementation manner, the second discharging branch includes a fourth resistor and a fourth diode;

[0028] The first end of the fourth resistor is electrically connected to the first end of the second discharging branch. The second end of the fourth resistor is electrically connected to the second end of the second discharging branch and the cathode of the fourth diode;

[0029] The anode of the fourth diode is electrically connected to the third end of the second discharging branch.

[0030] In a possible implementation manner, the circuit further includes a fifth resistor and a sixth resistor;

[0031] The first end of the fifth resistor is electrically connected to the first end of the first capacitor, the drive turn-on voltage terminal, and the drain of the PMOS switch transistor. The second end of the fifth resistor is electrically connected to the second end of the first charging branch, the second end of the first discharging branch, and the gate of the PMOS switch transistor;

[0032] The first end of the sixth resistor is electrically connected to the first end of the second capacitor, the driving disconnection voltage terminal, and the source electrode of the NMOS switching transistor. The second end of the sixth resistor is electrically connected to the second end of the second charging branch, the second end of the second discharging branch, and the gate electrode of the NMOS switching transistor.

[0033] In a possible implementation manner, the circuit further includes a turn-on resistor and a turn-off resistor;

[0034] The first end of the turn-on resistor is electrically connected to the source electrode of the PMOS switching transistor. The second end of the turn-on resistor serves as an output terminal for providing the driving turn-on voltage to the power switching transistor.

[0035] The first end of the turn-off resistor is electrically connected to the drain electrode of the NMOS switching transistor. The second end of the turn-off resistor serves as an output terminal for providing the driving disconnection voltage to the power switching transistor.

[0036] In a second aspect, the present application provides a driving system, including at least one power switching transistor and a driving circuit as described in any one of the first aspects connected to each power switching transistor.

[0037] The beneficial effects of the present utility model are as follows:

[0038] A driving circuit and a system provided by the present application. The driving circuit includes: a PMOS driving circuit, an NMOS driving circuit, a PMOS switching transistor, and an NMOS switching transistor. The PMOS driving circuit is configured to receive a driving signal and a driving turn-on voltage. When the driving signal is at a low level, it controls the PMOS switching transistor to conduct and output the driving turn-on voltage. When the driving signal is at a high level, it controls the PMOS switching transistor to disconnect. The NMOS driving circuit is configured to receive a driving signal and a driving disconnection voltage. When the driving signal is at a low level, it controls the NMOS switching transistor to disconnect. When the driving signal is at a high level, it controls the NMOS switching transistor to conduct and output the driving disconnection voltage. The PMOS switching transistor is configured to, in a conducting state, provide the driving turn-on voltage to the power switching transistor to make the power switching transistor conduct. The NMOS switching transistor is configured to, in a conducting state, provide the driving disconnection voltage to the power switching transistor to make the power switching transistor disconnect. That is to say, the present application controls the turn-on and disconnection of the PMOS switching transistor through the PMOS driving circuit, and controls the turn-on and disconnection of the NMOS switching transistor through the NMOS driving circuit, thereby controlling the turn-on and disconnection of the power switching transistor. Description of the Drawings

[0039] To more clearly illustrate the technical solutions in the embodiments of the present utility model, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0040] Figure 1 A schematic circuit diagram provided by the related art;

[0041] Figure 2 A schematic circuit diagram of a driving circuit provided by an embodiment of the present application;

[0042] Figure 3 A schematic circuit diagram of another driving circuit provided by an embodiment of the present application;

[0043] Figure 4 A schematic circuit diagram of another driving circuit provided by an embodiment of the present application;

[0044] Figure 5 A schematic circuit diagram of another driving circuit provided by an embodiment of the present application;

[0045] Figure 6 A schematic circuit diagram of another driving circuit provided by an embodiment of the present application;

[0046] Figure 7 A schematic circuit diagram of a driving system provided by an embodiment of the present application. Detailed implementation manners

[0047] In order to make the objectives, technical solutions, and advantages of the present utility model clearer, the following further describes the present utility model in detail with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.

[0048] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0049] With the rapid development of new energy technologies, power switching transistors are widely used in fields such as photovoltaic inverters, motor controllers for new energy vehicles, and on-vehicle DC-DC converters. For example, power switching transistors include Si MOSFET (silicon-based power devices) and SiC MOSFET (silicon carbide power devices). As the power requirement increases, a single power switching transistor is limited by current stress. Therefore, in related technologies, multiple power switching transistors are connected in parallel to reduce the limitation of current stress on a single power switching transistor.

[0050] However, as Figure 1 shown, it is a schematic diagram of a circuit structure provided by related technologies. In related technologies, a set of push-pull circuits 101 is used to drive multiple power switching transistors Q1, Q2, and Q3 connected in parallel. Due to the uneven gate traces of the power switching transistors connected in parallel, the turn-on and turn-off times of the power switching transistors Q1, Q2, and Q3 are inconsistent, resulting in uneven current sharing among the power switching transistors Q1, Q2, and Q3, and further causing oscillations in the power switching transistors Q1, Q2, and Q3 and low efficiency.

[0051] Based on the above problems, an embodiment of the present application provides a driving circuit. As Figure 2 shown, it is a schematic diagram of the circuit structure of a driving circuit provided by an embodiment of the present application, including a PMOS driving circuit 201, an NMOS driving circuit 202, a PMOS switching transistor S1, and an NMOS switching transistor S2;

[0052] The PMOS driving circuit 201 is configured to receive a driving signal and a driving turn-on voltage VCC. When the driving signal is at a low level, control the PMOS switching transistor S1 to conduct and output the driving turn-on voltage VCC. When the driving signal is at a high level, control the PMOS switching transistor S1 to turn off;

[0053] The NMOS driving circuit 202 is configured to receive a driving signal and a driving turn-off voltage VEE. When the driving signal is at a low level, control the NMOS switching transistor S2 to turn off. When the driving signal is at a high level, control the NMOS switching transistor S2 to conduct and output the driving turn-off voltage VEE;

[0054] The PMOS switching transistor S1 is configured to provide the driving turn-on voltage VCC to the power switching transistor in the conducting state to turn on the power switching transistor;

[0055] The NMOS switching transistor S2 is configured to provide the driving turn-off voltage VEE to the power switching transistor in the conducting state to turn off the power switching transistor.

[0056] A driving circuit provided by the present application, the driving circuit includes: a PMOS driving circuit, an NMOS driving circuit, a PMOS switching transistor, and an NMOS switching transistor; the PMOS driving circuit is used to receive a driving signal and a driving turn-on voltage, when the driving signal is at a low level, control the PMOS switching transistor to conduct and output the driving turn-on voltage, when the driving signal is at a high level, control the PMOS switching transistor to disconnect; the NMOS driving circuit is used to receive a driving signal and a driving turn-off voltage, when the driving signal is at a low level, control the NMOS switching transistor to disconnect, when the driving signal is at a high level, control the NMOS switching transistor to conduct and output the driving turn-off voltage. The PMOS switching transistor is used to provide the driving turn-on voltage to the power switching transistor in the conducting state, so that the power switching transistor conducts; the NMOS switching transistor is used to provide the driving turn-off voltage to the power switching transistor in the conducting state, so that the power switching transistor disconnects. That is to say, the present application controls the turn-on and turn-off of the PMOS switching transistor through the PMOS driving circuit, and controls the turn-on and turn-off of the NMOS switching transistor through the NMOS driving circuit, and further controls the turn-on and turn-off of the power switching transistor.

[0057] Among them, the driving turn-on voltage VCC can be 15 to 20V, and the driving turn-off voltage VEE can be -2 to -5V.

[0058] In a possible implementation manner, as Figure 3 shown, it is a schematic circuit diagram of another driving circuit provided by the embodiment of the present application. The PMOS driving circuit includes a first capacitor C1, a first charging branch 301, and a first discharging branch 302;

[0059] The first end of the first capacitor C1 is electrically connected to the driving turn-on voltage terminal and the drain of the PMOS switching transistor. The second end of the first capacitor C1 is electrically connected to the first end of the first charging branch 301 and the third end of the first discharging branch 302. The second end of the first charging branch 301 is electrically connected to the second end of the first discharging branch 302 and the gate of the PMOS switching transistor S1. The third end of the first charging branch 301 is electrically connected to the first end of the first discharging branch 302 and the driving signal terminal;

[0060] Among them, the driving turn-on voltage terminal is used to provide the driving turn-on voltage VCC; the driving signal terminal is used to provide the driving signal.

[0061] The first charging branch 301 is used to conduct the path between the first end and the second end of the first charging branch 301 when the driving signal is at a low level, so that the first capacitor C1 is charged, and provide a first conduction voltage to the gate of the PMOS switching transistor S1;

[0062] Among them, the first conduction voltage is used to control the PMOS switching transistor S1 to conduct.

[0063] Specifically, as Figure 3 shown, the first charging branch 301 includes a first resistor R1 and a first diode D1; the first end of the first resistor R1 is electrically connected to the third end of the first charging branch 301, the second end of the first resistor R1 is electrically connected to the second end of the first charging branch 301 and the cathode of the first diode D1; the anode of the first diode D1 is electrically connected to the first end of the first charging branch 301.

[0064] In a specific embodiment, when the drive signal is at a low level, the drive turn-on voltage VCC conducts the path between the first end and the second end of the first charging branch 301, that is, conducts the first diode D1, so that the drive turn-on voltage VCC charges the first capacitor C1 through the first capacitor C1, the first diode D1 and the first resistor R1, and provides a first conduction voltage for the gate of the PMOS switch S1. When the gate voltage of the PMOS switch S1 reaches the first conduction voltage, the PMOS switch S1 conducts and provides the drive turn-on voltage VCC to the power switch to make the power switch conduct.

[0065] It should be noted that the larger the parameters of the first resistor R1 and the first capacitor C1, the longer the time for the gate voltage of the PMOS switch S1 to reach the first conduction voltage. That is to say, the present application can adjust the duration for the PMOS switch S1 to conduct by adjusting the parameters of the first resistor R1 and the first capacitor C1, and further adjust the time for the power switch to conduct.

[0066] The first discharge branch 302 is used to conduct the path between the first end and the second end of the first discharge branch 302 when the drive signal is at a high level, so that the first capacitor C1 discharges and provides a first disconnection voltage for the gate of the PMOS switch S1.

[0067] Wherein, the first disconnection voltage controls the PMOS switch S1 to disconnect.

[0068] Specifically, as Figure 3 shown, the first discharge branch 302 includes a second resistor R2 and a second diode D2; the first end of the second resistor R2 is electrically connected to the third end of the first discharge branch 302, the second end of the second resistor R2 is electrically connected to the second end of the first discharge branch 302 and the cathode of the second diode D2; the anode of the second diode D2 is electrically connected to the first end of the first discharge branch 302.

[0069] In a specific embodiment, when the driving signal is at a high level, the driving signal conducts the path between the first end and the second end of the first discharge branch 302, that is, conducts the second diode D2, so that the high-level driving signal discharges the first capacitor C1 through the second diode D2, the second resistor R2, and the first capacitor C1, and provides a first disconnection voltage for the gate of the PMOS switch S1. When the gate of the PMOS switch S1 drops to the first disconnection voltage, the PMOS switch S1 disconnects, that is to say, the PMOS switch S1 no longer provides the driving turn-on voltage VCC to the power switch.

[0070] It should be noted that the larger the parameters of the second resistor R2 and the first capacitor C1, the longer the time for the gate voltage of the PMOS switch S1 to reach the first disconnection voltage. That is to say, in this application, the parameters of the second resistor R2 and the first capacitor C1 can be adjusted, so as to adjust the duration for which the PMOS switch can be disconnected, and further adjust the time for the power switch to be disconnected.

[0071] In a possible implementation manner, as Figure 4 shown, it is a schematic circuit structure diagram of another driving circuit provided by an embodiment of this application. The NMOS driving circuit includes a second capacitor C2, a second charging branch 401, and a second discharge branch 402;

[0072] The first end of the second capacitor C2 is electrically connected to the driving disconnection voltage terminal and the source electrode of the NMOS switch. The second end of the second capacitor C2 is electrically connected to the first end of the second charging branch 401 and the third end of the second discharge branch 402. The second end of the second charging branch 401 is electrically connected to the second end of the second discharge branch 402 and the gate of the NMOS switch S2. The third end of the second charging branch 401 is electrically connected to the first end of the second discharge branch 402 and the driving signal terminal;

[0073] Among them, the driving disconnection voltage terminal is used to provide the driving disconnection voltage VEE; the driving signal terminal is used to provide the driving signal.

[0074] The second charging branch 401 is used to conduct the path between the first end and the second end of the second charging branch 401 when the driving signal is at a high level, so that the second capacitor C2 is charged, and provides a second conduction voltage for the gate of the NMOS switch S2;

[0075] Among them, the second conduction voltage is used to control the NMOS switch S2 to conduct.

[0076] Specifically, as Figure 4As shown, the second charging branch 401 includes a third resistor R3 and a third diode D3; a first end of the third resistor R3 is electrically connected to a first end of the second charging branch 401, and a second end of the third resistor R3 is electrically connected to a second end of the second charging branch 401 and a cathode of the third diode D3; an anode of the third diode D3 is electrically connected to a third end of the second charging branch 401.

[0077] In a specific embodiment, when the driving signal is at a high level, the driving signal turns on the path between the first end and the second end of the second charging branch 401, that is, turns on the third diode D3, so that the high-level driving signal charges the second capacitor C2 through the third diode D3, the third resistor R3, and the second capacitor R2, and provides a second conduction voltage for the gate of the NMOS switch tube S2. When the gate voltage of the NMOS switch tube S2 reaches the second conduction voltage, the NMOS switch tube S2 turns on and provides a driving disconnection voltage VEE for the power switch tube to turn off the power switch tube.

[0078] It should be noted that the larger the parameters of the third resistor R3 and the second capacitor R2 are, the longer the time for the gate voltage of the NMOS switch tube S2 to reach the second conduction voltage is. That is to say, the present application can adjust the duration for the NMOS switch tube S2 to turn on by adjusting the parameters of the third resistor R3 and the second capacitor R2, and further adjust the time for the power switch tube to turn off.

[0079] The second discharging branch 402 is used to turn on the path between the first end and the second end of the second discharging branch 402 when the driving signal is at a low level, so that the second capacitor C2 discharges and provides a second disconnection voltage for the gate of the NMOS switch tube S2.

[0080] Wherein, the second disconnection voltage controls the NMOS switch tube S2 to turn off.

[0081] Specifically, as Figure 4 shown, the second discharging branch 402 includes a fourth resistor R4 and a fourth diode D4; a first end of the fourth resistor R4 is electrically connected to a first end of the second discharging branch 402, and a second end of the fourth resistor R4 is electrically connected to a second end of the second discharging branch 402 and a cathode of the fourth diode D4; an anode of the fourth diode D4 is electrically connected to a third end of the second discharging branch 402.

[0082] In a specific embodiment, when the drive signal is at a low level, the drive-off voltage VEE turns on the path between the first end and the second end of the second discharge branch 402, that is, turns on the fourth diode D4, so that the drive-off voltage VEE discharges the second capacitor C2 through the second capacitor C2, the fourth diode D4, and the fourth resistor R4, and provides a second turn-off voltage for the gate of the NMOS switch S2. When the gate voltage of the NMOS switch S2 drops to the second turn-off voltage, the NMOS switch S2 turns off, that is to say, the NMOS switch S2 no longer provides the drive-off voltage VEE for the power switch.

[0083] It should be noted that the larger the parameters of the fourth resistor R4 and the second capacitor C2, the longer the time for the gate voltage of the NMOS switch S2 to reach the second turn-off voltage. That is to say, the present application can adjust the turn-off duration of the NMOS switch S2 by adjusting the parameters of the fourth resistor R4 and the second capacitor C2, and further adjust the conduction time of the power switch.

[0084] In a possible implementation, as Figure 5 shown, the circuit further includes a fifth resistor R5 and a sixth resistor R6;

[0085] The first end of the fifth resistor R5 is electrically connected to the first end of the first capacitor C1, the drive-on voltage terminal, and the drain of the PMOS switch S1. The second end of the fifth resistor R5 is electrically connected to the second end of the first charging branch 301, the second end of the first discharge branch 302, and the gate of the PMOS switch S1;

[0086] The first end of the sixth resistor R6 is electrically connected to the first end of the second capacitor C2, the drive-off voltage terminal, and the source of the NMOS switch S2. The second end of the sixth resistor R6 is electrically connected to the second end of the second charging branch 401, the second end of the second discharge branch 402, and the gate of the NMOS switch S2.

[0087] In a specific embodiment, the fifth resistor R5 is the gate discharge resistor of the PMOS switch S1, and the sixth resistor R6 is the gate discharge resistor of the NMOS switch S2.

[0088] In a possible implementation, as Figure 6 shown, the circuit further includes a turn-on resistor R7 and a turn-off resistor R8;

[0089] The first end of the turn-on resistor R7 is electrically connected to the source of the PMOS switch S1. The second end of the turn-on resistor R7 is used as an output terminal to provide a drive-on voltage VCC for the power switch.

[0090] Disconnect the first end of the disconnect resistor R8 from the drain of the NMOS switch S2, and use the second end of the disconnect resistor R8 as the output terminal for providing the drive disconnect voltage VEE to the power switch.

[0091] In addition, the turn-on resistor R7 and the disconnect resistor R8 are also used to reduce the gate oscillation of the power switch.

[0092] In this application, when the drive signal is at a low level, the PMOS switch is turned on and the NMOS switch is turned off. The PMOS switch provides the drive turn-on voltage VCC to the power switch to turn on the power switch. When the drive signal is at a high level, the PMOS switch is turned off and the NMOS switch is turned on. The NMOS switch provides the drive disconnect voltage VEE to the power switch to turn off the power switch.

[0093] In addition, in this application, by adjusting the parameter values of the first resistor R1, the second resistor R2, the first capacitor C1, the third resistor R3, the fourth resistor R4, and the second capacitor C2, the turn-on and turn-off durations of the PMOS switch and the NMOS switch are adjusted, and further the conduction and disconnection times of the power switch are adjusted.

[0094] On this basis, this application drives the PMOS switch through the PMOS drive circuit and drives the NMOS switch through the NMOS drive circuit, without an additional circuit on the power switch to turn on the power switch, improving the circuit compactness of the drive circuit, reducing the parasitic inductance of the drive circuit, and further reducing the switching loss and improving the efficiency of the power switch.

[0095] Based on the same concept, the embodiment of this application also provides a drive system. The principle of this drive system is similar to that of the above drive circuit, and the repeated parts will not be elaborated here.

[0096] As Figure 7 shown, it is a schematic circuit diagram of a drive system provided by an embodiment of this application, including at least one power switch Q and a drive circuit connected to each power switch.

[0097] Among them, the power switch tube can be a SiC MOSFET or a Si IGBT (silicon-based insulated gate bipolar transistor). When all the power switch tubes are SiC MOSFETs, the parameters of the first resistor R1, the second resistor R2, the first capacitor C1, the third resistor R3, the fourth resistor R4, and the second capacitor C2 of the driving circuit corresponding to each power switch tube can be adjusted, so as to adjust the on and off times of the power switch tubes, and avoid the current sharing problem of multi-tube parallel connection caused by different self-parameters or inconsistent driving layouts of the power switch tubes. When the power switch tubes are SiC MOSFETs and Si IGBTs, the parameters of the first resistor R1, the second resistor R2, the first capacitor C1, the third resistor R3, the fourth resistor R4, and the second capacitor C2 of the driving circuit corresponding to each power switch tube can be adjusted to achieve that the turn-on of the SiC MOSFET is earlier than that of the Si IGBT, and the turn-off of the SiC MOSFET is earlier than that of the Si IGBT.

[0098] A driving circuit and system provided by this application, the driving circuit includes: a PMOS driving circuit, an NMOS driving circuit, a PMOS switch tube, and an NMOS switch tube; the PMOS driving circuit is used to receive a driving signal and a driving turn-on voltage, and when the driving signal is at a low level, control the PMOS switch tube to conduct and output the driving turn-on voltage, and when the driving signal is at a high level, control the PMOS switch tube to turn off; the NMOS driving circuit is used to receive a driving signal and a driving turn-off voltage, and when the driving signal is at a low level, control the NMOS switch tube to turn off, and when the driving signal is at a high level, control the NMOS switch tube to conduct and output the driving turn-off voltage. The PMOS switch tube is used to provide a driving turn-on voltage to the power switch tube in the conducting state to make the power switch tube conduct; the NMOS switch tube is used to provide a driving turn-off voltage to the power switch tube in the conducting state to make the power switch tube turn off. That is to say, this application controls the turn-on and turn-off of the PMOS switch tube through the PMOS driving circuit, and controls the turn-on and turn-off of the NMOS switch tube through the NMOS driving circuit, so as to control the turn-on and turn-off of the power switch tube.

[0099] The above describes this application with reference to the block diagrams and / or flowcharts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that the functions of one block in the block diagram and / or flowchart illustration and the combination of blocks in the block diagram and / or flowchart illustration can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, and / or other programmable data processing devices to generate a machine, so that the instructions executed by the computer processor and / or other programmable data processing devices create a method for implementing the functions / actions specified in the blocks of the block diagram and / or flowchart.

[0100] Accordingly, the present application can also be implemented by hardware and / or software (including firmware, resident software, microcode, etc.). Further, the present application can take the form of a computer program product on a computer-usable or computer-readable storage medium, having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of the present application, the computer-usable or computer-readable medium can be any medium that can contain, store, communicate, transmit, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0101] Obviously, those skilled in the art can make various changes and modifications to the present utility model without departing from the spirit and scope of the present utility model. Thus, if these modifications and variations of the present utility model fall within the scope of the claims of the present utility model and their equivalent technologies, the present utility model is also intended to include these changes and modifications.

Claims

1. A driving circuit, characterized in that: include: PMOS driving circuit, NMOS driving circuit, PMOS switch tube and NMOS switch tube; The PMOS driving circuit is used to receive a driving signal and a driving turn-on voltage, and when the driving signal is at a low level, controls the PMOS switch tube to be turned on and output the driving turn-on voltage, and when the driving signal is at a high level, controls the PMOS switch tube to be turned off; The NMOS driving circuit is used to receive the driving signal and the driving disconnection voltage, and when the driving signal is at a low level, control the NMOS switch tube to be disconnected, and when the driving signal is at a high level, control the NMOS switch tube to be turned on and output the driving disconnection voltage; The PMOS switch tube is used to provide the driving turn-on voltage to the power switch tube in the on state, so as to turn on the power switch tube; The NMOS switch tube is used to provide the driving disconnection voltage to the power switch tube in the on state, so as to disconnect the power switch tube.

2. The circuit according to claim 1, characterized in that The PMOS driving circuit includes a first capacitor, a first charging branch and a first discharging branch; The first end of the first capacitor is electrically connected to the driving turn-on voltage end and the drain of the PMOS switch tube, the second end of the first capacitor is electrically connected to the first end of the first charging branch and the third end of the first discharging branch, the second end of the first charging branch is electrically connected to the second end of the first discharging branch and the gate of the PMOS switch tube, and the third end of the first charging branch is electrically connected to the first end of the first discharging branch and the driving signal end; The first charging branch is used to conduct the path between the first end of the first charging branch and the second end of the first charging branch when the driving signal is at a low level, so as to charge the first capacitor and provide a first turn-on voltage for the gate of the PMOS switch tube; The first discharge branch is used to conduct the path between the first end of the first discharge branch and the second end of the first discharge branch when the driving signal is at a high level, so as to discharge the first capacitor and provide a first disconnection voltage for the gate of the PMOS switch tube.

3. The circuit according to claim 2, characterized in that The first charging branch includes a first resistor and a first diode; The first end of the first resistor is electrically connected to the third end of the first charging branch, and the second end of the first resistor is electrically connected to the second end of the first charging branch and the cathode of the first diode; An anode of the first diode is electrically connected to a first end of the first charging branch.

4. The circuit according to claim 2, characterized in that The first discharge branch includes a second resistor and a second diode; The first end of the second resistor is electrically connected to the third end of the first discharge branch, and the second end of the second resistor is electrically connected to the second end of the first discharge branch and the cathode of the second diode; An anode of the second diode is electrically connected to a first end of the first discharge branch.

5. The circuit according to claim 2, characterized in that The NMOS driving circuit includes a second capacitor, a second charging branch and a second discharging branch; The first end of the second capacitor is electrically connected to the driving disconnect voltage terminal and the source of the NMOS switch tube, the second end of the second capacitor is electrically connected to the first end of the second charging branch and the third end of the second discharging branch, the second end of the second charging branch is electrically connected to the second end of the second discharging branch and the gate of the NMOS switch tube, and the third end of the second charging branch is electrically connected to the first end of the second discharging branch and the driving signal terminal; The second charging branch is used to conduct the path between the first end of the second charging branch and the second end of the second charging branch when the driving signal is at a high level, so as to charge the second capacitor and provide a second turn-on voltage for the gate of the NMOS switch tube; The second discharge branch is used to conduct the path between the first end of the second discharge branch and the second end of the second discharge branch when the driving signal is at a low level, so as to discharge the second capacitor and provide a second disconnection voltage for the gate of the NMOS switch tube.

6. The circuit according to claim 5, characterized in that The second charging branch includes a third resistor and a third diode; A first end of the third resistor is electrically connected to a first end of the second charging branch, and a second end of the third resistor is electrically connected to a second end of the second charging branch and a cathode of the third diode; An anode of the third diode is electrically connected to a third end of the second charging branch.

7. The circuit according to claim 5, characterized in that The second discharge branch includes a fourth resistor and a fourth diode; A first end of the fourth resistor is electrically connected to a first end of the second discharge branch, and a second end of the fourth resistor is electrically connected to a second end of the second discharge branch and a cathode of the fourth diode; An anode of the fourth diode is electrically connected to the third end of the second discharge branch.

8. The circuit according to any one of claims 5 to 7, characterized in that: The circuit further includes a fifth resistor and a sixth resistor; The first end of the fifth resistor is electrically connected to the first end of the first capacitor, the driving turn-on voltage end and the drain of the PMOS switch tube, and the second end of the fifth resistor is electrically connected to the second end of the first charging branch, the second end of the first discharging branch and the gate of the PMOS switch tube; The first end of the sixth resistor is electrically connected to the first end of the second capacitor, the driving disconnect voltage end and the source of the NMOS switch tube, and the second end of the sixth resistor is electrically connected to the second end of the second charging branch, the second end of the second discharging branch and the gate of the NMOS switch tube.

9. The circuit according to claim 1, characterized in that The circuit also includes an on resistor and an off resistor; The first end of the turn-on resistor is electrically connected to the source of the PMOS switch tube, and the second end of the turn-on resistor serves as an output end, and is used to provide the driving turn-on voltage to the power switch tube; The first end of the disconnect resistor is electrically connected to the drain of the NMOS switch tube, and the second end of the disconnect resistor serves as an output end for providing the driving disconnect voltage to the power switch tube.

10. A drive system, characterized in that: The invention comprises at least one power switch tube and a driving circuit as claimed in any one of claims 1 to 9 connected to each power switch tube.

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