Capacitor assembly with multiple capacitors connected in parallel, power assembly and converter

Abstract

The utility model provides a capacitor assembly with multiple capacitors connected in parallel, a power assembly and a converter, the capacitor assembly comprises a capacitor pool arranged on a printed circuit board, and a terminal group and a transfer end which are respectively located at two opposite sides of the capacitor pool, the terminal group comprises a first terminal and a second terminal, the capacitor pool comprises at least one capacitor array, and the transfer end comprises a first terminal and a second terminal. Each capacitor array comprises a plurality of capacitors which are connected in parallel, the first ends of the plurality of capacitors and the first terminal are connected to a first conduction path, the second ends of the plurality of capacitors and the transfer end are connected to a second conduction path, the second terminal and the transfer end are connected to a third conduction path, and the third conduction path is connected to a second conduction path. Therefore, commutation paths from the first terminal to the second terminal after passing through the capacitors are equal in length, equivalent impedance on conduction paths of the capacitors is equal in magnitude, and current sharing of the capacitors is guaranteed.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and particularly to a capacitor component, a power component, and a converter with multiple capacitors connected in parallel. Background Art

[0002] In the power supply field, in order to improve the stability of the circuit and reduce noise, capacitors are commonly used. Especially in inverters and uninterruptible power supplies, capacitors are used as bus capacitors, which can not only filter out the high-frequency noise of the power supply, but also provide a stable power supply voltage, and are widely used. To meet the demand for large capacitance values, multiple capacitors are often connected in parallel in use. When multiple capacitors are connected in parallel, how to improve the current sharing degree among the capacitors is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a capacitor component, a power component, and a converter with multiple capacitors connected in parallel.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, the present invention provides a capacitor component with multiple capacitors connected, including a capacitor bank, a terminal group, and a transfer terminal disposed on a printed circuit board. The terminal group includes a first terminal and a second terminal. The capacitor bank includes at least one capacitor array, and each capacitor array includes multiple capacitors connected in parallel. The first ends of the multiple capacitors and the first terminal are both connected to a first conduction path, the second ends of the multiple capacitors and the transfer terminal are connected to a second conduction path, and the second terminal and the transfer terminal are both connected to a third conduction path, so that the commutation paths from the first terminal to the second terminal passing through each capacitor are of equal length, where the first terminal and the transfer terminal are respectively located on opposite sides of the capacitor bank.

[0006] For the capacitor component provided in this solution, by setting a transfer terminal on the opposite side of the terminal group, connecting the first ends of the multiple capacitors and the first terminal in the terminal group through a first conduction path, connecting the second ends of the multiple capacitors through a second conduction path, and connecting the transfer terminal and the second terminal in the terminal group through a third conduction path, the current paths from the first terminal of the terminal group entering through each capacitor and returning to the second terminal of the terminal group are of equal length. Therefore, the equivalent impedances on the conduction paths are equal, thus ensuring the current sharing of each capacitor. In addition, in this solution, by connecting the transfer terminal and the second terminal through a third conduction path, the second terminal and the first terminal can be set at different positions on the PCB according to actual needs, and the commutation paths passing through each capacitor can be ensured to be of equal length, improving the layout freedom of the PCB.

[0007] Based on the above Scheme 1, a capacitor component of Scheme 2 is provided: The first terminal is the first end of the first capacitor in the capacitor array, and / or the transfer terminal is the second end of the last capacitor in the capacitor array, where the first capacitor and the last capacitor are the two capacitors with the farthest distance in the capacitor array.

[0008] In this scheme, one pin of the first capacitor or the last capacitor in the capacitor array is used as the first terminal or the transfer terminal of the terminal group, thereby reducing the connection terminals and increasing the freedom of printed circuit layout.

[0009] Based on the above Scheme 1 or Scheme 2, a capacitor component of Scheme 3 is provided: The terminal group includes a positive terminal, a neutral terminal, and a negative terminal. The capacitor bank includes at least one positive capacitor array and at least one negative capacitor array. The first ends of the multiple capacitors in the positive capacitor array and the positive terminal are both connected to the positive conduction path. The second ends of the multiple capacitors in the negative capacitor array and the negative terminal are both connected to the negative conduction path. The second ends of the multiple capacitors in the positive capacitor array, the first ends of the multiple capacitors in the negative capacitor array, and the transfer terminal are all connected to the second conduction path. The neutral terminal and the transfer terminal are both connected to the third conduction path, where the first terminal is the positive terminal or the negative terminal, and the second terminal is the neutral terminal.

[0010] In Scheme 3, the capacitor bank includes a positive capacitor array and a negative capacitor array. Correspondingly, the terminal group includes a positive terminal, a neutral terminal, and a negative terminal. The second ends of the multiple capacitors in the positive capacitor array and the first ends of the multiple capacitors in the negative capacitor array are both connected to the transfer terminal. It can be seen that in this scheme, the positive capacitor array and the negative capacitor array are connected in series. For the positive capacitor array, the positive terminal and the neutral terminal in this scheme respectively correspond to the first terminal and the second terminal in Scheme 1, and the positive conduction path corresponds to the first conduction path of the positive capacitor array. For the negative capacitor array, the negative terminal and the neutral terminal in this scheme respectively correspond to the first terminal and the second terminal in Scheme 1, and the negative conduction path corresponds to the first conduction path of the negative capacitor array. Thus, in this scheme, the positive and negative capacitor arrays share three connection terminals, and also share the second conduction path and the third conduction path on the conduction path, realizing current sharing among the capacitors in the positive capacitor array and current sharing among the capacitors in the negative capacitor array, while reducing the connection paths between the capacitors and lowering the wiring difficulty.

[0011] Based on the above Scheme 3, a capacitor component of Scheme 4 is provided: The positive conduction path, the second conduction path, and the third conduction path are respectively located on different wiring layers of the printed circuit, and the negative conduction path is located on the same wiring layer as the positive conduction path.

[0012] In this solution, different conduction paths are distributed on different wiring layers, which is convenient for wiring. Additionally, since the distributions of the positive capacitance array and the negative capacitance array on the printed circuit cannot overlap, the positive conduction paths corresponding to the positive capacitance array and the negative conduction paths corresponding to the negative capacitance array are respectively on the same wiring layer. This can make full use of the wiring layer. Moreover, for many circuits, the operating currents and operating voltages in the positive and negative half-cycles are symmetric. Distributing them on the same wiring layer can also make the positive and negative half-cycles relatively symmetric from the wiring perspective, which is beneficial for error checking.

[0013] In a second aspect, the present invention provides a capacitive component with multiple-capacitor connection according to Solution 5, including a capacitor bank and a terminal group disposed on a printed circuit board. The terminal group includes a first terminal and a second terminal respectively located on opposite sides of the capacitor bank. The capacitor bank includes at least one capacitance array, and each capacitance array includes multiple capacitors connected in parallel. The first ends of the multiple capacitors and the first terminal are both connected to a first conduction path, and the second ends of the multiple capacitors and the second terminal are both connected to a second conduction path, so that the commutation paths from the first terminal to the second terminal passing through each capacitor are of equal length.

[0014] In this solution, the first terminal and the second terminal are respectively disposed on opposite sides of the capacitor bank and are connected to the first ends and the second ends of the multiple capacitors through the first conduction path and the second conduction path respectively, so that the current paths from the first terminal of the terminal group through each capacitor back to the second terminal of the terminal group are of equal length. Thus, the equivalent impedances on the conduction paths are equal, ensuring the equal current sharing of each capacitor.

[0015] In a third aspect, the present invention provides a power component according to Solution 6, including a power conversion circuit and the capacitive component in any one of Solutions 1 to 5 above. Among them, the power conversion circuit is connected to the terminal group of the capacitive component.

[0016] The power component provided in this solution is based on the capacitive components provided in Solutions 1 to 5 above and naturally inherits the beneficial effects of the above capacitive components, which will not be elaborated here.

[0017] Further based on Solution 6, a power component according to Solution 7 is provided. The power conversion circuit includes multiple conversion bridge arms. The capacitor bank includes at least one first positive capacitance array and at least one first negative capacitance array. The first positive capacitance array and the first negative capacitance array are alternately arranged, and each conversion bridge arm is disposed between the first positive capacitance array and the first negative capacitance array.

[0018] In this solution, the first positive capacitor array and the first negative capacitor array are alternately arranged, and the power conversion bridge arm is arranged between the positive capacitor array and the negative capacitor array, so that the paths of each power conversion bridge arm to the capacitor bank are relatively equal in length, and the capacitor arrays are dispersedly arranged on both sides of the power conversion bridge arm, so that each power conversion bridge arm has a positive capacitor array and a negative capacitor array nearby, which is beneficial to shortening the commutation path, reducing the commutation stray inductance, and reducing the reverse peak.

[0019] Further, based on Solution Seven, a power component of Solution Eight is provided. The conversion bridge arm is a multi-level bridge arm, and the two multi-level bridge arms distributed on both sides of the first capacitor array are mirror-symmetrical in layout. The first capacitor array includes a first positive capacitor array and a first negative capacitor array.

[0020] Further, based on Solution Eight, a power component of Solution Nine is provided. The multi-level bridge arm further includes a decoupling capacitor. The decoupling capacitor is arranged in the core device area, and both ends of the decoupling capacitor are respectively connected in parallel with the positive capacitor array or the negative capacitor array. Among them, the core device area is a device area formed by surrounding multiple switching devices constituting the multi-level bridge arm.

[0021] In this solution, by setting the decoupling capacitor and arranging both the decoupling capacitor and the multiple switching devices constituting the multi-level bridge arm in the core device area, relatively, the positive capacitor array and the negative capacitor array are located outside the core device area. Relatively, the commutation path passing through the decoupling capacitor is greatly shortened compared with the commutation path passing through the positive capacitor array and the negative capacitor array, reducing the path stray inductance during the commutation process, thereby reducing the reverse peak and increasing the device life.

[0022] Fourthly, the present invention provides a converter, which includes the capacitor component of any one of Solutions One to Five above, or includes the power component of any one of Solutions Six to Nine above.

[0023] The converter provided by this solution naturally inherits the beneficial effects of the above capacitor component or power component based on the capacitor component provided by Solutions One to Five above or the power component provided by Solutions Six to Nine above, which will not be elaborated here. Description of the Drawings

[0024] Figure 1 is the connection equivalent schematic of the capacitor component provided in the embodiment of the present application Figure 1

[0025] Figure 2 is the connection equivalent schematic of the capacitor component provided in the embodiment of the present application Figure 2 ;

[0026] Figure 3 is the structural schematic diagram of the printed circuit board of the capacitor component provided in the embodiment of the present application;

[0027] Figure 4 Schematic diagram of the power component provided in the embodiment of the present application Figure 1 ;

[0028] Figure 5 Schematic diagram of the power component with multiple conversion bridge arms provided in the embodiment of the present application Figure 1 ;

[0029] Figure 6 Schematic diagram of the power component with multiple conversion bridge arms provided in the embodiment of the present application Figure 2 ;

[0030] Figure 7 Schematic diagram of the T-type three-level bridge arm provided in the embodiment of the present application;

[0031] Figure 8 Schematic diagram of the I-type three-level bridge arm provided in the embodiment of the present application;

[0032] Figure 9 Schematic diagram of the rectangular layout of the T-type three-level bridge arm provided in the embodiment of the present application;

[0033] Figure 10 Schematic diagram of the lower diamond layout of the T-type three-level bridge arm provided in the embodiment of the present application;

[0034] Figure 11 Schematic diagram under the layout of the I-type three-level bridge arm provided in the embodiment of the present application Figure 1 ;

[0035] Figure 12 Schematic diagram under the layout of the I-type three-level bridge arm provided in the embodiment of the present application Figure 2 ;

[0036] Figure 13 Schematic diagram under the layout of the I-type three-level bridge arm provided in the embodiment of the present application Figure 3 ;

[0037] Figure 14 Schematic diagram under the layout of the I-type three-level bridge arm provided in the embodiment of the present application Figure 4 ;

[0038] Figure 15 Schematic diagram of the equivalent connection of the capacitor component provided in the embodiment of the present application Figure 3 ;

[0039] Figure 16 Schematic diagram of the equivalent connection of the capacitor component provided in the embodiment of the present application Figure 4 ; Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. Additionally, it should be noted that for the convenience of description, only parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than the illustrated or described order.

[0041] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor;

[0042] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide-Semiconductor Field-Effect Transistor;

[0043] BJT (Bipolar Junction Transistor): Bipolar Junction Transistor;

[0044] HBT (Hetero Junction Bipolar Transistor): Hetero Junction Bipolar Transistor.

[0045] Next, each embodiment of the present application will be described in detail in conjunction with the accompanying drawings.

[0046] In one embodiment, a capacitive component is provided, which includes a capacitor bank, a terminal group, and a transfer terminal disposed on a printed circuit board. The terminal group includes a first terminal and a second terminal. The capacitor bank includes at least one capacitor array, and each capacitor array includes a plurality of capacitors connected in parallel. The first ends of the plurality of capacitors and the first terminal are both connected to a first conduction path, the second ends of the plurality of capacitors and the transfer terminal are both connected to a second conduction path, and the second terminal and the transfer terminal are both connected to a third conduction path, so that the commutation paths from the first terminal to the second terminal passing through each capacitor are of equal length, wherein the first terminal and the transfer terminal are respectively located on opposite sides of the capacitor bank.

[0047] In this embodiment, the connection relationship of the capacitive component is equivalent to Figure 1 as shown in the figure, where the first terminal 11 and the second terminal 12 are used for connecting the capacitive component to other external components. A plurality of capacitors C1 are connected in parallel to form a capacitor array. The first end of each capacitor C1 is connected to the first terminal 11 through the first conduction path 21, the second end of each capacitor C2 is connected to the transfer terminal 13 through the second conduction path 22, and the transfer terminal 13 is connected to the second terminal through the third conduction path 23. As can be seen from Figure 1 the schematic diagram, the path length of each capacitor C1 through the first conduction path 21 is the same as the sum of the lengths through the second conduction path 22 and the third conduction path 23. That is, the commutation paths from the first terminal 11 to the second terminal 12 passing through each capacitor C1 are of equal length. The length of the commutation path is related to the equivalent impedance, and different impedances will affect the current sharing of different capacitors. When the conduction paths of different capacitors are of equal length, the equivalent impedances thereon are equal, thereby ensuring that the current flowing through each capacitor C1 is evenly distributed.

[0048] Figure 1 It only represents the electrical connection relationship of the capacitive component. In the electrical connection relationship, both the second terminal 12 and the first terminal 11 are set on the left side, which does not mean that their layout on the printed circuit board is also on the same side of the capacitor bank or the printed circuit board. Through the third conduction path 13, the transfer terminal 13 can be connected to any position, that is, the second terminal 12 can be set at any position according to needs, as long as it is ensured that the first terminal and the transfer terminal are located on opposite sides of the capacitor bank, the commutation paths from the first terminal 11 to the second terminal passing through each capacitor can be of equal length, thereby ensuring the even current distribution of each capacitor C1.

[0049] In addition, a large capacitor with a preset capacitance value is formed by connecting multiple small capacitors in parallel. Since the parasitic inductance of a capacitor is proportional to the pin pitch, the package volume of a small capacitor is small, resulting in a small parasitic inductance for a single capacitor. From experimental data, it can be seen that the parasitic inductance of the large capacitor is greater than that of the equivalent large capacitor formed by connecting multiple small capacitors in parallel. Therefore, connecting multiple small capacitors in parallel can further reduce the parasitic inductance and the reverse peak of the device. In addition, the distribution positions of the individual small capacitors can be flexibly selected, providing greater freedom for the layout of the PCB board.

[0050] In another embodiment, the capacitor bank may include at least one positive capacitor array and at least one negative capacitor array. The terminal group includes a positive terminal, a neutral terminal, and a negative terminal. The first ends of the multiple capacitors in the positive capacitor array and the positive terminal are both connected to a positive conduction path. The second ends of the multiple capacitors in the negative capacitor array and the negative terminal are both connected to a negative conduction path. The second ends of the multiple capacitors in the positive capacitor array, the first ends of the multiple capacitors in the negative capacitor array, and the transfer terminal are all connected to a second conduction path. The neutral terminal and the transfer terminal are both connected to the third conduction path.

[0051] In this embodiment, the connection relationship of the capacitor assembly is equivalent to Figure 2 as shown in the figure, including at least one positive capacitor array (including multiple capacitors C1, hereinafter represented by C1) and at least one negative capacitor array (including multiple capacitors C2, hereinafter represented by C2). For the positive capacitor array C1, the positive terminal BUS+ and the neutral terminal N are respectively equivalent to the first terminal 11 and the second terminal 12 in the previous embodiment. The positive conduction path 21 is equivalent to the first conduction path 21 in the previous embodiment. The second conduction path 22 is equivalent to the second conduction path 22 in the previous embodiment. The third conduction path 23 is equivalent to the third conduction path 23 in the previous embodiment. The transfer terminal (i.e., the N-line busbar in the figure) is equivalent to the transfer terminal in the previous embodiment. For the negative capacitor array C2, the negative terminal BUS- and the neutral terminal N in this embodiment are respectively equivalent to the first terminal 11 and the second terminal 12 in the previous embodiment. The negative conduction path 24 is equivalent to the first conduction path 21 in the previous specific embodiment. The second conduction path 22 is equivalent to the second conduction path 22 in the previous embodiment. The third conduction path 23 is equivalent to the third conduction path 23 in the previous embodiment. The transfer terminal (i.e., the N-line busbar in the figure) is equivalent to the transfer terminal in the previous embodiment. It can be seen that in this embodiment, it is equivalent to two capacitor arrays connected in series in the previous embodiment. And from the above connection relationship and Figure 2It can also be seen that in this embodiment, the positive capacitance array C1 and the negative capacitance array C2 are connected in series. The positive capacitance array and the negative capacitance array share three connection terminals (BUS+, N, BUS-), and also share the second conduction path 22 and the third conduction path 23 on the conduction path, realizing current sharing among the capacitors in the positive capacitance array and among the capacitors in the negative capacitance array, while reducing the connection paths between the capacitors and lowering the wiring difficulty.

[0052] Specifically, the PCB (Printed Circuit Board) layout of this embodiment is as Figure 3 shown. Figure 3 It shows that multiple capacitors 1 form a capacitor bank, and terminal groups (including positive terminal 11, negative terminal 14, and neutral terminal 12) and a transfer terminal 13 are respectively located on both sides of the capacitor bank. As can be seen in the figure, the terminal group is located on the left side of the capacitor bank, while the transfer terminal 13 is located on the right side of the capacitor bank, that is, the terminal group and the transfer terminal are respectively located on opposite sides of the capacitor bank. The multiple capacitors 1 forming the capacitor bank are divided into a positive capacitance array and a negative capacitance array. Figure 3 (a), (b), and (c) are wiring diagrams of different wiring layers of the PCB. Among them, the positive conduction path 21 and the negative conduction path 24 are arranged on the same wiring layer, as Figure 3 shown in (a), and the second conduction path 22 and the third conduction path are respectively located on the other two wiring layers, as shown in Figure 3 (b) and Figure 3 (c) respectively.

[0053] In this embodiment, the terminal group is located on the left side of the capacitor bank, that is, the first terminal 11 and the second terminal 12 (or rather, the positive terminal BUS+, the neutral terminal N, and the negative terminal BUS-) are all located on the same side of the capacitor bank. In other embodiments, the first terminal 11 and the second terminal 12 can be respectively arranged on both sides of the capacitor bank. For example, the Figure 3 second terminal 12 (i.e., the neutral terminal N) in is arranged near the transfer terminal 13 or other positions, which does not affect the equal length of the commutation paths of each capacitor. In other words, it does not affect the current sharing effect of the capacitor assembly in this embodiment.

[0054] Specifically, Figure 3 (a) shows that the positive terminal 11 (i.e., corresponding to Figure 2 BUS+ in) and the first ends of each capacitor 1 in the positive capacitance array are all connected to the positive conduction path 21 (among the two pins of the capacitor 1, the small white dot located within the conduction path indicates connection to the corresponding conduction path, and the black ring dot indicates non - connection to the conduction path. It can be known from Figure 3 (a) that the 15 capacitors 1 located on the upper side in this PCB are the positive capacitance array), and the negative terminal 14 (i.e., corresponding to Figure 2The first ends of each capacitor 1 in the BUS- in and the negative capacitance array are both connected to the negative conduction path 24 (from Figure 3 As can be seen from Figure 3 , the 15 capacitors 1 with bit distribution on the lower side in the PCB are the negative capacitance array). Figure 3 (b) It can be seen that the second ends of each capacitor 1 in the positive capacitance array, the first ends of each capacitor 1 in the negative capacitance array, and the transfer ends are all connected to the second conduction path 22, Figure 3 (c) It can be seen that the neutral terminal 12 and the transfer terminal 13 are connected through the third conduction path 23.

[0055] According to the above Figure 3 As can be seen, the positive conduction path 21, the second conduction path 22, and the third conduction path 23 are respectively located on different wiring layers of the printed circuit, and the negative conduction path 24 is located on the same wiring layer as the positive conduction path 21. Distributing different conduction paths on different wiring layers facilitates wiring. In addition, since the distributions of the positive capacitance array and the negative capacitance array on the printed circuit cannot overlap, as long as the positive capacitance array and the negative capacitance array are partitioned and set, the positive conduction path corresponding to the positive capacitance array and the negative conduction path corresponding to the negative capacitance array can be respectively on the same wiring layer, which can make full use of the wiring layer. Moreover, for many circuits, the working currents and working voltages in the positive and negative half-cycles are symmetric. Distributing them on the same wiring layer can also be relatively symmetric in terms of wiring for the positive and negative half-cycles, which is beneficial for error checking.

[0056] From Figure 3 As can be seen, the terminal group including the positive terminal 11, the negative terminal 14, and the neutral terminal 12 is used as the connection end between the capacitor component and other external components. The connection end that needs to be independently set is convenient for other external components to connect to it, while the transfer terminal 13 only serves as the aggregation end of two conduction paths and may not require an independently set connection end. In this embodiment, for example, the pin of the leftmost capacitor in the capacitor array is used as the transfer terminal, specifically, the second end of the leftmost capacitor in the positive capacitance array and the first end of the leftmost capacitor in the negative capacitance array. Taking the capacitor close to the terminal group in the capacitor array as the first capacitor, then the leftmost capacitor (i.e., the last capacitor) is the capacitor in the capacitor array that is the farthest from the first capacitor. In other embodiments, the transfer terminal 11 can also be independently set with a connection end like the terminal group. Of course, if the terminal group is not used to connect to other external components, or other external components can be connected through other means, the pin of a certain capacitor in the capacitor array can also be used as the terminal group. Of course, the capacitor used as the terminal group should preferably be the first capacitor in the capacitor array that is the farthest from the last capacitor, so as to ensure that the commutation paths passing through each capacitor are of equal length.

[0057] When the capacitor assembly is used as a bus capacitor, the terminal group may further include a third terminal 15 and a fourth terminal 16. Among them, an external other device is connected between the third terminal 15 and the first terminal 11, and another device is connected between the fourth terminal 16 and the second terminal 12. The other device here may be an inductor, an absorption circuit, etc., which is not specifically limited herein. Thus, the capacitor bank and other devices form a complete capacitor assembly. The external connection terminals of the capacitor assembly include the third terminal 15, the neutral terminal 12, and the fourth terminal 16, increasing the integration of the PCB and reducing the assembly difficulty of the assembly personnel.

[0058] In another embodiment of the present application, another capacitor assembly is provided, including a capacitor bank and a terminal group arranged on a printed circuit board. The terminal group includes a first terminal and a second terminal respectively located on opposite sides of the capacitor bank. The capacitor bank includes at least one capacitor array, and each capacitor array includes a plurality of capacitors connected in parallel. The first ends of the plurality of capacitors and the first terminal are all connected to a first conduction path, and the second ends of the plurality of capacitors and the second terminal are all connected to a second conduction path, so that the commutation paths from the first terminal to the second terminal passing through each capacitor are of equal length.

[0059] As Figure 15 shown, in this embodiment, since the first terminal 11 and the second terminal 12 are respectively arranged on opposite sides of the capacitor bank, the current paths from the first terminal of the terminal group entering through each capacitor C1 and returning to the second terminal of the terminal group are of equal length. Therefore, the equivalent impedances on the conduction paths are equal, thus ensuring the equal current sharing of each capacitor. Compared with the first embodiment, this embodiment does not require the transfer terminal 13 and the third conduction path 23. Correspondingly, the positions of the first terminal 11 and the second terminal 12 are relatively limited. The first terminal 11 and the second terminal 12 are required to be respectively located on opposite sides of the capacitor bank to make the commutation paths passing through each capacitor of equal length.

[0060] In another embodiment, the capacitor bank may include at least one positive capacitor array and at least one negative capacitor array. The terminal group includes a positive terminal, a neutral terminal, and a negative terminal. The first ends of the plurality of capacitors in the positive capacitor array and the positive terminal are all connected to a positive conduction path. The second ends of the plurality of capacitors in the negative capacitor array and the negative terminal are all connected to a negative conduction path. The second ends of the plurality of capacitors in the positive capacitor array, the first ends of the plurality of capacitors in the negative capacitor array, and the neutral terminal are all connected to a second conduction path. Among them, the first terminal is the positive terminal or the negative terminal, and the second terminal is the neutral terminal.

[0061] In this embodiment, the connection relationship of the capacitor assembly is equivalent to Figure 16As shown, it includes at least one positive capacitance array (including a plurality of capacitors C1, hereinafter represented by C1) and at least one negative capacitance array (including a plurality of capacitors C2, hereinafter represented by C2). The positive terminal BUS+ and the negative terminal BUS- are located on one side of the capacitance pool, and the neutral terminal N is located on the other side. For the positive capacitance array C1, the positive terminal BUS+ and the neutral terminal N respectively correspond to the first terminal 11 and the second terminal 12 in the previous embodiment. The positive conduction path 21 corresponds to the first conduction path 21 in the previous embodiment, and the second conduction path 22 corresponds to the second conduction path 22 in the previous embodiment. For the negative capacitance array C2, the negative terminal BUS- and the neutral terminal N in this embodiment respectively correspond to the first terminal 11 and the second terminal 12 in the previous embodiment. The negative conduction path 24 corresponds to the first conduction path 21 in the previous specific embodiment, and the second conduction path 22 corresponds to the second conduction path 22 in the previous embodiment. It can be seen that in this embodiment, it is equivalent to the series connection of two capacitance arrays in the previous embodiment, and from the above connection relationship and Figure 16 It can also be seen that in this embodiment, the positive capacitance array C1 and the negative capacitance array C2 are connected in series. The positive capacitance array and the negative capacitance array share three connection terminals (BUS+, N, BUS-), and also share the second conduction path 22 and the third conduction path 23 on the conduction path, realizing current sharing among the capacitors in the positive capacitance array and current sharing among the capacitors in the negative capacitance array, while reducing the connection path between the capacitors and reducing the wiring difficulty.

[0062] In another embodiment of the present application, a power component is provided, such as Figure 4 As shown, the power component 300 includes the aforementioned capacitance component 100 and a power conversion circuit 3.

[0063] Figure 4 In, the capacitance component 100 and the power conversion circuit 3 are arranged on the same PCB board. In other embodiments, the capacitance component 100 and the power conversion circuit 3 that make up the power component 200 can be arranged on different PCB boards respectively or arranged as multiple PCB boards, which can be set by those skilled in the art according to needs and will not be limited herein.

[0064] In this embodiment, the power conversion circuit 3 may include a plurality of conversion bridge arms 31. The capacitance pool further includes at least one first positive capacitance array 41 and at least one first negative capacitance array 42. The first positive capacitance array 41 and the first negative capacitance array 42 are alternately arranged, and each conversion bridge arm 31 is arranged between the first positive capacitance array 41 and the first negative capacitance array 42.

[0065] Exemplarily, please refer to Figure 5 , the number of conversion bridge arms 31 is three. The three conversion bridge arms 31 can form three parallel conversion bridge arms or can respectively correspond to the three phases of a three-phase circuit, which will not be limited herein. FromFigure 5 It can be seen that the three conversion bridge arms 31 are arranged in sequence along the first direction, and a first positive capacitance array 41 and a first negative capacitance array 42 are respectively arranged on both sides of each conversion bridge arm 31. In this embodiment, the first positive capacitance array 41 and the first negative capacitance array 42 are collectively referred to as the first capacitance array, and the number of first capacitors included in each first capacitance array is different. In other embodiments, the number of capacitors included in each bus capacitance array may be the same.

[0066] Figure 5 In the power component shown, in this embodiment, the capacitor bank includes electrolytic capacitors ( Figure 5 schematically shown as small circles) and thin-film capacitors ( Figure 5 schematically shown as small squares). Among them, the electrolytic capacitors form the aforementioned positive capacitance array and negative capacitance array, and the thin-film capacitors form the aforementioned first positive capacitance array and first negative capacitance array. In other embodiments, both the electrolytic capacitors and the thin-film capacitors can form the aforementioned capacitance array, positive capacitance array, negative capacitance array, first positive capacitance array, and first negative capacitance array, which are not limited herein.

[0067] In this embodiment, the conversion bridge arm is a multi-level bridge arm, and the two multi-level bridge arms distributed on both sides of the first capacitance array are mirror-symmetrical in layout. The first capacitance array includes a first positive capacitance array and a first negative capacitance array. More specifically, the multi-level bridge arm can be a T-type three-level bridge arm or an I-type three-level bridge arm.

[0068] Specifically, as shown in Figure 6 ( Figure 6 the electrolytic capacitors are not schematically shown, which does not mean there are no electrolytic capacitors), the area where the multiple switching devices constituting the conversion bridge arm 31 are located is defined as the core device area. The multiple switching devices and decoupling capacitors are all located within the core device area, and the capacitor bank is located outside the core device area, and the conversion bridge arms located on both sides of the first capacitance array (the first positive capacitance array 41 or the first negative capacitance array 42) are mirror-symmetrical.

[0069] In this embodiment, the first positive capacitance array and the first negative capacitance array are respectively arranged on both sides of the conversion bridge arm, so that there are a large number of small capacitors in parallel nearby in the commutation loop of the positive half-cycle or negative half-cycle of each conversion bridge arm, with a short path, small stray inductance, and small reverse peak.

[0070] In this embodiment, the multi-level bridge arm further includes a decoupling capacitor. The decoupling capacitor is arranged in the core device area, and both ends of the decoupling capacitor are respectively connected in parallel with the positive capacitance array or the negative capacitance array. Among them, the core device area is the device area surrounded by the multiple switching devices constituting the multi-level bridge arm.

[0071] The conversion bridge arm is taken as a T-type three-level bridge arm and an I-type three-level bridge arm as examples below to further illustrate the conversion bridge arm.

[0072] The connection relationship of the T-type three-level bridge arm is as Figure 7 shown. The multiple switching devices constituting the T-type three-level bridge arm include a first switching device 311, a second switching device 312, a third switching device 313, and a fourth switching device 314. The bus capacitors include a first bus capacitor 315 and a second bus capacitor 316. The first switching device 311 and the fourth switching device 314 are connected in series to form a vertical tube bridge arm. The second switching device 312 and the third switching device 313 are connected in series to form a horizontal tube bridge arm. The first bus capacitor 315 and the second bus capacitor 316 are connected in series to form a capacitor bridge arm. Among them, the common point of the first switching device 311 and the fourth switching device 314 is used as the output point (i.e., the AC terminal). The common point of the first bus capacitor 315 and the second bus capacitor 316 is used as the midpoint O. The two free ends of the vertical tube bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm. The first end of the horizontal tube bridge arm is respectively connected to the neutral point, and the second end is connected to the output point. The two free ends of the capacitor bridge arm are also respectively connected to the positive and negative ends of the power supply. The decoupling capacitor is connected across the free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm.

[0073] The connection relationship of the I-type three-level bridge arm is as Figure 8 shown. The multiple switching devices constituting the I-type three-level bridge arm include a first switching device 311, a second switching device 312, a third switching device 313, a fourth switching device 314, a first diode 321, and a second diode 322. The bus capacitors include a first bus capacitor 315 and a second bus capacitor 316. The first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314 are sequentially connected in series to form an I-type bridge arm. The first bus capacitor 315 and the second bus capacitor 316 are connected in series to form a capacitor bridge arm. The first diode 321 and the second diode 322 are connected in series to form a diode bridge arm. Among them, the common point of the first switching device 311 and the second switching device 312 is used as the first connection point. The common point of the second switching device 312 and the third switching device 313 is used as the output point. The common point of the third switching device 313 and the fourth switching device 314 is used as the second connection point. The common point of the first bus capacitor 315 and the second bus capacitor 316 is used as the midpoint O. The two free ends of the I-type bridge arm are respectively connected in parallel with the two free ends of the capacitor bridge arm. The two free ends of the diode bridge arm are respectively connected to the first connection point and the second connection point. The common point of the diode bridge arm is connected to the midpoint O. The decoupling capacitor is connected between the free end of the I-type bridge arm and the common point of the diode bridge arm.

[0074] Figure 8 (a), the decoupling capacitor includes a first decoupling capacitor 317 and a second decoupling capacitor 318. In a specific embodiment, please refer toFigure 5 , a first decoupling capacitor 317 is connected between the free end of the first switching device 311 and the anode of the first diode 321, and a second decoupling capacitor 318 is connected between the free end of the fourth switching device 314 and the cathode of the second diode 322; Figure 8 In (b), the first decoupling capacitor 317 is connected between the free end of the first switching device 311 and the cathode of the second diode 322, and the second decoupling capacitor 318 is connected between the free end of the fourth switching device 314 and the anode of the first diode 321. Compared with Figure 8 the connection scheme of the decoupling capacitor in (a), Figure 8 the commutation path in (b) is shorter.

[0075] As described above Figure 7 and Figure 8 it can be seen that the two ends of the decoupling capacitor are respectively connected in parallel with the first bus capacitor 315 (i.e., the positive capacitor array) or the second bus capacitor 316 (i.e., the negative capacitor array). It should be noted that the conventional T-type three-level bridge arm and I-type three-level bridge arm do not include decoupling capacitors. In the present invention, the addition of decoupling capacitors is used to shorten the commutation loop, which can effectively reduce the stray inductance of the commutation path and reduce the reverse peak.

[0076] It should be noted that Figure 7 and Figure 8 show the example where the first switching device 311 to the fourth switching device 314 are all IGBT devices. In other embodiments, the first switching device 311 to the fourth switching device 314 can also be formed by selecting other types of switching devices / switching device combinations, such as MOS, BJT, HBT, diodes, etc. At the same time, each switching device can include a single transistor or multiple transistors.

[0077] At the same time, in Figure 7 and Figure 8 , the electrolytic capacitor includes a first electrolytic capacitor 317 and a second electrolytic capacitor 18. The first electrolytic capacitor 317 is connected in parallel with the first bus capacitor 315, and the second electrolytic capacitor 318 is connected in parallel with the second bus capacitor 316. It should be noted that the aforementioned capacitor array, positive capacitor array, negative capacitor array, first positive capacitor array, and first negative capacitor array can all be used to form the first bus capacitor 317 or the second bus capacitor 318.

[0078] In the above description, the capacitance value of the decoupling capacitor satisfies: the current division of the decoupling capacitor for the ripple of the reverse peak current > the current division of the decoupling capacitor for the power frequency ripple current, and the current division of the decoupling capacitor for the ripple of the reverse peak current > the current division of the decoupling capacitor for the switching frequency ripple current.

[0079] It should be noted that there are mainly three types of ripple currents in the conversion bridge arm 31: (1) power frequency ripple current; (2) switching frequency ripple current; (3) reverse peak ripple current (which can also be said to be commutation current). The frequencies of these three types of ripple currents are different, and the frequency of the power frequency ripple < the frequency of the switching frequency ripple < the frequency of the reverse peak ripple (generally, the frequency of the power frequency ripple is 50 Hz or 60 Hz and its multiples, the frequency of the switching frequency ripple is 10 kHz - 100 kHz, and the frequency of the reverse peak ripple is 1 MHz - 10 MHz). Through experiments, it is found that capacitors of different types and different capacitance values have different passing amounts for the three different frequency ripples. Capacitors with a small capacitance value have a larger passing amount for high switching frequencies. The capacitance value of the decoupling capacitor needs to allow the reverse peak ripple current to pass well, while having a smaller passing amount for the power frequency ripple current and the switching frequency ripple current. Therefore, the capacitance value of the decoupling capacitor cannot be too large, otherwise it is easy to distribute too much switching frequency current, resulting in capacitor overheating.

[0080] In a specific scenario, the capacitance value of the decoupling capacitor for "a commutation path used to shorten the switching process from one current loop to another current loop" is 0.47 μF. For the bus capacitor corresponding to absorbing the power frequency ripple current, the capacitance value can be 470 μF. Electrolytic capacitors are selected, which are large in volume and are set in a more peripheral area. They can be composed of multiple capacitors in parallel. For the bus capacitor corresponding to absorbing the switching frequency ripple current, the capacitance value can be 12 μF. Generally, film capacitors are used and are also set in a more peripheral area, and they can be composed of multiple capacitors in parallel. Through experimental verification, the 0.47 μF decoupling capacitor has almost no current division for the power frequency ripple current, about 1% current division for the switching frequency ripple current, and about 99% current division for the reverse peak ripple current. The 12 μF bus capacitor has about 95% current division for the switching frequency ripple current and about 1% current division for the reverse peak ripple current. The 0.47 μF decoupling capacitor has almost no current division for the reverse peak ripple current and about 99% current division for the power frequency ripple current. It can be seen that the reverse peak ripple current (i.e., commutation current) mainly passes through the decoupling capacitor. The above capacitance value and experimental data are only a set of values during the inventor's experiment, and cannot limit the only value range of the capacitance value of this application, nor can it limit the current division of different capacitors for different ripple currents as measured in the experiment. It should be understood based on the inventive concept of the present invention.

[0081] In summary, by introducing a decoupling capacitor in the embodiment of the present application, the commutation path length during the switching process from the median freewheeling loop to the reverse freewheeling loop can be reduced, thereby reducing the reverse peak and prolonging the device life.

[0082] In another embodiment of the present application, a converter is provided, and the converter includes the aforementioned capacitor assembly 100, or, the aforementioned power assembly 200.

[0083] The following takes the T-type three-level arm (i.e., the structure shown in Figure 7 ) as an example to provide several specific layouts for reference and understanding.

[0084] In some embodiments, the layout of the T-type three-level arm can be as shown in Figure 6 (hereinafter referred to as the T-type layout). In this layout, the first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314 present a T-type layout; the first switching device 311 and the fourth switching device 314 form the short sides of the T-type layout; the second switching device 312 and the third switching device 313 form the long sides of the T-type layout; the third switching device 313 is close to the short side of the T-type layout, and the second switching device 312 is far from the long side of the T-type layout.

[0085] It should be noted that in the T-type layout, even the commutation path via the bus capacitor itself is relatively short, and the reverse peak is relatively low. And when wiring the PCB multi-layer board, it is easy to achieve that there is an overlapping area in the projection direction for the two conduction paths on different wiring layers between the switching devices, and the included angle of the current directions in the overlapping area is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths are superimposed and cancelled each other, so the stray inductances generated by the two conduction paths are also cancelled each other, and the induced voltage △V generated is reduced, thereby reducing the reverse peak, avoiding permanent damage to the switching device, and improving the circuit life.

[0086] In addition, for the T-type layout, the first decoupling capacitor 317 and the second decoupling capacitor 318 are located between the first switching device 311, the fourth switching device 314, and the third switching device 313; one of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the first switching device 311 far from the fourth switching device 314, and the other of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the fourth switching device 314 far from the first switching device 311.

[0087] In this way, the first decoupling capacitor 317 is arranged between the first switching device 311 and the third switching device 313, and the second decoupling capacitor 318 is arranged between the fourth switching device 314 and the third switching device 313. Therefore, the commutation paths passing through the first decoupling capacitor 317 and the second decoupling capacitor 318 are further shortened, thereby reducing the reverse peak.

[0088] As described above, each switching device may include a single transistor or multiple transistors. In the case where each switching device includes multiple transistors, please refer to Figure 6, the second switching device 312 includes four second transistors, and the four second transistors are arranged in a trapezoidal distribution; the third switching device 313 includes four third transistors, and the four third transistors are arranged in a 2×2 array distribution; the first switching device 311 includes three first transistors, and the three first transistors are arranged in a triangular distribution; the fourth switching device 314 includes three fourth transistors, and the three fourth transistors are arranged in a triangular distribution (the specific shape of the triangle is not limited, such as a right triangle or an isosceles triangle); a first decoupling capacitor 317 and a second decoupling capacitor 318 are placed in the area surrounded by the first transistor at the top of the triangle, the fourth transistor at the top of the triangle, and the four third transistors.

[0089] In this way, the decoupling capacitors do not occupy additional area and can better reduce the reverse peak.

[0090] Please refer to Figure 9 , a second layout of the T-type three-level bridge arm is provided. The first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314 are arranged in a rectangular layout; the first switching device 311 and the fourth switching device 314 are arranged along a first direction, and the second switching device 312 and the third switching device 313 are arranged along the first direction; the first switching device 311 and the third switching device 313 are arranged along a second direction, and the second switching device 312 and the fourth switching device 314 are arranged along the second direction.

[0091] The first decoupling capacitor 317 and the second decoupling capacitor 318 are located between the first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314.

[0092] It should be noted that the commutation path of the rectangular layout is shorter than that of the T-type layout, and the first decoupling capacitor 317 and the second decoupling capacitor 318 are also added, so the reverse peak is smaller.

[0093] Please refer to Figure 10 , a third layout of the T-type three-level bridge arm is provided. The first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314 are arranged in a diamond layout; the first switching device 311, the third switching device 313, and the fourth switching device 314 are arranged along a first direction, and the first switching device 311, the second switching device 312, and the fourth switching device 314 are arranged along the first direction; the third switching device 313 and the second switching device 312 are arranged along a second direction; the first decoupling capacitor 317 is located between the second switching device 312 and the third switching device 313 and is placed close to the first switching device 311; the second decoupling capacitor 318 is located between the second switching device 312 and the third switching device 313 and is placed close to the fourth switching device 314.

[0094] As can be seen from the above second and third layouts, the core device area can be divided into a first core device area and a second core device area arranged adjacent to each other. Correspondingly, the multiple switching devices constituting the multilevel circuit are divided into positive half-cycle devices (corresponding to the first switching device 311 and the second switching device 312 in FIGS. 312 and 313) and negative half-cycle devices (corresponding to the fourth switching device 314 and the third switching device 313 in FIGS. 312 and 313). The positive half-cycle switching devices and the first decoupling capacitor are arranged in the first core device area, and the negative half-cycle switching devices and the second decoupling capacitor are arranged in the second core device area, so that the switching devices and the decoupling capacitors with close relationships are more closely arranged in the layout, thereby making the connection path between the switching devices and the decoupling capacitor shorter, further shortening the commutation path, reducing the stray inductance, and lowering the reverse peak.

[0095] Similarly, several specific layouts are provided taking the I-type three-level bridge arm (i.e., the structure shown in Figure 8 as an example for reference and understanding.

[0096] Please refer to Figure 11 , the core device area is divided into a first core device area and a second core device area. Among them, the first switching device 311, the second switching device 312, and the first diode 321 form a triangular layout in the first core device area, and the first decoupling capacitor 317 is arranged inside the triangular layout (the first core device area). The fourth switching device 314, the third switching device 313, and the second diode 322 form a triangular layout in the second core device area, and the second decoupling capacitor 318 is arranged inside the triangular layout (the second core device area). Moreover, the first core device area and the second core device area are mirror-symmetrical. Among them, the fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0097] Furthermore, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the first diode 321) faces the first diode 321, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) faces the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 should be mirror-symmetrical. Then, the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the second diode 322) faces the second diode 322, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) faces the fourth switching device 314.

[0098] In this way, a first decoupling capacitor 317 is arranged between the first switching device 311 and the first diode 321, and a second decoupling capacitor 318 is arranged between the fourth switching device 314 and the second diode 322. Therefore, the commutation paths passing through the first decoupling capacitor 317 and the second decoupling capacitor 318 are further shortened, thereby reducing the reverse peak. And this layout is beneficial to reducing electromagnetic interference and improving the electromagnetic compatibility performance.

[0099] Outside the core device area, a first bus capacitor 315 and a second bus capacitor 316 are arranged. The bus capacitors can be formed by connecting multiple small capacitors in parallel, and their distribution positions can be flexibly selected. As shown in the figure, in this embodiment, both the first bus capacitor and the second bus capacitor can include multiple electrolytic bus capacitors (small circles in the figure) and multiple thin-film bus capacitors (small squares in the figure). The electrolytic bus capacitors and the thin-film bus capacitors together form a capacitor assembly, which is arranged on one side of the core device area.

[0100] In the second specific layout embodiment, please refer to Figure 12 , similarly, the core device area is divided into a first core device area and a second core device area. Among them, the first switching device 311, the second switching device 312, and the second diode 322 form a triangular layout in the first core device area, and the first decoupling capacitor 317 is arranged inside the triangular layout (the first core device area). The fourth switching device 314, the third switching device 313, and the first diode 321 form a triangular layout in the second core device area, and the second decoupling capacitor 318 is arranged inside the triangular layout (the second core device area). And the first core device area and the second core device area are mirror-symmetrical. Among them, the fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0101] More specifically, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the second diode 322) faces the second diode 322, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) faces the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 should be mirror-symmetrical. Then, the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the first diode 321) faces the first diode 321, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) faces the fourth switching device 314.

[0102] In this layout, while inheriting the advantages of the capacitive component, the stress of the commutation loop is relatively small, and when wiring a multi-layer PCB, it is easy to achieve an overlapping area in the projection direction between two conduction paths on different wiring layers of the switching devices, and the included angle of the current directions in the overlapping area is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths are superimposed and cancelled each other, so the stray inductances generated by the two conduction paths are also cancelled each other, the induced voltage △V generated is reduced, and thus the reverse peak is reduced, avoiding permanent damage to the switching devices and improving the circuit life.

[0103] In the third specific layout embodiment, please refer to Figure 13 , the first switching device 311, the second switching device 312 and the second diode 322 form an L-shaped layout in the first core device area, and the second switching device 312 is located at the corner position of the L-shaped layout. The first decoupling capacitor 317 is arranged inside the L-shaped layout (the first core device area). The fourth switching device 314, the third switching device 313 and the first diode 321 form an L-shaped layout in the second core device area, and the second decoupling capacitor 318 is arranged inside the L-shaped layout (the second core device area), and the first core device area and the second core device area are mirror-symmetrical. Among them, the fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0104] More specifically, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the second diode 322) faces the second diode 322, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) faces the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 should be mirror-symmetrical. Then, the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the first diode 321) faces the first diode 321, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) faces the fourth switching device 314.

[0105] In this layout, the stress of the commutation loop is also relatively small.

[0106] In the fourth specific layout embodiment, please refer to Figure 14, the core device area is divided into a first core device area and a second core device area. Among them, the first switching device 311, the second switching device 312, and the first diode 321 form an "I" - shaped layout in the first core device area, and the first diode 321 is placed adjacent to the first switching device 311. The first decoupling capacitor 317 is arranged between the first diode 321 and the first switching device 311. The fourth switching device 314, the third switching device 313, and the second diode 322 form an "I" - shaped layout in the second core device area, and the second diode 322 is placed adjacent to the fourth switching device 314. The second decoupling capacitor 318 is arranged between the second diode 322 and the fourth switching device 314. The first core device area and the second core device area are mirror - symmetric. Among them, the fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0107] Similar to the first layout embodiment, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the first diode 321) faces the first diode 321, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) faces the first switching device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 should be mirror - symmetric. Then, the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the second diode 322) faces the second diode 322, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) faces the fourth switching device 314.

[0108] In this layout embodiment, it also satisfies the advantages of shortening the commutation path and reducing the reverse peak.

[0109] It should be noted that the above Figures 12 to 14 only shows the layout of the core device area (i.e., the conversion bridge arm 31). The layout of the capacitor assembly can be in the structure as shown in Figure 11 or Figure 5 . Figure 11 and Figure 5 only takes three core device areas as an example. In other embodiments, more or fewer can be set, which is not limited here.

[0110] In another embodiment of the present application, a converter is provided. The converter includes the aforementioned capacitor assembly 100 or power assembly 200.

[0111] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. It should be noted that in the present application, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising such element. The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered within the protection scope of the present application.

Claims

1. A capacitor assembly with multiple capacitors connected in parallel, characterized in that: It includes a capacitor pool and a terminal group and a transfer end arranged on a printed circuit board, the terminal group includes a first terminal and a second terminal, the capacitor pool includes at least one capacitor array, each of the capacitor arrays includes a plurality of capacitors connected in parallel, the first ends of the plurality of capacitors and the first terminal are connected to a first conduction path, the second ends of the plurality of capacitors and the transfer end are connected to a second conduction path, and the second terminal and the transfer end are connected to a third conduction path, so that the commutation path from the first terminal to the second terminal after passing through each of the capacitors is of equal length, wherein the first terminal and the transfer end are respectively located on opposite sides of the capacitor pool.

2. The capacitor assembly according to claim 1, characterized in that: The first terminal is the first end of the first capacitor in the capacitor array, and / or the transfer end is the second end of the last capacitor in the capacitor array, wherein the first capacitor and the last capacitor are the two capacitors with the farthest distance in the capacitor array.

3. The capacitor assembly according to any one of claims 1 or 2, characterized in that: The terminal group includes a positive terminal, a neutral terminal and a negative terminal, the capacitor array includes at least one positive capacitor array and at least one negative capacitor array, the first ends of the multiple capacitors of the positive capacitor array and the positive terminal are both connected to the positive conduction path, the second ends of the multiple capacitors of the negative capacitor array and the negative terminal are both connected to the negative conduction path, the second ends of the multiple capacitors of the positive capacitor array, the first ends of the multiple capacitors of the negative capacitor array and the transfer end are all connected to the second conduction path, the neutral terminal and the transfer end are both connected to the third conduction path, wherein the first terminal is the positive terminal or the negative terminal, and the second terminal is the neutral terminal.

4. The capacitor assembly according to claim 3, characterized in that: The positive conduction path, the second conduction path and the third conduction path are respectively located in different wiring layers of the PCB, and the negative conduction path and the positive conduction path are located in the same wiring layer.

5. A capacitor assembly with multiple capacitors connected in parallel, characterized in that: It includes a capacitor pool and a terminal group arranged on a printed circuit board, the terminal group includes a first terminal and a second terminal respectively located on opposite sides of the capacitor pool, the capacitor pool includes at least one capacitor array, each of the capacitor arrays includes a plurality of capacitors connected in parallel, the first ends of the plurality of capacitors and the first terminal are both connected to a first conduction path, and the second ends of the plurality of capacitors and the second terminal are both connected to a second conduction path, so that the commutation path from the first terminal to the second terminal after passing through each of the capacitors is of equal length.

6. A power component, characterized in that: It comprises a power conversion circuit and the capacitor component according to any one of claims 1 to 5, wherein the power conversion circuit is connected to the capacitor component through the terminal group.

7. The power assembly according to claim 6, characterized in that: The power conversion circuit includes multiple conversion bridge arms, the capacitor pool includes at least one first positive capacitor array and at least one first negative capacitor array, the first positive capacitor array and the first negative capacitor array are alternately arranged, and each of the conversion bridge arms is arranged between the first positive capacitor array and the first negative capacitor array.

8. The power assembly according to claim 7, characterized in that: The conversion bridge arm is a multi-level bridge arm, and the two multi-level bridge arms distributed on both sides of the first capacitor array are mirror-symmetrical in layout. The first capacitor array includes a first positive capacitor array and a first negative capacitor array.

9. The power assembly according to claim 8, characterized in that: The multi-level bridge arm also includes a decoupling capacitor, which is arranged in a core device area, and the two ends of the decoupling capacitor are respectively connected in parallel with a positive capacitor array or a negative capacitor array, wherein the core device area is a device area formed by a plurality of switching devices constituting the multi-level bridge arm.

10. A converter, characterized in that: The converter comprises the capacitor component described in any one of claims 1 to 5, or comprises the power component described in any one of claims 6 to 9.

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