Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor device. Background Art

[0002] The integrated ultra-high voltage BCD (also known as UHVBCD) process is widely used in the fields of AC / DC electrical parameter conversion and LED lighting drive. Its main devices are Junction Field-Effect Transistor (JFET) and Lateral Double Diffused Metal Oxide Semiconductor (LDMOS). The latest architecture of the JFET and LDMOS composite structure combines the two, thus reducing the chip area by at least 20%. For example, Figure 2 The chip area of the JFET and LDMOS composite structure with ultra-high voltage in Figure 1 is smaller than that of the chip with independent UHVJFET (ultra-high voltage JFET) and UHVLDMOS (ultra-high voltage LDMOS) in

[0003] In the JFET and LDMOS composite structure, JFETs with a width of about 100 - 300 μm can be placed on the short side of the LDMOS, and the supply current can reach 2 - 6 mA, which can meet most circuit applications. However, the current JFET and LDMOS composite structure still has the following problems:

[0004] On the one hand, the HPW (high-voltage P-well) of the JFET and LDMOS composite structure needs to be used as the triple RESURF (triple reduced surface field) of the LDMOS, and on the other hand, it needs to be used as the B' (HPW bulk region) of the JFET to control Vp (pinch-off voltage). However, the HPW cannot simultaneously meet the performance requirements of the LDMOS and the JFET (the HPW on the LDMOS side requires a low ion doping concentration, and the HPW on the JFET side requires a high ion doping concentration). Therefore, the current JFET and LDMOS composite structure will sacrifice the performance of one aspect (LDMOS or JFET). Summary of the Utility Model

[0005] The purpose of the utility model is to provide a semiconductor device that can simultaneously meet the performance requirements of the LDMOS and the JFET.

[0006] To achieve the above purpose and other related purposes, the utility model provides a semiconductor device, including:

[0007] A semiconductor substrate of a first conductivity type;

[0008] A deep well of a second conduction type, located in the semiconductor substrate;

[0009] A shallow well of a first conduction type, located in the semiconductor substrate outside the deep well of the second conduction type;

[0010] JFET source regions, drain regions, and LDMOS source regions arranged at intervals, the JFET source regions and drain regions are located on the surface of the deep well of the second conduction type, the LDMOS source regions are located on the surface of the shallow well of the first conduction type, and the drain region is located between the JFET source region and the LDMOS source region;

[0011] A field oxide layer, a JFET polysilicon gate, and an LDMOS polysilicon gate, the field oxide layer is located in the deep well of the second conduction type, the JFET polysilicon gate is located on the field oxide layer between the JFET source region and the drain region, and the LDMOS polysilicon gate is located on the field oxide layer between the drain region and the LDMOS source region;

[0012] A high-voltage well of a first conduction type, which includes a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygon matrix.

[0013] Optionally, in the semiconductor device, the second part of the high-voltage well of the first conduction type includes a plurality of sub-high-voltage wells, the cross-sectional shape of each sub-high-voltage well parallel to the surface of the semiconductor substrate is a polygon, and the plurality of sub-high-voltage wells are distributed in a matrix.

[0014] Optionally, in the semiconductor device, the cross-sectional shape of each sub-high-voltage well parallel to the surface of the semiconductor substrate is the same.

[0015] Optionally, in the semiconductor device, the cross-sectional dimensions of each sub-high-voltage well parallel to the surface of the semiconductor substrate are the same.

[0016] Optionally, in the semiconductor device, the shallow well of the first conduction type is also located in the deep well of the second conduction type and longitudinally extends from the surface of the deep well of the second conduction type into the first part of the high-voltage well of the first conduction type.

[0017] Optionally, in the semiconductor device, the semiconductor device further includes an HPW body pole region, a JFET body pole region, and an LDMOS body pole region. The HPW body pole region, the JFET body pole region, and the LDMOS body pole region are all located on the surface of the shallow well of the first conductivity type. The JFET body pole region and the HPW body pole region are spaced apart from the JFET source region, and the JFET source region is located between the JFET body pole region and the HPW body pole region. The LDMOS body pole region is adjacent to the LDMOS source region.

[0018] Optionally, in the semiconductor device, the field oxide layer is located between the JFET body pole region and the JFET source region, between the JFET source region and the HPW body pole region, between the HPW body pole region and the drain region, and between the drain region and the LDMOS source region.

[0019] Optionally, in the semiconductor device, the semiconductor device further includes a spacer region. The spacer region is located below the field oxide layer between the JFET source region and the JFET body pole region, and longitudinally penetrates the deep well of the second conductivity type. And a first part of the high-voltage well of the first conductivity type laterally penetrates the spacer region.

[0020] Optionally, in the semiconductor device, the JFET source region, the LDMOS source region, and the drain region are of the second conductivity type, and the JFET body pole region, the LDMOS body pole region, and the HPW body pole region are of the first conductivity type.

[0021] Optionally, in the semiconductor device, the polarity of the first conductivity type is opposite to the polarity of the second conductivity type.

[0022] Compared with the prior art, the technical solution of the present invention has the following unexpected beneficial effects:

[0023] In the semiconductor device provided by the present invention, the second part of the high-voltage well of the first conductivity type (i.e., the high-voltage well of the first conductivity type in the deep well of the second conductivity type located between the drain region and the LDMOS polysilicon gate) is arranged in a polygonal matrix distribution, so that the ion doping concentration of the second part is reduced, while the ion doping concentration of the first part (i.e., the high-voltage well of the first conductivity type in the deep well of the second conductivity type located between the JFET source region and the drain region) remains unchanged, thereby simultaneously meeting the performance requirements of the LDMOS and the JFET. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of a chip having an independent UHVJFET and UHVLDMOS;

[0025] Figure 2 It is a schematic structural diagram of a chip with a JFET and LDMOS composite structure having ultra-high voltage;

[0026] Figure 3 It is a schematic structural diagram of an existing JFET and LDMOS composite structure;

[0027] Figure 4 It is a top view of the structure of an existing JFET and LDMOS composite structure;

[0028] Figure 5 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 6 It is Figure 5 a schematic structural diagram of the JFET in the semiconductor device in

[0030] Figure 7 It is Figure 5 a schematic structural diagram of the LDMOS in the semiconductor device in

[0031] Figure 8 It is Figure 5 a top view of the structure of the deep well of the second conductivity type in the semiconductor device in

[0032] Figure 9 It is Figure 5 a top view of the structure of the high-voltage well of the first conductivity type in the semiconductor device in

[0033] Figures 1 to 4 In

[0034] 01 - P-type substrate, 02 - N-type deep well, 03 - High-voltage P-type well, 031 - First part, 032 - Second part, 04 - P-type shallow well, 05a - LDMOS doping region, 051 - LDMOS body region, 052 - LDMOS source region, 053 - Drain region, 054 - HPW body region, 055 - JFET source region, 056 - JFET body region, 06 - Field oxide layer, 071 - JFET polysilicon gate, 072 - LDMOS polysilicon gate, 08 - Spacer region, 09 - Contact hole.

[0035] Figures 5 to 9 In

[0036] 10 - Semiconductor substrate, 20 - Deep well of the second conductivity type, 30 - High-voltage well of the first conductivity type, 301 - First part, 302 - Second part, 40 - Shallow well of the first conductivity type, 50a - LDMOS doping region, 501 - LDMOS body region, 502 - LDMOS source region, 503 - Drain region, 504 - HPW body region, 505 - JFET source region, 506 - JFET body region, 60 - Field oxide layer, 701 - JFET polysilicon gate, 702 - LDMOS polysilicon gate, 80 - Spacer, 90 - Contact hole. Detailed implementation mode

[0037] The semiconductor device proposed by the present utility model will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present utility model will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present utility model.

[0038] Refer to Figure 3 and Figure 4, the existing JFET and LDMOS composite structure may include: a P-type substrate 01; an N-type deep well 02; a P-type shallow well 04, located in the N-type deep well 02 and in the P-type substrate 01 outside the N-type deep well 02; the JFET body region 056, JFET source region 055, HPW body region 054, drain region 053, and LDMOS source region 052 are arranged at intervals. The JFET source region 055 and drain region 053 are located on the surface of the N-type deep well 02. The JFET body region 056, HPW body region 054, and LDMOS source region 052 are located on the surface of the P-type shallow well 04, and the drain region 053 is located between the HPW body region 054 and the LDMOS source region 052; the LDMOS body region 051 is located on the surface of the P-type shallow well 04 and is adjacent to the LDMOS source region 052; a field oxide layer 06, a JFET polysilicon gate 071, and an LDMOS polysilicon gate 072. The field oxide layer 06 is located in the N-type deep well 02. The JFET polysilicon gate 071 is located on the field oxide layer 06 between the HPW body region 054 and the drain region 053. The LDMOS polysilicon gate 072 is located on the field oxide layer 06 between the drain region 053 and the LDMOS source region 052. The LDMOS polysilicon gate 072 may also extend and be located on the P-type shallow well 04; a spacer region 08 is located below the field oxide layer 06 between the JFET source region 055 and the HPW body region 054 and penetrates the N-type deep well 02; a high-voltage P-type well (HPW) 03 includes a first part 031 and a second part 032. The first part 031 is located in the N-type deep well 02 between the JFET source region 055 and the drain region 053. The second part 032 is located in the N-type deep well 02 between the drain region 053 and the LDMOS polysilicon gate 072. The ion doping concentration distributions of the first part 031 and the second part 032 are the same. Figure 4The LDMOS doping region 05a in it includes an LDMOS body region 051 and an LDMOS source region 052. The JFET and LDMOS combiner structure further includes a contact hole 09. The JFET body region 056 is connected to the JFET body (J-B) through the contact hole 09. The HPW body region 054 is connected to the HPW body (J-B') through the contact hole 09. The JFET polysilicon gate 071 is connected to the JFET gate (J-G) through the contact hole 09. The JFET source region 055 is connected to the JFET source (J-S) through the contact hole 09. The drain region 053 is connected to the drain (D) through the contact hole 09. The LDMOS body region 051 is connected to the LDMOS body (L-B) through the contact hole 09. The LDMOS polysilicon gate 072 is connected to the LDMOS gate (L-G) through the contact hole 09. The LDMOS source region 052 is connected to the LDMOS source (L-S) through the contact hole 09.

[0039] Since the HPW (the second part 032) on the LDMOS side requires a low ion doping concentration, and the HPW (the first part 031) on the JFET side requires a high ion doping concentration, the existing HPW cannot meet the performance requirements of both the LDMOS and the JFET simultaneously.

[0040] In order to be able to meet the performance requirements of both the LDMOS and the JFET simultaneously, the present utility model provides a semiconductor device. Refer to Figures 5 to 9 , the semiconductor device is a JFET and LDMOS combiner structure, and the semiconductor device may include:

[0041] A semiconductor substrate 10 of a first conductivity type;

[0042] A deep well 20 of a second conductivity type, located in the semiconductor substrate 10;

[0043] A shallow well 40 of a first conductivity type, located in the semiconductor substrate 10 outside the deep well 20 of the second conductivity type;

[0044] The JFET source region 505, the drain region 503, and the LDMOS source region 502 which are spaced apart. The JFET source region 505 and the drain region 503 are located on the surface of the deep well 20 of the second conductivity type. The LDMOS source region 502 is located on the surface of the shallow well 40 of the first conductivity type, and the drain region 503 is located between the JFET source region 505 and the LDMOS source region 502;

[0045] A field oxide layer 60, a JFET polysilicon gate 701, and an LDMOS polysilicon gate 702. The field oxide layer 60 is located in the deep well 20 of the second conductivity type. The JFET polysilicon gate 701 is located on the field oxide layer 60 between the JFET source region 505 and the drain region 503. The LDMOS polysilicon gate 702 is located on the field oxide layer 60 between the drain region 503 and the LDMOS source region 502.

[0046] A high-voltage well 30 of the first conductivity type, which includes a first part 301 and a second part 302. The first part 301 is located in the deep well 20 of the second conductivity type between the JFET source region 505 and the drain region 503. The second part 302 is located in the deep well 20 of the second conductivity type between the drain region 503 and the LDMOS polysilicon gate 702, and the second part 302 is distributed in a polygon matrix.

[0047] Figure 6 The structure of the JFET in the above semiconductor device is shown. Figure 7 The structure of the LDMOS in the above semiconductor device is shown. The JFET and the LDMOS share the drain 503. Moreover, the LDMOS in this embodiment adopts an interdigital planar structure, which can be referred to Figure 8 and Figure 9 , where Figure 8 The top view of the structure of the deep well of the second conductivity type is shown. Figure 9 The top view of the structure of the high-voltage well of the first conductivity type is shown. Figure 8 and Figure 9 The LDMOS doping region 50a in

[0048] In this embodiment, the polarities of the first conductivity type and the second conductivity type are opposite. For example, if the first conductivity type is P-type and the second conductivity type is N-type, then the LDMOS is NLDMOS. It should be known that in other embodiments, the first conductivity type can be N-type and the second conductivity type is P-type. In this embodiment, taking the first conductivity type as P-type and the second conductivity type as N-type as an example, the device of this example is described. Correspondingly, the semiconductor substrate 10 of the first conductivity type is a P-type substrate, the deep well 20 of the second conductivity type is an N-type deep well, the shallow well 40 of the first conductivity type is a P-type shallow well, and the high-voltage well 30 of the first conductivity type is a P-type high-voltage well (i.e., high-voltage P-type well HPW).

[0049] The semiconductor substrate 10 can be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, a silicon carbide substrate, etc., and the semiconductor substrate 10 is a P-type semiconductor substrate. The P-type ion doping concentration can be the same as that of the P-type substrate in the existing JFET and LDMOS composite structures, and will not be elaborated here.

[0050] The deep well 20 of the second conductivity type is formed in the semiconductor substrate 10, and the deep well 20 of the second conductivity type is an N-type deep well. The N-type ion doping concentration can be the same as that of the N-type deep well in the existing JFET and LDMOS composite structures, and will not be elaborated here.

[0051] In this embodiment, the deep well 20 of the second conductivity type is formed in the semiconductor substrate 10 through an ion implantation process. Moreover, after the ion implantation process, a high-temperature baking process is performed to enable the ions in the deep well 20 of the second conductivity type to diffuse into a deeper region, increasing the depth of the deep well 20 of the second conductivity type in the semiconductor substrate 10. The high-temperature baking process can be the same as that of the N-type deep well in the existing JFET and LDMOS composite structures, and will not be elaborated here.

[0052] The semiconductor device in this embodiment may further include a spacer 80. The spacer 80 longitudinally penetrates the deep well 20 of the second conductivity type, and the spacer 80 is located under the field oxide layer 60 between the JFET source region 505 and the HPW body region 504, dividing the deep well 20 of the second conductivity type into two parts. In this embodiment, the spacer 80 is formed simultaneously with the deep well 20 of the second conductivity type. The spacer 80 can be formed simultaneously with the formation of the deep well 20 of the second conductivity type only by adjusting the mask of the deep well 20 of the second conductivity type. During the formation of the deep well 20 of the second conductivity type, the mask used will cover the position of the spacer, so that ion implantation is not performed at the position of the spacer.

[0053] The field oxide layer 60 is formed in the deep well 20 of the second conductivity type, and can also be formed in the shallow well 40 of the first conductivity type. In this embodiment, the number of the field oxide layers 60 can be multiple. Specifically, the field oxide layer 60 is provided between the JFET body region 506 and the JFET source region 505, between the JFET source region 505 and the HPW body region 504, between the HPW body region 504 and the drain region 503, and between the drain region 503 and the LDMOS source region 502. In addition, the field oxide layer 60 can also be located between other different device regions to play an isolation role.

[0054] After the step of forming the deep well 20 of the second conductivity type in this embodiment, the field oxide layer 60 is formed by performing a deposition process or a thermal oxidation process.

[0055] The high-voltage well 30 of the first conductivity type is formed in the deep well 20 of the second conductivity type. The high-voltage well 30 of the first conductivity type includes a first part 301 and a second part 302. The first part 301 is located in the deep well 20 of the second conductivity type between the JFET source region 505 and the drain region 503, and the second part 302 is located in the deep well 20 of the second conductivity type between the drain region 503 and the LDMOS polysilicon gate 702. In this embodiment, the high-voltage well 30 of the first conductivity type is not provided below the drain region 503. The first part 301 adopts an existing design, that is, the ion doping in the first part 301 is continuous and relatively uniform, while the second part 302 adopts a polygon matrix distribution, that is, the second part 302 includes a plurality of sub-high-voltage wells. The cross-sectional shape of each sub-high-voltage well parallel to the surface of the semiconductor substrate 10 is preferably a polygon, and the plurality of sub-high-voltage wells are in a matrix distribution. Refer to Figure 9 , since the LDMOS adopts an interdigital planar structure, its bend region (not serving as the channel of the LDMOS) is prone to breakdown. Therefore, the part of the high-voltage well 30 of the first conductivity type in the bend region can adopt the same design as the first part 301, that is, it is not designed as a polygon matrix distribution.

[0056] The cross-sectional shape of each sub-high-voltage well parallel to the surface of the semiconductor substrate 10 is preferably a polygon, such as a pentagon, a hexagon, etc. In this embodiment, the cross-sectional shapes of each sub-high-voltage well can be the same or different, preferably the same. For example, the cross-sectional shape of each sub-high-voltage well is a hexagon. Further, the shapes of each sub-high-voltage well are also preferably the same. The cross-sectional dimensions of each sub-high-voltage well can be the same or different, preferably the same. In this embodiment, the shapes and sizes of each sub-high-voltage well are the same, and adopting a matrix distribution can make the ion doping concentration distribution in the second part 302 more uniform, and can also increase the size of the depletion region, making the depletion more comprehensive, thereby increasing the BV (breakdown voltage) of the LDMOS.

[0057] In this embodiment, ion implantation is only performed at the position where each sub-high-voltage well is located to achieve ion doping of the second part 302, while the interval region between adjacent sub-high-voltage wells is not deliberately doped, so that the ion doping concentration of the second part 302 is lower, and the ion doping concentration of the first part 301 remains unchanged, that is, the ion doping concentration of the second part 302 is lower than that of the first part 301. In this embodiment, the ion doping concentration of the second part 302 can be adjusted by adjusting the density and cross-sectional size of the sub-high-voltage wells, that is, the ion doping concentration of the second part 302 can be adjusted by adjusting the occupied area ratio of the sub-high-voltage wells (that is, the ratio of the sub-high-voltage wells in the total area of the sub-high-voltage wells and the interval region). The greater the density of the sub-high-voltage wells or the larger the cross-sectional size (that is, the larger the occupied area ratio), the greater the ion doping concentration of the second part 302, and the density and cross-sectional size (occupied area ratio) of the sub-high-voltage wells can be adjusted according to the performance requirements of the LDMOS. For example, according to the performance requirements of the LDMOS, the occupied area ratio of the sub-high-voltage wells is adjusted to be between 50% and 100%. Therefore, the second part 302 adopts a polygonal matrix distribution, which can make the ion doping concentration of the second part 302 relatively low, while the ion doping concentration of the first part 301 remains unchanged, and the performance requirements of both the LDMOS and the JFET can be satisfied, that is, the LDMOS performance can be regulated without affecting the JFET performance.

[0058] After forming the field oxide layer 60 in this embodiment, the high-voltage well 30 of the first conductivity type is formed by an ion implantation process, and after the ion implantation process, a short high-temperature process is performed to activate ions and remove impurities. The high-temperature process can adopt the high-temperature baking process of the high-voltage P-type well of the existing JFET and LDMOS combiner structure, which will not be elaborated here. During the process of forming the high-voltage well 30 of the first conductivity type,

[0059] The mask used will cover the positions outside the first part 301 and the sub-high-voltage wells of the second part 302, so that only the first part 301 and the sub-high-voltage wells of the second part 302 are ion implanted in this embodiment. The high-voltage well 30 of the first conductivity type is a P-type high-voltage well, and the ion implantation parameters of its P-type ions can adopt the ion implantation parameters of the P-type ions of the P-type high-voltage well of the existing JFET and LDMOS combiner structure, which will not be elaborated here. That is, compared with the prior art, the present invention only needs to adjust the mask design of the second part 302, and other parameters can remain unchanged.

[0060] The depth of the shallow well 40 of the first conduction type is lower than that of the deep well 20 of the second conduction type. It is located in the deep well 20 of the second conduction type and longitudinally extends from the surface of the deep well 20 of the second conduction type to the first part 301 of the high-voltage well 30 of the first conduction type. In addition, the shallow well 40 of the first conduction type can also be located in the semiconductor substrate 10 outside the deep well 20 of the second conduction type. The shallow well 40 of the first conduction type is a P-type shallow well, and its P-type ion doping concentration can be the same as that of the P-type shallow well in the existing JFET and LDMOS combiner structures, which will not be elaborated here.

[0061] In this embodiment, after the step of forming the high-voltage well 30 of the first conduction type, the shallow well 40 of the first conduction type is formed by an ion implantation process. Moreover, after the ion implantation process, a short high-temperature process is performed to activate the ions and remove impurities. The temperature of the high-temperature process can be the same as that of the high-temperature process of the P-type shallow well in the existing JFET and LDMOS combiner structures, which will not be elaborated here.

[0062] The JFET polysilicon gate 701 is located on the field oxide layer 60 between the JFET source region 505 and the drain region 503. When the semiconductor device further includes the HPW body region 504, the JFET polysilicon gate 701 is located on the field oxide layer 60 between the HPW body region 504 and the drain region 503. The LDMOS polysilicon gate 702 is located on the field oxide layer 60 between the drain region 503 and the LDMOS source region 502. The materials of the JFET polysilicon gate 701 and the LDMOS polysilicon gate 702 are preferably polysilicon. In this embodiment, the JFET polysilicon gate 701 and the LDMOS polysilicon gate 702 can be P-type or N-type.

[0063] In this embodiment, after the step of forming the shallow well 40 of the first conduction type, the JFET polysilicon gate 701 and the LDMOS polysilicon gate 702 are formed by a deposition process and an etching process.

[0064] The JFET source region 505 and the drain region 503 are located on the surface of the deep well 20 of the second conductivity type. The LDMOS source region 502 is located on the surface of the shallow well 40 of the first conductivity type, and the drain region 503 is located between the JFET source region 505 and the LDMOS source region 502. The semiconductor device may further include a JFET body region 506, an HPW body region 504, and an LDMOS body region 501. The JFET body region 506, the HPW body region 504, and the LDMOS body region 501 are all located on the surface of the shallow well 40 of the first conductivity type. The JFET body region 506 and the HPW body region 504 are spaced apart from the JFET source region 505, and the JFET source region 505 is located between the JFET body region 506 and the HPW body region 504. The LDMOS body region 501 is adjacent to the LDMOS source region 502. In this embodiment, between the JFET body region 506 and the JFET source region 505, between the JFET source region 505 and the HPW body region 504, between the HPW body region 504 and the drain region 503, and between the drain region 503 and the LDMOS source region 502 are all isolated by the field oxide layer 60.

[0065] In this embodiment, after the steps of forming the JFET polysilicon gate 701 and the LDMOS polysilicon gate 702, the JFET body region 506, the JFET source region 505, the HPW body region 504, the drain region 503, the LDMOS source region 502, and the LDMOS body region 501 are formed by multiple ion implantation processes. Moreover, after each ion implantation process, a short high-temperature process is performed to activate the ions and remove impurities. The high-temperature process may adopt the existing high-temperature process for the source, drain, and body regions of the JFET and LDMOS composite structure, which will not be elaborated here. In this embodiment, the JFET source region 505, the LDMOS source region 502, and the drain region 503 are of the second conductivity type, and the JFET body region 506, the LDMOS body region 501, and the HPW body region 504 are of the first conductivity type. Therefore, the JFET source region 505, the LDMOS source region 502, and the drain region 503 in this embodiment can be formed by one ion implantation process, and the JFET body region 506, the LDMOS body region 501, and the HPW body region 504 can be formed by one ion implantation process.

[0066] The semiconductor device of this embodiment further includes a contact hole 90. The JFET body region 506 is connected to the JFET body electrode (J-B) through the contact hole 90. The HPW body region 504 is connected to the substrate gate (J-B') through the contact hole 90. The JFET polysilicon gate 701 is connected to the JFET gate (J-G) through the contact hole 90. The JFET source region 505 is connected to the JFET source (J-S) through the contact hole 90. The drain region 503 is connected to the drain (D) through the contact hole 90. The LDMOS body region 501 is connected to the LDMOS body electrode (L-B) through the contact hole 90. The LDMOS polysilicon gate 702 is connected to the LDMOS gate (L-G) through the contact hole 90. The LDMOS source region 502 is connected to the LDMOS source (L-S) through the contact hole 90. The contact hole 90 adopts the formation process of the contact hole of the existing JFET and LDMOS combiner structure, which will not be elaborated here.

[0067] In summary, in the semiconductor device provided by the embodiment of the present invention, the second part of the high-voltage well of the first conductivity type (i.e., the high-voltage well of the first conductivity type in the deep well of the second conductivity type located between the drain region and the LDMOS polysilicon gate) is arranged in a polygonal matrix distribution, so that the ion doping concentration of the second part is reduced, while the ion doping concentration of the first part (i.e., the high-voltage well of the first conductivity type in the deep well of the second conductivity type located between the JFET source region and the drain region) remains unchanged, thereby meeting the performance requirements of both the LDMOS and the JFET. Moreover, without adding a mask (only adjusting the layout design of the original mask), the present invention can meet the performance of both the NLDMOS and the JFETMOS.

[0068] In addition, it can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the disclosed technical content, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

[0069] It should also be understood that the present utility model is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, and they may vary. It should also be understood that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the present utility model. It must be noted that the singular forms "a", "an", and "the" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means reference to one or more steps and may include sub-steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or", unless the context clearly dictates otherwise. The structures described herein should be understood to also refer to functional equivalents of the structures. Language that may be construed as approximate should be so understood unless the context clearly dictates otherwise.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate of a first conductivity type; A deep well of a second conductivity type, located in the semiconductor substrate; A shallow well of a first conductivity type is located in the semiconductor substrate outside the deep well of the second conductivity type; A JFET source region, a drain region and an LDMOS source region are arranged at intervals, wherein the JFET source region and the drain region are located on the surface of the second conductivity type deep well, the LDMOS source region is located on the surface of the first conductivity type shallow well, and the drain region is located between the JFET source region and the LDMOS source region; A field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, wherein the field oxide layer is located in the deep well of the second conductivity type, the JFET polysilicon gate is located on the field oxide layer between the JFET source region and the drain region, and the LDMOS polysilicon gate is located on the field oxide layer between the drain region and the LDMOS source region; A high-voltage well of the first conductivity type comprises a first part and a second part, wherein the first part is located in a deep well of the second conductivity type between the JFET source region and the drain region, and the second part is located in a deep well of the second conductivity type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix.

2. The semiconductor device according to claim 1, wherein The second part of the first conductivity type high-voltage well includes a plurality of sub-high-voltage wells, each of which has a polygonal cross-sectional shape parallel to the surface of the semiconductor substrate, and the plurality of sub-high-voltage wells are distributed in a matrix.

3. The semiconductor device according to claim 2, wherein: Each of the sub-high-voltage wells has the same cross-sectional shape parallel to the surface of the semiconductor substrate.

4. The semiconductor device according to claim 2, wherein: Each of the sub-high-voltage wells has the same cross-sectional dimensions parallel to the surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein: The shallow well of the first conductivity type is also located in the deep well of the second conductivity type and extends longitudinally from a surface of the deep well of the second conductivity type to a first portion of the high-voltage well of the first conductivity type.

6. The semiconductor device according to claim 1, wherein: The semiconductor device also includes an HPW body region, a JFET body region and an LDMOS body region, wherein the HPW body region, the JFET body region and the LDMOS body region are all located on the surface of the shallow well of the first conductivity type, the JFET body region and the HPW body region are spaced apart from the JFET source region, and the JFET source region is located between the JFET body region and the HPW body region, and the LDMOS body region is adjacent to the LDMOS source region.

7. The semiconductor device according to claim 6, wherein: The field oxide layer is located between the JFET body region and the JFET source region, between the JFET source region and the HPW body region, between the HPW body region and the drain region, and between the drain region and the LDMOS source region.

8. The semiconductor device according to claim 7, wherein: The semiconductor device also includes a spacer region, which is located below the field oxide layer between the JFET source region and the JFET body region and vertically penetrates the second conductivity type deep well, and a first portion of the first conductivity type high voltage well laterally passes through the spacer region.

9. The semiconductor device according to claim 6, wherein: The JFET source region, the LDMOS source region and the drain region are of the second conductivity type, and the JFET body region, the LDMOS body region and the HPW body region are of the first conductivity type.

10. The semiconductor device according to claim 1, wherein The polarity of the first conductivity type is opposite to the polarity of the second conductivity type.

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