Heterojunction battery, laminated battery and battery assembly
By setting a double-layer transparent conductive oxide (TCO) film layer structure on the front and back of the battery body of the heterojunction battery, the problem of high cost caused by the large amount of indium elements in the existing heterojunction battery is solved, and the feasibility of large-scale mass production of the battery is achieved, and the anti-reflection effect of the battery is improved.
Patent Information
- Application Number
- CN202422125417.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2034-08-30
AI Technical Summary
The existing heterojunction batteries use a large amount of indium, which leads to high production costs and limits the large-scale mass production of batteries.
A two-layer structure is adopted in which the front anti-reflection layer and the first TCO layer are arranged on the front surface of the main body of the cell. The thickness of the first TCO layer is reduced to 20 nanometers to 30 nanometers, and the second TCO layer is arranged on the back surface, and the thickness is also reduced to reduce the use of indium elements.
When the electrical performance parameters of traditional ITO film layers are comparable to those of the battery, the use of indium elements is reduced, the production cost is controlled, the limitation of large-scale battery production is reduced, and the anti-reflection effect of the TCO layer is improved.
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Figure CN223007839U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of solar power generation, and particularly relates to a heterojunction battery, a tandem battery and a battery module. Background Art
[0002] A tandem battery is a kind of optoelectronic semiconductor thin sheet that directly generates electricity using sunlight. As long as it is illuminated by light with a certain illuminance condition, it can output voltage and generate current in the case of a loop. Among them, the heterojunction tandem battery is known as the next-generation high-efficiency battery technology with the most industrial potential because of a series of advantages such as high conversion rate, simple manufacturing process, application of thin silicon wafers, low temperature coefficient, and double-sided power generation.
[0003] In a homojunction silicon tandem battery, silicon nitride is usually used as an anti-reflection (AR) coating. For a heterojunction silicon tandem battery, the design of a TCO (transparent conductive oxide) film layer can also achieve this purpose. At the same time, since the upper surface of the battery is a TCO film layer and the TCO on the surface of the heterojunction battery has conductive properties, PID (Potential Induced Degradation) will not occur.
[0004] Currently, in the mainstream technical route of HJT (Heterojunction with Intrinsic Thin film) batteries, ITO (Indium Tin Oxides) includes In2O3 (indium oxide) and Sn2O3 (tin oxide). It has high transmittance, high mobility, and excellent electrical conductivity, so it can be used as the preferred material for the TCO film layer. However, the existing heterojunction batteries use a single-layer ITO film layer with a thickness of 70 to 80 nanometers. Since the In element (indium element) is relatively scarce, the preparation cost of the ITO film layer is high, which limits the large-scale mass production of HJT batteries. Summary of the Utility Model
[0005] An embodiment of the utility model provides a heterojunction battery, aiming to solve the problem that the large amount of indium element used in the existing heterojunction battery leads to an increase in cost and thus limits the mass production of the battery.
[0006] The embodiment of the utility model is implemented as follows. A heterojunction battery includes a battery chip main body, a front anti-reflection layer, and a first TCO layer. The first TCO layer is disposed on the front of the battery chip main body, and the front anti-reflection layer is disposed on the side of the first TCO layer away from the battery chip main body. The thickness of the first TCO layer is 20 to 30 nanometers.
[0007] Further, the heterojunction battery further includes a back antireflection layer and a second TCO layer. The second TCO layer is disposed on the back surface of the battery cell body, and the back antireflection layer is disposed on a side of the second TCO layer away from the battery cell body. The thickness of the second TCO layer is 20 nanometers to 30 nanometers.
[0008] Further, the first TCO layer is an IWO layer, and the second TCO layer is an ITO layer.
[0009] Further, the thicknesses of both the front antireflection layer and the back antireflection layer are 40 nanometers to 60 nanometers.
[0010] Further, both the front antireflection layer and the back antireflection layer are silicon oxide or aluminum oxide.
[0011] Further, the battery cell body includes an n-type amorphous silicon thin film, a first i-type amorphous silicon thin film, a silicon substrate, a second i-type amorphous silicon thin film, and a p-type amorphous silicon thin film that are sequentially distributed from top to bottom. The first TCO layer is disposed on a side of the n-type amorphous silicon thin film away from the first i-type amorphous silicon thin film, and the second TCO layer is disposed on a side of the p-type amorphous silicon thin film away from the second i-type amorphous silicon thin film.
[0012] Further, pyramid textures are provided on the front and / or back surfaces of the silicon substrate.
[0013] In a second aspect, the present application further provides a stacked battery, and the stacked battery includes the heterojunction battery as described above.
[0014] In a third aspect, the present application further provides a battery module, and the battery module includes the stacked battery as described above.
[0015] In a fourth aspect, the present application further provides a battery module, and the battery module includes the heterojunction battery as described above.
[0016] The beneficial effects of the present application are as follows. The heterojunction battery provided by the present application includes a battery cell body, a front antireflection layer, and a first TCO layer. The first TCO layer and the front antireflection layer are sequentially disposed on the front surface of the battery cell body. Compared with the conventional heterojunction battery using an ITO film layer with a thickness of 70 nanometers to 80 nanometers, by providing a double-layer structure of the front antireflection layer and the first TCO layer on the front surface of the battery cell body in the present application, when the battery electrical performance parameters are equivalent to those of the conventional ITO film layer with a thickness of 70 nanometers to 80 nanometers, the thickness of the first TCO layer is reduced to 20 nanometers to 30 nanometers, the usage amount of indium elements is reduced, the production cost is controlled, and the limitation of large-scale battery production is reduced. In addition, by introducing the front antireflection layer on the basis of the first TCO layer, the surface of the first TCO layer can be effectively passivated, the mobility and conductivity of the first TCO layer can be improved, and thus the antireflection effect of the first TCO layer can be enhanced. Description of the Drawings
[0017] Figure 1 It is a schematic structural diagram of an embodiment of the heterojunction battery provided by this application.
[0018] Among them, 100 is the main body of the battery cell; 110 is the n-type amorphous silicon thin film; 120 is the first i-type amorphous silicon thin film; 130 is the silicon substrate; 140 is the first i-type amorphous silicon thin film; 150 is the p-type amorphous silicon thin film; 200 is the front antireflection layer; 300 is the first TCO layer; 400 is the back antireflection layer; 500 is the second TCO layer. Detailed implementation manners
[0019] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation to the present utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0020] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model.
[0021] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present utility model, "a plurality" means two or more, unless otherwise specifically defined.
[0022] In the description of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0023] In the present utility model, unless otherwise clearly specified and defined, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may also include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on the top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "under" and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.
[0024] The following disclosure provides many different embodiments or examples for implementing different structures of the present utility model. To simplify the disclosure of the present utility model, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present utility model. In addition, the present utility model may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed. In addition, the present utility model provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.
[0025] The heterojunction battery provided by the present application includes a battery chip main body, a front antireflection layer and a first TCO layer. The first TCO layer and the front antireflection layer are sequentially arranged on the front of the battery chip main body. Compared with the traditional heterojunction battery using an ITO film layer with a thickness of 70 nanometers to 80 nanometers, by providing a double-layer structure of the front antireflection layer and the first TCO layer on the front of the battery chip main body in the present application, when the electrical performance parameters are equivalent to those of the traditional battery with an ITO film layer having a thickness of 70 nanometers to 80 nanometers, the thickness of the first TCO layer is reduced to 20 nanometers to 30 nanometers, the usage amount of indium element is reduced, the production cost is controlled, and the limitation of large-scale mass production of the battery is reduced. In addition, by introducing the front antireflection layer on the basis of the first TCO layer, the surface of the first TCO layer can be effectively passivated, the mobility and conductivity of the first TCO layer are improved, and thus the antireflection effect of the first TCO layer is enhanced.
[0026] Embodiment 1
[0027] As Figure 1As shown in the figure, an embodiment of the present application provides a heterojunction battery, which includes a battery chip body 100, a front antireflection layer 200, and a first TCO layer 300. The first TCO layer 300 is disposed on the front of the battery chip body 100, and the front antireflection layer 200 is disposed on the side of the first TCO layer 300 away from the battery chip body 100. The thickness of the first TCO layer 300 is 20 nanometers to 30 nanometers.
[0028] In the traditional HJT battery structure, the TCO film layer can be disposed on the front and back of the battery chip body 100, that is, the front TCO film layer and the back TCO film layer. For example, the front TCO film layer is generally a layer of ITO film deposited on the TCO (n-type amorphous silicon thin film 110) of the a-Si:H(n) film layer, and the back TCO film layer is generally a layer of ITO film deposited on the TCO (p-type amorphous silicon thin film 150) of the a-Si:H(p) film layer. That is to say, the traditional TCO film layer is a single-layer ITO film, and the thickness of the single-layer ITO film reaches 70 nanometers to 80 nanometers, and the amount of indium used is relatively large.
[0029] In the heterojunction battery provided by the present application, the front antireflection layer 200 and the first TCO layer 300 are disposed on the front of the battery chip body 100. Among them, the front antireflection layer 200 is an AR coating TCO, which plays an antireflection and light-transmitting enhancement effect, improves the light absorption ability, and further improves the conversion efficiency of the tandem battery. The first TCO layer 300 is a transparent conductive oxide film layer, and the transparent conductive oxide film layer has excellent optoelectronic properties such as a small band gap, low resistivity, high light transmittance in the visible light region, and high light reflectance in the infrared spectral region.
[0030] In some embodiments, the total thickness of the front antireflection layer 200 and the first TCO layer 300 can be set according to the thickness of the traditional TCO film layer. Exemplarily, if the thickness of the TCO film layer of the traditional HJT battery is 70 nanometers to 80 nanometers, then the total thickness of the front antireflection layer 200 and the first TCO layer 300 of the present application can be set to 70 nanometers to 80 nanometers. For example, when the thickness of the traditional TCO film layer is 72 nanometers, the total thickness of the front antireflection layer 200 and the first TCO layer 300 of the present application is 72 nanometers; or when the thickness of the traditional TCO film layer is 75 nanometers, the total thickness of the front antireflection layer 200 and the first TCO layer 300 of the present application is 75 nanometers; or when the thickness of the traditional TCO film layer is 78 nanometers, the total thickness of the front antireflection layer 200 and the first TCO layer 300 of the present application is 78 nanometers, without limitation.
[0031] Since the thickness of the first TCO layer 300 is 20 nanometers to 30 nanometers, for example, the thickness of the first TCO layer 300 can be 21 nanometers, 22 nanometers, 25 nanometers, 26 nanometers, 28 nanometers, or 29 nanometers, etc., without limitation.
[0032] The thickness of the front antireflection layer 200 is 40 nanometers to 60 nanometers. Specifically, the thickness of the front antireflection layer 200 can be adaptively adjusted according to the thickness of the first TCO layer 300. Exemplarily, taking the sum of the thickness of the front antireflection layer 200 and the first TCO layer 300 as 74 nanometers as an example, when the thickness of the first TCO layer 300 is 25 nanometers, the thickness of the front antireflection layer 200 is 49 nanometers; when the thickness of the first TCO layer 300 is 26 nanometers, the thickness of the front antireflection layer 200 is 48 nanometers; when the thickness of the first TCO layer 300 is 27 nanometers, the thickness of the front antireflection layer 200 is 47 nanometers, which is not limited.
[0033] It should be noted that the thickness of the above-mentioned front antireflection layer 200 and the first TCO layer 300 are only examples of the embodiments of the present application, rather than specific limitations on the present application. In some other embodiments, the thickness of the front antireflection layer 200 and the first TCO layer 300 can be determined according to the actual production environment and requirements, without specific limitations.
[0034] The heterojunction battery provided by the present application includes a battery chip main body 100, a front antireflection layer 200, and a first TCO layer 300. The first TCO layer 300 and the front antireflection layer 200 are sequentially arranged on the front of the battery chip main body 100. Compared with the traditional heterojunction battery using an ITO film layer with a thickness of 70 nanometers to 80 nanometers, by providing a double-layer structure of the front antireflection layer 200 and the first TCO layer 300 on the front of the battery chip main body 100 in the present application, when the battery electrical performance parameters are equivalent to those of the traditional ITO film layer with a thickness of 70 nanometers to 80 nanometers, the thickness of the first TCO layer 300 is reduced to 20 nanometers to 30 nanometers, reducing the usage amount of indium elements, controlling production costs, and reducing the limitations of large-scale battery production. In addition, by introducing the front antireflection layer 200 on the basis of the first TCO layer 300, the surface of the first TCO layer 300 can be effectively passivated, improving the mobility and conductivity of the first TCO layer 300, thereby enhancing the antireflection effect of the first TCO layer 300.
[0035] In some alternative embodiments, the heterojunction battery provided by the present application further includes a back antireflection layer 400 and a second TCO layer 500. The second TCO layer 500 is arranged on the back of the battery chip main body 100, and the back antireflection layer 400 is arranged on the side of the second TCO layer 500 away from the battery chip main body 100. The thickness of the second TCO layer 500 is 20 nanometers to 30 nanometers.
[0036] During implementation, the battery chip main body 100 includes a front and a back, and the front and the back are opposite sides. Generally, the light-receiving surface of the battery is called the front, and the side facing away from the sun is the back, which will not be elaborated.
[0037] On the back surface of the cell body 100, an anti-reflection layer 400 and a second TCO layer 500 are provided. The total thickness of the anti-reflection layer 400 and the second TCO layer 500 can be set according to the thickness of the traditional TCO film layer. Exemplarily, if the thickness of the traditional TCO film layer is 70 nm to 80 nm, the total thickness of the anti-reflection layer 400 and the second TCO layer 500 can be set to 70 nm to 80 nm. For example, when the thickness of the traditional TCO film layer is 71 nm, the total thickness of the anti-reflection layer 400 and the second TCO layer 500 in the present application is 71 nm; or when the thickness of the traditional TCO film layer is 73 nm, the total thickness of the anti-reflection layer 400 and the second TCO layer 500 in the present application is 73 nm; or when the thickness of the traditional TCO film layer is 77 nm, the total thickness of the anti-reflection layer 400 and the second TCO layer 500 in the present application is 77 nm, which is not limited.
[0038] Since the thickness of the second TCO layer 500 is 20 nm to 30 nm, for example, the thickness of the second TCO layer 500 can be 21 nm, 23 nm, 24 nm, 25 nm, or 30 nm, etc., which is not limited.
[0039] The thickness of the anti-reflection layer 400 is 40 nm to 60 nm. Specifically, the thickness of the anti-reflection layer 400 can be adaptively adjusted according to the thickness of the second TCO layer 500. Exemplarily, taking the total thickness of the anti-reflection layer 400 and the second TCO layer 500 as 78 nm as an example, when the thickness of the second TCO layer 500 is 28 nm, the thickness of the anti-reflection layer 400 is 50 nm; when the thickness of the second TCO layer 500 is 29 nm, the thickness of the anti-reflection layer 400 is 49 nm; when the thickness of the second TCO layer 500 is 30 nm, the thickness of the anti-reflection layer 400 is 47 nm, which is not limited.
[0040] It should be noted that the thickness of the anti-reflection layer 400 and the thickness of the second TCO layer 500 above are only examples of the embodiments of the present application, rather than specific limitations on the present application. In some other embodiments, the thickness of the anti-reflection layer 400 and the thickness of the second TCO layer 500 can be determined according to the actual production environment and requirements, without specific limitations.
[0041] In some alternative embodiments, the first TCO layer 300 is an IWO layer, and the second TCO layer 500 is an ITO layer.
[0042] During implementation, ITO or IWO is used as a sputtering target in the TCO deposition process. Among them, ITO is an N-type oxide semiconductor - indium tin oxide, and the ITO layer is the ITO thin film, which is an indium tin oxide semiconductor transparent conductive film. IWO is indium oxide doped with tungsten. With the above settings, using the IWO layer on the front side of the cell, compared with the ITO layer arranged on the back side of the cell, the light transmittance of the IWO layer is better than that of the ITO layer, enabling the cell to generate more photo-generated carriers and improving the power generation efficiency.
[0043] The front anti-reflection layer 200 and the back anti-reflection layer 400 can be made of silicon oxide (SiOx) or aluminum oxide. Taking the front anti-reflection layer 200 and the back anti-reflection layer 400 being made of silicon oxide as an example, in this application, introducing SiOx on the front and back sides of the cell can effectively passivate the surfaces of the IWO layer and the ITO layer, improve the mobility and conductivity of the IWO layer and the ITO layer, enhance the anti-reflection effect of the ITO layer and the IWO layer, so as to achieve the same cell electrical performance parameters as those of a traditional ITO film layer with a thickness of 70 nanometers to 80 nanometers; in addition, the reduction of the thickness of the ITO layer and the IWO layer means a significant reduction in the use of indium elements. Compared with the traditional HJT cell structure (for example, the ITO film thickness on both the front and back sides is 75 nanometers), the total consumption of indium elements is reduced by 60% to 70%, greatly reducing the preparation cost of the TCO film layer and providing the possibility for large-scale mass production of HJT in the future.
[0044] In some possible embodiments, the thickness of the first TCO layer 300 and the thickness of the second TCO layer 500 are both 20 nanometers to 30 nanometers, and the thickness of the front anti-reflection layer 200 and the thickness of the back anti-reflection layer 400 are both 40 nanometers to 60 nanometers. For example, when the sum of the thickness of the front anti-reflection layer 200 and the thickness of the first TCO layer 300 is 75 nanometers, the thickness of the first TCO layer 300 is 25 nanometers, and the thickness of the front anti-reflection layer 200 is 50 nanometers, which is not limited.
[0045] In some alternative embodiments, the cell body 100 includes an n-type amorphous silicon thin film 110, a first i-type amorphous silicon thin film 120, a silicon substrate 130, a second i-type amorphous silicon thin film 140, and a p-type amorphous silicon thin film 150 arranged in sequence from top to bottom. The first TCO layer 300 is arranged on the side of the n-type amorphous silicon thin film 110 away from the first i-type amorphous silicon thin film 120, and the second TCO layer 500 is arranged on the side of the p-type amorphous silicon thin film 150 away from the second i-type amorphous silicon thin film 140.
[0046] The n-type amorphous silicon thin film 110 is a-Si:H(n), the first i-type amorphous silicon thin film 120 and the second i-type amorphous silicon thin film 140 are both a-Si:H(i), the silicon substrate 130 is n-Si, and the p-type amorphous silicon thin film 150 is a-Si:H(p). The overall structure of the cell provided in this application from top to bottom is the front antireflection layer 200, the first TCO layer 300, the n-type amorphous silicon thin film 110, the first i-type amorphous silicon thin film 120, the silicon substrate 130, the second i-type amorphous silicon thin film 140, the p-type amorphous silicon thin film 150, the second TCO layer 500, and the back antireflection layer 400.
[0047] Electrically, considering the contact theory, for the TCO / a-Si:H(n) contact (or electron contact), the TCO / doped silicon junction is of the same type. The transport of electrons is simple because it only occurs in the conduction band, so the work function theory is feasible. The work function of the IWO layer material is lower than that of the ITO layer. The IWO layer is selected as the TCO contact layer with a-Si:H(n) on the front side. At the same time, IWO has a higher carrier mobility, which means that the resistivity of the TCO film layer itself is lower and the charge lateral transport ability is stronger, indicating that the cell has a higher FF (Fill Factor). On the other hand, optically, considering the thinning of the front IWO layer, through analysis by optical simulation software, the optical parasitic absorption of the TCO film layer is greatly reduced, but at the same time, the front antireflection effect is also reduced. Introducing SiOx can be used as the second antireflection coating TCO so that the thinner IWO layer absorbs less light. At the same time, due to the influence of hydrogen treatment, the conductivity of the thin IWO layer can be maintained at a level equivalent to that of a single-layer ITO, that is, under the condition of equivalent cell electrical performance parameters, less indium is used in this application.
[0048] In some alternative embodiments, the front and / or back of the silicon substrate 130 is provided with pyramid textures.
[0049] When manufacturing a stacked cell, it is necessary to remove the surface impurities of the silicon wafer (silicon substrate 130) and eliminate the damaged layer TCO on the surface of the silicon wafer. At the same time, to reduce the reflection of light on the surface of the solar cell and increase the absorption of light energy, it is necessary to form a concave-convex structure on the surface of the silicon wafer, that is, it is necessary to perform cleaning and texturing treatment on the surface of the solar cell to form a quadrangular pyramid structure with many crystal planes on the surface of the silicon substrate 130, that is, pyramid textures. This structure is densely distributed on the surface of the stacked cell, like a layer of TCO velvet, so it is called a "textured surface". Through the above settings, the incident light can be reflected and refracted multiple times on the surface, changing the direction of the incident light advancing in the silicon, extending the optical path, generating a light trapping effect, reducing the reflectivity of the silicon wafer surface to less than 10%, and also increasing the generation of photo-generated carriers.
[0050] In some possible embodiments, electrodes 600 are provided on both the front and back sides of the heterojunction battery. The electrode 600 can be a positive electrode or a negative electrode. Generally, the electrode 600 is made of silver, copper or other materials, which will not be elaborated here.
[0051] In this application, a first TCO layer 300 and a front antireflection layer 200 are provided on the front side of the battery cell body 100, and a second TCO layer 500 and a back antireflection layer 400 are provided on the back side of the battery cell body 100. Taking the first TCO layer 300 as an IWO layer and the second TCO layer 500 as an ITO layer as an example, the preparation principle of the heterojunction battery is as follows:
[0052] ①. Use PVD (Physical Vapor Deposition) deposition method to deposit and form the first TCO layer 300 on the front side of the battery cell body 100. Among them, the first preset target is composed of 90 wt% to 98 wt% (mass percentage) of (indium oxide) and 2 wt% to 10 wt% of (tungsten trioxide), and the purity is 99.999%. The first preparation parameters are: DC magnetron sputtering power of 2 Kw to 8 Kw, argon (600 sccm) for sputtering process at a chamber temperature of 120 °C to 200 °C, the initial chamber pressure is 1 × mbar to 1 × mbar (mbar, 1 kg of atmospheric pressure per square centimeter is "1 bar", one-thousandth of "bar" is called "mbar", and one standard atmospheric pressure is equal to 1013 mbar) and the working pressure is 1 × torr to 8 × torr (torr, pressure unit, 760 torr = 1 atm (standard atmospheric pressure)), the sheet resistance is 50 - 500 Ω / □, and the transmittance is 80% - 95%; control the deposition time so that the thickness of the first TCO layer 300 is 20 nanometers to 30 nanometers.
[0053] ②. The preparation method of the second TCO layer 500 is the same as that of the first TCO layer 300, the difference being that the second preset target used for the second TCO layer 500 is composed of 90 wt% to 98 wt% of (indium oxide) and 2 wt% to 10 wt% of tin oxide.
[0054] Exemplarily, when preparing the first TCO layer 300, using the PVD deposition method, the first preset target is composed of 92 wt% of and 8 wt% of. Set the first preparation parameters as: DC magnetron sputtering power of 4 Kw, argon (600 sccm) for sputtering process at a chamber temperature of 130 °C, the initial chamber pressure is 5 × mbar and the working pressure is 4 × torr, the sheet resistance is 70 Ω / □, the transmittance is 85%, and control the deposition time so that the thickness of the first TCO layer 300 is 25 nanometers.
[0055] In some alternative embodiments, when preparing the first TCO layer 300, the PVD deposition method is adopted. The first preset target is composed of 95 wt% of [substance 1] and 5 wt% of [substance 2]. The first preparation parameters are set as follows: the sputtering power of DC magnetron sputtering is 6 Kw, argon (600 sccm) is used for the sputtering process at a chamber temperature of 150 °C, the initial chamber pressure is 8 × 10^-3 mbar, the working pressure is 5 × 10^-3 torr, the sheet resistance is 150 Ω / sq, the transmittance is 88%, and the deposition time is controlled to make the thickness of the first TCO layer 300 29 nanometers.
[0056] In some possible embodiments, when preparing the first TCO layer 300, the PVD deposition method is adopted. The first preset target is composed of 97 wt% of [substance 1] and 3 wt% of [substance 2]. The first preparation parameters are set as follows: the sputtering power of DC magnetron sputtering is 7 Kw, argon (600 sccm) is used for the sputtering process at a chamber temperature of 180 °C, the initial chamber pressure is 9 × 10^-3 mbar, the working pressure is 7 × 10^-3 torr, the sheet resistance is 300 Ω / sq, the transmittance is 90%, and the deposition time is controlled to make the thickness of the first TCO layer 300 30 nanometers.
[0057] Similarly, taking the first TCO layer 300 as an example, when preparing the second TCO layer 500, the PVD deposition method is adopted. The second preset target is composed of 93 wt% of [substance 1] and 7 wt% of [substance 2]. The second preparation parameters are set as follows: the sputtering power of DC magnetron sputtering is 4.5 Kw, argon (600 sccm) is used for the sputtering process at a chamber temperature of 140 °C, the initial chamber pressure is 1 × 10^-3 mbar, the working pressure is 2 × 10^-3 torr, the sheet resistance is 400 Ω / sq, the transmittance is 90%, and the deposition time is controlled to make the thickness of the second TCO layer 500 26 nanometers.
[0058] In some alternative embodiments, when preparing the second TCO layer 500, the PVD deposition method is adopted. The second preset target is composed of 98 wt% of [substance 1] and 2 wt% of [substance 2]. The second preparation parameters are set as follows: the sputtering power of DC magnetron sputtering is 8 Kw, argon (600 sccm) is used for the sputtering process at a chamber temperature of 200 °C, the initial chamber pressure is 5 × 10^-3 mbar, the working pressure is 5 × 10^-3 torr, the sheet resistance is 220 Ω / sq, the transmittance is 93%, and the deposition time is controlled to make the thickness of the second TCO layer 500 31 nanometers.
[0059] In some possible embodiments, when preparing the second TCO layer 500, the PVD deposition method is adopted. The second preset target is composed of 97 wt% of and 3 wt% of. The first preparation parameters are set as follows: the sputtering power of DC magnetron sputtering is 4 Kw, argon (600 sccm) is used for the sputtering process at a chamber temperature of 150 °C, the initial pressure of the chamber is 1×mbar and the working pressure is 5×torr, the sheet resistance is 250 Ω / □, the transmittance is 94%, and the deposition time is controlled so that the thickness of the second TCO layer 500 is 27 nanometers.
[0060] It should be noted that the above-mentioned target and preparation parameters are only examples of the embodiments of the present application, rather than specific limitations on the present application. In some other embodiments, the target and preparation parameters can be determined according to the actual production environment and requirements, and no specific limitations are made.
[0061] Embodiment 2
[0062] In some embodiments, the present application further provides a stacked cell, and the stacked cell includes the heterojunction cell as described above.
[0063] The stacked cell is also called a stacked TCO cell, which stacks and connects multiple small cell wafers in series to form an independent cell, and the small cell wafers are the above-mentioned heterojunction cells.
[0064] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the implementation principle of the stacked cell described above can refer to the corresponding structure and implementation principle in the first embodiment, and will not be repeated here.
[0065] The heterojunction cell provided by the present application includes a cell wafer main body 100, a front antireflection layer 200 and a first TCO layer 300. The first TCO layer 300 and the front antireflection layer 200 are sequentially arranged on the front of the cell wafer main body 100. Compared with the traditional heterojunction cell using an ITO film layer with a thickness of 70 to 80 nanometers, by setting a double-layer structure of the front antireflection layer 200 and the first TCO layer 300 on the front of the cell wafer main body 100 in the present application, when the battery electrical performance parameters are equivalent to those of the traditional ITO film layer with a thickness of 70 to 80 nanometers, the thickness of the first TCO layer 300 is reduced to 20 to 30 nanometers, reducing the usage amount of indium elements, controlling the production cost, and reducing the limitation of large-scale battery production. In addition, by introducing the front antireflection layer 200 on the basis of the first TCO layer 300, the surface of the first TCO layer 300 can be effectively passivated, improving the mobility and conductivity of the first TCO layer 300, thereby enhancing the antireflection effect of the first TCO layer 300.
[0066] In some possible embodiments, the first TCO layer 300 and the front antireflection layer 200 are deposited on the a-Si:H(n) film layer TCO, and the second TCO layer 500 and the back antireflection layer 400 are deposited on the a-Si:H(p) film layer TCO. Therefore, it is necessary to first deposit the first i-type amorphous silicon thin film 120, the second i-type amorphous silicon thin film 140, the n-type amorphous silicon thin film 110, and the p-type amorphous silicon thin film 150 on the silicon substrate 130. The preparation method is as follows:
[0067] The first i-type amorphous silicon thin film 120 and the second i-type amorphous silicon thin film 140 are prepared by PECVD deposition method (Plasma Enhanced Chemical Vapor Deposition). On the front and back surfaces of the silicon substrate 130, i-type amorphous silicon thin films with a thickness of 2 nanometers to 8 nanometers are respectively prepared. The second preparation parameters are that the gas ratio of SiH4 (silane):H2 (hydrogen):B2H4 (diborane) is (1 to 5):(20 to 25):(0.07 to 1), where the content of diborane is 0.7% to 1.5%, the power is 10 mW / cm2 to 20 mW / cm2, the room temperature is 100 °C to 500 °C, and the deposition pressure is 50 mTorr (mTorr is the pressure of micron mercury column, which is one thousandth of the pressure of millimeter mercury column, and 1 mTorr is equal to 0.133 Pa) to 200 mTorr.
[0068] The n-type amorphous silicon thin film 110 is prepared by PECVD deposition method. The thickness of the n-type amorphous silicon thin film 110 is controlled to be 5 nanometers to 20 nanometers. The third preparation parameters can refer to the above second preparation parameters and will not be elaborated.
[0069] The p-type amorphous silicon thin film 150 is also prepared by PECVD deposition method with a thickness of 15 nanometers to 30 nanometers. The preparation conditions are the same as those of the n-type amorphous silicon thin film 110 and will not be elaborated.
[0070] In some embodiments, the i-type amorphous silicon thin film is prepared by PECVD deposition method. On the front and back surfaces of the silicon substrate 130, i-type amorphous silicon thin films with a thickness of 5 nanometers are respectively prepared. Among them, the second preparation parameters are that the gas ratio of SiH4:H2:B2H4 is 3:22:0.09, the content of diborane is 1%, the power is 14 mW / cm2, the room temperature is 200 °C, and the deposition pressure is 100 mTorr.
[0071] The n-type amorphous silicon thin film 110 has a thickness of 10 nanometers and is prepared by PECVD deposition method in an environment where the gas ratio of SiH4:H2:B2H4 is 3:22:0.09, the content of diborane is 1%, the power is 14 mW / cm2, the room temperature is 200 °C, and the deposition pressure is 100 mTorr.
[0072] The thickness of the p-type amorphous silicon thin film 150 is 19 nm. It is deposited by PECVD method under the conditions that the gas ratio of SiH4:H2:B2H4 is 3:22:0.09, the content of diborane is 1%, the power is 14 mW / cm2, the room temperature is 200 °C, and the deposition pressure is 100 mTorr.
[0073] In some alternative embodiments, the i-type amorphous silicon thin film is prepared by PECVD method. The i-type amorphous silicon thin films with a thickness of 6 nm are respectively prepared on the front and back surfaces of the silicon substrate 130. Among them, the second preparation parameters are that the gas ratio of SiH4:H2:B2H4 is 4:24:0.1, the content of diborane is 0.9%, the power is 17 mW / cm2, the room temperature is 450 °C, and the deposition pressure is 150 mTorr.
[0074] The thickness of the n-type amorphous silicon thin film 110 is 12 nm. It is deposited by PECVD method under the conditions that the gas ratio of SiH4:H2:B2H4 is 4:24:0.1, the content of diborane is 0.9%, the power is 17 mW / cm2, the room temperature is 450 °C, and the deposition pressure is 150 mTorr.
[0075] The thickness of the p-type amorphous silicon thin film 150 is 20 nm. It is deposited by PECVD method under the conditions that the gas ratio of SiH4:H2:B2H4 is 4:24:0.1, the content of diborane is 0.9%, the power is 17 mW / cm2, the room temperature is 450 °C, and the deposition pressure is 150 mTorr.
[0076] In some possible embodiments, the i-type amorphous silicon thin film is prepared by PECVD method. The i-type amorphous silicon thin films with a thickness of 5 nm are respectively prepared on the front and back surfaces of the silicon substrate 130. Among them, the second preparation parameters are that the gas ratio of SiH4:H2:B2H4 is 5:21:0.08, the content of diborane is 0.8%, the power is 18 mW / cm2, the room temperature is 250 °C, and the deposition pressure is 170 mTorr.
[0077] The thickness of the n-type amorphous silicon thin film 110 is 11 nm. It is deposited by PECVD method under the conditions that the gas ratio of SiH4:H2:B2H4 is 5:21:0.08, the content of diborane is 0.8%, the power is 18 mW / cm2, the room temperature is 250 °C, and the deposition pressure is 170 mTorr.
[0078] The thickness of the p-type amorphous silicon thin film 150 is 21 nm. It is deposited by PECVD method under the conditions that the gas ratio of SiH4:H2:B2H4 is 5:21:0.08, the content of diborane is 0.8%, the power is 18 mW / cm2, the room temperature is 250 °C, and the deposition pressure is 170 mTorr.
[0079] It should be noted that the preparation processes of the above-mentioned i-type amorphous silicon thin film, n-type amorphous silicon thin film 110, and p-type amorphous silicon thin film 150 are illustrative examples of the embodiments of this application, rather than specific limitations on this application. In some other embodiments, the parameters involved in the preparation processes of the i-type amorphous silicon thin film, n-type amorphous silicon thin film 110, and p-type amorphous silicon thin film 150 can be determined according to the actual production environment and requirements, without specific limitations.
[0080] Embodiment III
[0081] In some embodiments, this application also provides a stacked cell, and the stacked cell includes the heterojunction cell as described above.
[0082] The stacked cell, also known as the stacked TCO cell, is formed by stacking and connecting multiple small cell pieces in series to form an independent cell, and the small cell pieces are the above-mentioned heterojunction cells.
[0083] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the structure and implementation principle of the stacked cell described above can refer to the corresponding structure and implementation principle in the foregoing Embodiment I and Embodiment II, and will not be elaborated here.
[0084] The heterojunction cell provided by this application includes a cell body 100, a front antireflection layer 200, and a first TCO layer 300. The first TCO layer 300 and the front antireflection layer 200 are sequentially disposed on the front of the cell body 100. Compared with the traditional heterojunction cell using an ITO film layer with a thickness of 70 to 80 nanometers, by setting a double-layer structure of the front antireflection layer 200 and the first TCO layer 300 on the front of the cell body 100 in this application, when the battery electrical performance parameters are equivalent to those of the traditional ITO film layer with a thickness of 70 to 80 nanometers, the thickness of the first TCO layer 300 is reduced to 20 to 30 nanometers, reducing the usage amount of indium element, controlling the production cost, and reducing the limitations of large-scale battery production. In addition, by introducing the front antireflection layer 200 on the basis of the first TCO layer 300, the surface of the first TCO layer 300 can be effectively passivated, improving the mobility and conductivity of the first TCO layer 300, thereby enhancing the antireflection effect of the first TCO layer 300.
[0085] Embodiment IV
[0086] In some alternative embodiments, this application also provides a battery module, and the battery module includes the stacked cell as described above.
[0087] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the structure and implementation principle of the battery module described above can refer to the corresponding structure and implementation principle in the foregoing Embodiments I to III, and will not be elaborated here.
[0088] The heterojunction battery provided by the present application includes a battery cell main body 100, a front antireflection layer 200, and a first TCO layer 300. The first TCO layer 300 and the front antireflection layer 200 are sequentially disposed on the front surface of the battery cell main body 100. Compared with the traditional heterojunction battery using an ITO film layer with a thickness of 70 to 80 nanometers, by providing a double-layer structure of the front antireflection layer 200 and the first TCO layer 300 on the front surface of the battery cell main body 100 in the present application, when the battery electrical performance parameters are equivalent to those of the traditional ITO film layer with a thickness of 70 to 80 nanometers, the thickness of the first TCO layer 300 is reduced to 20 to 30 nanometers, reducing the usage amount of indium elements, controlling the production cost, and reducing the limitation of large-scale battery production. In addition, by introducing the front antireflection layer 200 on the basis of the first TCO layer 300, the surface of the first TCO layer 300 can be effectively passivated, improving the mobility and conductivity of the first TCO layer 300, thereby enhancing the antireflection effect of the first TCO layer 300.
[0089] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A heterojunction battery, characterized in that: It includes a battery cell body, a front anti-reflection layer and a first TCO layer, wherein the first TCO layer is arranged on the front side of the battery cell body, the front anti-reflection layer is arranged on a side of the first TCO layer away from the battery cell body, and the thickness of the first TCO layer is 20 nanometers to 30 nanometers.
2. The heterojunction battery according to claim 1, characterized in that: The heterojunction cell further includes a back anti-reflection layer and a second TCO layer, wherein the second TCO layer is disposed on the back of the cell body, and the back anti-reflection layer is disposed on a side of the second TCO layer away from the cell body, and the thickness of the second TCO layer is 20 nanometers to 30 nanometers.
3. The heterojunction battery according to claim 2, characterized in that: The first TCO layer is an IWO layer, and the second TCO layer is an ITO layer.
4. The heterojunction battery according to claim 2 or 3, characterized in that: The thickness of the front anti-reflection layer and the thickness of the back anti-reflection layer are both 40 nanometers to 60 nanometers.
5. The heterojunction battery according to claim 2 or 3, characterized in that: The front anti-reflection layer and the back anti-reflection layer are both silicon oxide or aluminum oxide.
6. The heterojunction battery according to claim 2, characterized in that: The battery cell body includes an n-type amorphous silicon film, a first i-type amorphous silicon film, a silicon substrate, a second i-type amorphous silicon film and a p-type amorphous silicon film which are sequentially distributed from top to bottom, the first TCO layer is arranged on a side of the n-type amorphous silicon film away from the first i-type amorphous silicon film, and the second TCO layer is arranged on a side of the p-type amorphous silicon film away from the second i-type amorphous silicon film.
7. The heterojunction battery according to claim 6, characterized in that: The front side and / or the back side of the silicon substrate is provided with a pyramid texture.
8. A laminated battery, characterized in that: The stacked battery comprises the heterojunction battery according to any one of claims 1 to 7.
9. A battery assembly, characterized in that: The battery assembly comprises the laminated battery as claimed in claim 8.
10. A battery assembly, characterized in that: The battery assembly includes the heterojunction battery according to any one of claims 1 to 7.