Automatic data flow control circuit board for data transceiver

Abstract

The utility model relates to the technical field of industrial automation control, in particular to an automatic data flow control circuit board for data transceiving equipment, which comprises an input signal end, a diode, a resistor, a capacitor, a grounding end, a chip, a power supply end and an OE enabling end, the input signal end, the resistor, the capacitor and the grounding end are sequentially connected in series, the diode is connected with the resistor in parallel, the cathode of the diode is connected with the input signal end, the anode of the diode is connected between the resistor and the capacitor, the chip is respectively connected with the anode of the diode, the grounding end, the power supply end and the OE enabling end through pins of the chip, and the OE enabling end is connected with the data transceiver. The scheme not only is high in real-time performance, but also can effectively avoid data loss and conflicts, realizes automatic and accurate switching of data receiving and transmitting states, and ensures reliability and accuracy of communication.

Description

Technical Field

[0001] The utility model relates to the technical field of industrial automation control, and particularly relates to an automatic data flow control circuit board for a data transceiver device. Background Technique

[0002] The statements in this part are only to provide background information related to the technical solutions of this application to help understanding, and they do not necessarily constitute the prior art for the technical solutions of this application.

[0003] RS-485 communication is widely used in the field of industrial automation, and it uses differential signal transmission mode for data transmission. In an RS-485 network, if the timing of the flow control signal is incorrect, the entire network will not work properly. Therefore, during communication, in order to ensure that the data transmission between the sender and the receiver can be carried out effectively and stably, and to avoid network congestion or resource waste caused by excessive data, flow control methods are usually adopted. The flow control methods include traditional RTS (Request to Send) control and automatic data control. Traditional RTS control uses the RTS signal in the internal circuit of RS-485 to determine sending and receiving, and controls the states of the receiver and the transceiver by setting the RTS state or clearing the RTS signal. Here, the RTS state is controlled by the user software. Automatic data control is to confirm the data sending and receiving states of a 2-wire RS-485 network. Due to some limitations of the RS-485-2W interface, only one node (on a 2-wire RS-485 bus) can transmit signals at any time. At this time, the software can be used to artificially control the RTS signal to switch the data sending and receiving states. However, since software control is limited by software processing capabilities and system resources, it will introduce a large delay and low reliability; in high-speed and large-capacity data transmission, the efficiency is low. Summary of the Utility Model

[0004] Aiming at the disadvantages of software flow control, this application designs an automatic data flow control circuit board using a hardware chip. It directly controls the data flow through hardware signal lines, has a fast response speed, can effectively avoid data loss and conflicts, and can automatically and accurately switch the data sending and receiving states.

[0005] One aspect of the present application relates to an automatic data flow control circuit board for a data transceiver device, which is characterized by including: an input signal terminal, a diode, a resistor, a capacitor, a ground terminal, a chip, a power supply terminal, and an OE enable terminal. The input signal terminal is used to receive signals from the data transceiver device. The input signal terminal, the resistor, the capacitor, and the ground terminal are connected in series in sequence. The diode is connected in parallel with the resistor. The negative electrode of the diode is connected to the input signal terminal, and the positive electrode of the diode is connected between the resistor and the capacitor. The chip is connected to the positive electrode of the diode, the ground terminal, the power supply terminal, and the OE enable terminal respectively through its pins. The OE enable terminal is connected to the data transceiver device.

[0006] In one embodiment, the chip is a single-channel inverter gate circuit chip.

[0007] In one embodiment, the chip is a 74LVC1G04SE-7 chip.

[0008] In one embodiment, the first pin of the 74LVC1G04SE-7 chip is not connected, the second pin is connected to the positive electrode of the diode, the third pin is connected to the ground terminal, the fourth pin is connected to the OE enable terminal, and the fifth pin is connected to the power supply terminal.

[0009] In one embodiment, the power supply terminal provides a voltage of 1.65V - 5.5V for the 74LVC1G04SE-7 chip.

[0010] In one embodiment, the OE enable terminal has two states: low level and high level.

[0011] In one embodiment, the input signal terminal is a TX input signal terminal.

[0012] In the case of half-duplex communication (such as RS-485 half-duplex communication) in the present application, problems are likely to occur in the timing of the flow control signal, resulting in abnormal operation of the communication work. When software is used to control the flow control signal, due to the limitations of software processing capabilities and system resources, a large delay will be introduced, and communication congestion is likely to occur. A new type of automatic data flow control circuit board based on a hardware chip is proposed. It controls the transmission rate and flow direction of data by controlling hardware signal lines. This solution not only has high real-time performance but also can effectively avoid data loss and conflicts, realizing automatic and accurate switching of data transceiver states, ensuring the reliability and accuracy of communication. This solution is particularly suitable for scenarios of automatic data flow control based on RS-485 half-duplex communication in industrial control systems for complex environments and high-speed data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following further describes the embodiments of the present invention with reference to the drawings, where:

[0014] Figure 1 Shows the design diagram of an automatic data flow control circuit board for a data transceiver device according to an embodiment. Detailed implementation mode

[0015] In order to make the purpose, technical solution and advantages of the present utility model clearer, the present utility model will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0016] Figure 1 Shows the design diagram of an automatic data flow control circuit board for a data transceiver device. As Figure 1 shown, the automatic data flow control circuit board for the data transceiver device includes: an input signal terminal 1, a diode 2, a resistor 3, a capacitor 4, a ground terminal 5, a chip 6, a power supply terminal 7, and an OE enable terminal 8 (also referred to as an output enable terminal). The input signal terminal 1 is used to receive signals from a data transceiver device (not shown in the figure). The input signal terminal 1, the resistor 3, the capacitor 4, and the ground terminal 5 are connected in series in sequence. The diode 2 is connected in parallel with the resistor 3. The negative electrode of the diode 2 is connected to the input signal terminal 1, and the positive electrode of the diode 2 is connected between the resistor 3 and the capacitor 4. The chip 6 is connected to the positive electrode of the diode 2, the ground terminal 5, the power supply terminal 7, and the OE enable terminal 8 through its pins respectively. The OE enable terminal (8) is connected to the data transceiver device.

[0017] In one embodiment, the input signal terminal 1 is a TX (Transmit) input signal terminal.

[0018] The on / off of the diode 2 can be used to judge the transceiver state of the data transceiver device. When the communication port of the device is in the transmit state, the input signal terminal 1 is at a low level, and the diode conducts unidirectionally; when the communication port of the device is in the receive state, the input signal terminal 1 is at a high level, and the diode is reversely cut off.

[0019] The diode 2 can be used to protect subsequent circuit elements from voltage spikes. The resistor 3 is used to limit the current passing through the circuit, thereby protecting other elements in the circuit. In the receive state, the capacitor 4 provides an output for the OE enable terminal 8 by continuously charging when it exceeds the threshold set by the chip 6; otherwise, the circuit is not conducting; at the same time, high-frequency noise in the signal is removed, providing a filtering effect.

[0020] In one embodiment, the chip 6 is a single-channel inverter gate circuit chip. In one embodiment, the chip 6 is a 74LVC1G04SE-7 chip. The 74LVC1G04SE-7 chip is a logic gate chip with a single inverter function, which is used for logic circuit design and signal processing on a circuit board. Among them, the first pin of the 74LVC1G04SE-7 chip is not connected and usually remains in an unconnected state. The second pin is the input terminal, the third pin is the power ground terminal of the chip, the fourth pin is the output terminal of the chip, which is logically inverted with the input terminal, and the fifth pin is the positive power supply of the chip, and its operating voltage range is 1.65V - 5.5V.

[0021] In one embodiment, the first pin of the 74LVC1G04SE-7 chip is not connected, the second pin is connected to the positive electrode of the diode 2, the third pin is connected to the grounding terminal 5, the fourth pin is connected to the OE enable terminal 8, and the fifth pin is connected to the power supply terminal 7. The power supply terminal 7 provides a voltage of 1.65V - 5.5V for the 74LVC1G04SE-7 chip.

[0022] The OE enable terminal 8 has two states, namely low level or high level. When the state is high level, the OE enable terminal 8 conducts, so that data can be output; when the state is low level, the OE enable terminal 8 does not conduct, so that data cannot be output.

[0023] Embodiment:

[0024] Wire according to the above description. After wiring is completed, power on the power supply terminal 7. At this time, the 74LVC1G04SE-7 chip 6 remains in an on state, and then the following two situations may occur:

[0025] (1) Sending data: When the data transceiver device is in the sending state, the TX input signal terminal 1 is automatically pulled down to maintain a low level. At this time, the diode 2 conducts unidirectionally. The second pin of the 74LVC1G04SE-7 chip 6 connected to the positive electrode of the diode 2 receives a low level, and the fourth pin connected to the OE enable terminal 8 outputs a high level. Thus, the OE enable terminal 8 is a high-level signal, and the sending data circuit of the data transceiver device is in a conducting state, and the device starts to transmit data to the outside.

[0026] (2) Receiving data: When the data transceiver device is in the receiving state, the TX input signal terminal 1 does not act and remains at a high level. At this time, the diode 2 is in a cut-off state. At this time, the signal will charge the capacitor 4 through the resistor 3. When it exceeds the threshold set by the 74LVC1G04SE-7 chip 6, the OE enable terminal 8 receives a low-level signal, and the receiving data circuit of the data transceiver device is in a conducting state, and the device starts to receive data from the outside.

[0027] References to "each embodiment", "some embodiments", "an embodiment", or "embodiments" in this document refer to a particular feature, structure, or property described in connection with the embodiment being included in at least one embodiment. Thus, the appearances of the phrases "in each embodiment", "in some embodiments", "in an embodiment", or "in embodiments" throughout this document do not necessarily refer to the same embodiment. Additionally, a particular feature, structure, or property may be combined in any suitable manner in one or more embodiments. Therefore, a particular feature, structure, or property shown or described in connection with one embodiment may be combined, in whole or in part, with the features, structures, or properties of one or more other embodiments without limitation, as long as the combination is not illogical or non-functional. Expressions such as "in accordance with A", "based on A", "by A", or "using A" that appear in this document are meant to be non-exclusive. That is, "in accordance with A" can cover "only in accordance with A" or can also cover "in accordance with A and B", unless it is specifically stated that the meaning is "only in accordance with A". For the sake of clarity in this application, some illustrative operating steps are described in a certain order, but those skilled in the art can understand that each of these operating steps is not essential, and some of these steps can be omitted or replaced by other steps. These operating steps do not necessarily have to be executed in the order shown. Instead, some of these operating steps can be executed in a different order according to actual needs or in parallel, as long as the new execution method is not illogical or non-functional.

[0028] Some exemplary embodiments of the present utility model are described above. It can be understood that the above embodiments are only used to explain the present utility model and do not constitute a limitation on the protection scope of the present utility model. The features in these embodiments can be recombined in a suitable manner, and the solutions obtained thereby are still within the protection scope required by the present utility model. Based on the above embodiments, all other embodiments obtained by those skilled in the art without creative efforts, that is, all modifications, equivalent replacements, and improvements made within the spirit and principle of this application, fall within the protection scope required by the present utility model.

Claims

1. An automatic data flow control circuit board for a data transceiver device, characterized in that: include: An input signal terminal (1), a diode (2), a resistor (3), a capacitor (4), a ground terminal (5), a chip (6), a power supply terminal (7), and an OE enable terminal (8). The input signal terminal (1) is used to receive a signal from the data transceiver device. The input signal terminal (1), the resistor (3), the capacitor (4), and the ground terminal (5) are connected in series in sequence. The diode (2) is connected in parallel with the resistor (3). The cathode of the diode (2) is connected to the input signal terminal (1). The anode of the diode (2) is connected between the resistor (3) and the capacitor (4). The chip (6) is connected to the anode of the diode (2), the ground terminal (5), the power supply terminal (7), and the OE enable terminal (8) through its pins. The OE enable terminal (8) is connected to the data transceiver device.

2. The automatic data flow control circuit board according to claim 1, wherein: The chip (6) is a single-channel inverter gate circuit chip.

3. The automatic data flow control circuit board according to claim 1, wherein: The chip (6) is a 74LVC1G04SE-7 chip.

4. The automatic data flow control circuit board according to claim 3, wherein: The first pin of the 74LVC1G04SE-7 chip is not connected, the second pin is connected to the anode of the diode (2), the third pin is connected to the ground terminal (5), the fourth pin is connected to the OE enable terminal (8), and the fifth pin is connected to the power terminal (7).

5. The automatic data flow control circuit board according to claim 4, wherein: The power supply terminal (7) provides a voltage of 1.65V-5.5V for the 74LVC1G04SE-7 chip.

6. The automatic data flow control circuit board according to claim 1, wherein: The OE enable terminal (8) has two states: low level and high level.

7. The automatic data flow control circuit board according to claim 1, wherein: The input signal terminal (1) is a TX input signal terminal.

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