Improved complex programmable logic device, hard disk backboard and server
By designing improved complex programmable logic devices in CPLD and using phase-locked loops to output high-frequency system clocks, the error latch problems caused by insufficient driving capabilities of the clock signal and signal interference are solved, and the effect of registers accurately latch data on the clock edge is achieved.
Patent Information
- Application Number
- CN202422110639.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2034-08-29
AI Technical Summary
In CPLD, the SClock signal of the follow-up clock comes from the GPIO pin, resulting in insufficient signal driving capability, and the register cannot normally latch data on the clock edge, and the SGPIO signal may be disturbed during the inter-board transmission process, resulting in glitches, resulting in latch errors.
An improved complex programmable logic device is designed, including a phase-locked loop, a fast input register group, a secondary register, a signal acquisition register group and a fast output register group. The high-frequency system clock is output through the phase-locked loop, reducing the glitch of the GPIO input signal, and ensuring that the register accurately latch data on the clock edge.
It improves the signal driving capability, ensures that the registers can normally latch data on the clock edge, reduces the risk of false latch, and improves the accuracy and reliability of data transmission.
Smart Images
Figure CN223022681U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of programmable logic devices, in particular to an improved complex programmable logic device, a hard disk backplane and a server. Background Art
[0002] SGPIO (the full name is Serial General-Purpose Input / Output, indicating a serial general input / output bus) is a serial communication protocol, mainly used to connect a computer motherboard and a hard disk backplane. Through the serial communication protocol, not only can the status of the hard disk be monitored and managed, but also information such as the hard disk status and control information of the hard disk backplane can be accessed, such as the hard disk activity indicator, hard disk power control, etc.
[0003] After the SGPIO bus is connected to the hard disk backplane, it usually needs to be connected to a CPLD (the full name is Complex Programmable Logic Device, indicating a complex programmable logic device). In the CPLD, the Target end (i.e., the destination end of the SGPIO bus) is simulated to parse the bus data, and then the control request of the Initiator end (i.e., the initial end of the SGPIO bus) is responded to. The CPLD and the Initiator end of the SGPIO bus are usually on different circuit boards, and their clock signals are not synchronized.
[0004] To solve the above problems, although the SGPIO bus provides a companion clock SClock signal, when there are multiple SGPIO buses to be connected to the CPLD, or when the clock access pin resources of the CPLD are insufficient, the companion clock SClock signal is often connected to the GPIO pin of the CPLD (GPIO full name is General-Purpose Input / Output, indicating a general input / output bus), which leads to the following problems:
[0005] 1) The companion clock SClock signal comes from the GPIO pin of the CPLD, and the driving ability of the signal may be insufficient, resulting in the register being unable to normally latch data at the clock edge.
[0006] 2) During the inter-board transmission of the SGPIO signal, it may be interfered with and generate glitches, resulting in the register mis-latching data.
[0007] 3) The companion clock SClock signal and the data are not synchronized, which will cause different layout positions and routing delays of each data signal in the CPLD. Moreover, when the clock directly samples the data signal, the data may be at the transition time, resulting in data latch error codes. Summary of the Utility Model
[0008] The present utility model provides an improved complex programmable logic device, a hard disk backplane, and a server, aiming to solve the problem that in the prior art, when there are multiple SGPIO buses to be connected to a CPLD or the CPLD clock access pin resources are insufficient, the SClock signal of the follow-up clock comes from the GPIO pin of the CPLD, and the driving ability of the signal may be insufficient, resulting in the register being unable to normally latch data at the clock edge.
[0009] In a first aspect, the present utility model proposes an improved complex programmable logic device, which includes: a phase-locked loop, a fast input register group, a secondary register, a signal acquisition register group, and a fast output register group; wherein, the input end of the phase-locked loop is used to connect to an external clock or input an internal clock, and the output end of the phase-locked loop is connected to the fast input register group, the secondary register, the signal acquisition register group, and the fast output register group; the input end of the fast input register group is connected to a serial general-purpose input / output bus, and the output end of the fast input register group is connected to the input end of the secondary register and the input end of the signal acquisition register group; the output end of the signal acquisition register group is connected to the input end of the fast output register group; the output end of the secondary register is connected to the signal acquisition register group and the fast output register group; the fast output register group is used to output an output signal corresponding to the external clock or the input internal clock.
[0010] Further, the fast input register group includes a first fast input register, a second fast input register, and a third fast input register connected in parallel.
[0011] Further, the D pin of the first fast input register is used to access the serial clock line signal in the serial general-purpose input / output bus, the clk pin of the first fast input register is connected to the output end of the phase-locked loop, and the Q pin of the first fast input register is connected to the D pin of the secondary register; the D pin of the second fast input register is used to access the load signal line signal in the serial general-purpose input / output bus, the clk pin of the second fast input register is connected to the output end of the phase-locked loop, and the Q pin of the second fast input register is connected to the signal acquisition register group; the D pin of the third fast input register is used to access the bus data output signal, the clk pin of the third fast input register is connected to the output end of the phase-locked loop, and the Q pin of the third fast input register is connected to the signal acquisition register group.
[0012] Further, the Q pin of the first fast input register is connected to the first input terminal of the first AND gate, and the Q pin of the secondary register is connected to the second input terminal of the first AND gate through a first NOT gate; wherein, the output terminal of the first AND gate is connected to the fast output register bank.
[0013] Further, the signal acquisition register bank includes a first signal acquisition register and a second signal acquisition register connected in parallel.
[0014] Further, the EN pin of the first signal acquisition register is connected to the output terminal of the second AND gate, the clk pin of the first signal acquisition register is connected to the output terminal of the phase-locked loop, the D pin of the first signal acquisition register is connected to the Q pin of the second fast input register, and the Q pin of the first signal acquisition register is connected to the fast output register bank; the EN pin of the second signal acquisition register is connected to the output terminal of the second AND gate, the clk pin of the second signal acquisition register is connected to the output terminal of the phase-locked loop, the D pin of the second signal acquisition register is connected to the Q pin of the third fast input register, and the Q pin of the second signal acquisition register is connected to the fast output register bank; wherein, the first input terminal of the second AND gate is connected to the Q pin of the secondary register, and the second input terminal of the second AND gate is connected to the Q pin of the first fast input register through a second NOT gate.
[0015] Further, the fast output register bank includes a first fast output register; the D pin of the first fast output register is connected to the output terminal of the first AND gate, the Q pin of the first signal acquisition register, and the Q pin of the second signal acquisition register.
[0016] Further, the Q pin of the first fast output register is used to output the output signal corresponding to the external clock or the input internal clock.
[0017] In a second aspect, the present invention also provides a hard disk backplane, including the improved complex programmable logic device described in the first aspect.
[0018] In a third aspect, the present invention also provides a motherboard, including the improved complex programmable logic device described in the first aspect.
[0019] Compared with the prior art, the present utility model provides an improved complex programmable logic device, a hard disk backplane and a server, including a phase-locked loop, a fast input register bank, a secondary register, a signal acquisition register bank and a fast output register bank; wherein, the input end of the phase-locked loop is used to connect to an external clock or input an internal clock, and the output end of the phase-locked loop is connected to the fast input register bank, the secondary register, the signal acquisition register bank and the fast output register bank; the input end of the fast input register bank is connected to a serial general input / output bus, and the output end of the fast input register bank is connected to the input end of the secondary register and the input end of the signal acquisition register bank; the output end of the signal acquisition register bank is connected to the input end of the fast output register bank; the output end of the secondary register is connected to both the signal acquisition register bank and the fast output register bank; the fast output register bank is used to output an output signal corresponding to the external clock or the input internal clock. The present utility model does not require multiple clock signals to drive multiple registers, improves the driving ability of signals, and the registers can normally latch data at the clock edge. Description of the Drawings
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0021] Figure 1 It is a schematic block diagram of the improved complex programmable logic device provided by the present utility model;
[0022] Figure 2 It is a schematic circuit principle diagram of the improved complex programmable logic device provided by the present utility model;
[0023] Figure 3 It is a rising edge timing diagram of the clock signal on the same path in the improved complex programmable logic device provided by the present utility model;
[0024] Figure 4 It is a falling edge timing diagram of the clock signal on the same path in the improved complex programmable logic device provided by the present utility model;
[0025] Figure 5 It is a schematic block diagram of the hard disk backplane provided by the present utility model;
[0026] Figure 6 It is a schematic block diagram of the server provided by the present utility model. Detailed Embodiments
[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.
[0028] The directional terms mentioned in the present utility model, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model. In addition, in the drawings, structures that are similar or the same are denoted by the same reference numerals.
[0029] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.
[0030] It should also be understood that the terms used in the specification of the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. As used in the specification of the present utility model and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.
[0031] It should be further understood that the term "and / or" used in the specification of the present utility model and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0032] Please refer to Figure 1 which is a schematic block diagram of the improved complex programmable logic device provided by the present utility model. As Figure 1As shown in the figure, the improved complex programmable logic device 10 provided by the embodiment of the present invention includes: a phase-locked loop 110, a fast input register bank 120, a secondary register 130, a signal acquisition register bank 140, and a fast output register bank 150; wherein, the input end of the phase-locked loop 110 is used to connect to an external clock or input an internal clock, and the output end of the phase-locked loop 110 is connected to the fast input register bank 120, the secondary register 130, the signal acquisition register bank 140, and the fast output register bank 150; the input end of the fast input register bank 120 is connected to the serial general-purpose input / output bus 200, and the output end of the fast input register bank 120 is connected to the input ends of the secondary register 130 and the signal acquisition register bank 140; the output end of the signal acquisition register bank 140 is connected to the input end of the fast output register bank 150; the output end of the secondary register 130 is connected to both the signal acquisition register bank 140 and the fast output register bank 150; the fast output register bank 150 is used to output an output signal corresponding to the external clock or the input internal clock.
[0033] In this embodiment, the phase-locked loop 110 is connected to an external clock or inputs an internal clock during specific implementation to receive an external clock signal or obtain an internal clock signal (both the external clock signal and the internal clock signal can be represented by Clk), and after performing frequency multiplication or division processing, it outputs a high-frequency system clock (for example, denoted as Sysclk). The clock frequency of the high-frequency system clock is at least 10 MHz and meets the SGPIO signal sampling requirement of 100 KHz. The high-frequency system clock output by the phase-locked loop 110 is then output to the fast input register bank 120, the secondary register 130, the signal acquisition register bank 140, and the fast output register bank 150. Moreover, sampling the clock signal using the high-frequency system clock can effectively reduce the glitches of the GPIO input signal and avoid mis-sampling of the signal caused by glitches, resulting in data errors. For example, taking the case where the phase-locked loop 110 receives an external clock signal as an example, during the process of the external clock signal being transmitted on the board to the improved complex programmable logic device 10, it is prone to being interfered by the outside world and generating glitches. If the GPIO input signal is directly used as the clock, the internal register will misinterpret the glitches as the rising edge or falling edge of the clock, causing mis-sampling of the signal. The system clock output by the phase-locked loop 110 basically has no glitches, reducing the risk of mis-sampling.
[0034] Among them, the serial general-purpose input / output bus 200 is connected to the fast input register bank 120 through the input pins of the improved complex programmable logic device 10, so that the input signals of the serial general-purpose input / output bus 200 are sampled at the position closest to the input pins after entering the improved complex programmable logic device 10, ensuring that the path delay from the input signals entering the improved complex programmable logic device 10 to the fast input register bank 120 is minimized, and avoiding data desynchronization caused by inconsistent path delays due to random layout.
[0035] The fast output register bank 150 serves as a pre-register for output signals before signal output. It is closest to the output pins of the improved complex programmable logic device 10, ensuring that the path delay from the fast output register bank 150 to the output pins is minimized, and at the same time improving the synchronization accuracy between the output signals and the clock.
[0036] Moreover, after the high-frequency system clock enters the fast input register bank 120, it is at least double-registered by the secondary register 130 or double-registered by the signal acquisition register bank 140, and the output of the secondary register 130 or the output of the signal acquisition register bank 140 is used to obtain effective output signals.
[0037] In one embodiment, as Figure 1 - Figure 2 shown, the fast input register bank 120 includes a first fast input register 121, a second fast input register 122, and a third fast input register 123 connected in parallel.
[0038] In this embodiment, since the serial general-purpose input / output bus 200 connected to the fast input register bank 120 includes at least a serial clock line, a load signal line, and a bus data output / input line, corresponding to the three signal lines included in the serial general-purpose input / output bus 200, the fast input register bank 120 is set as the first fast input register 121, the second fast input register 122, and the third fast input register 123 connected in parallel. Specifically, the serial clock line in the serial general-purpose input / output bus 200 is connected to the first fast input register 121 through an input pin, the load signal line in the serial general-purpose input / output bus 200 is connected to the second fast input register 122 through an input pin, and the line data output / input line in the serial general-purpose input / output bus 200 is connected to the third fast input register 123 through an input pin.
[0039] Of course, in specific implementation, the fast input register bank 120 is not limited to the above 3 parallel fast input registers, and can be determined according to the total number of signal lines required to be connected to the improved complex programmable logic device in the serial general-purpose input / output bus.
[0040] In one embodiment, as Figure 1 - Figure 2 shown, the D pin of the first fast input register 121 is used to access the serial clock line signal in the serial universal input / output bus 200, the clk pin of the first fast input register 121 is connected to the output end of the phase-locked loop 110, and the Q pin of the first fast input register 121 is connected to the D pin of the secondary register 130; the D pin of the second fast input register 122 is used to access the load signal line signal in the serial universal input / output bus, the clk pin of the second fast input register 122 is connected to the output end of the phase-locked loop 110, and the Q pin of the second fast input register 122 is connected to the signal acquisition register group 140; the D pin of the third fast input register 123 is used to access the bus data output signal, the clk pin of the third fast input register 123 is connected to the output end of the phase-locked loop 110, and the Q pin of the third fast input register 123 is connected to the signal acquisition register group 140.
[0041] In this embodiment, the connection method of connecting the Q pin of the first fast input register 121 to the D pin of the secondary register 130, and connecting the Q pins of the second fast input register 122 and the third fast input register 123 to the signal acquisition register group 140 is adopted, so that the serial clock line signal in the serial universal input / output bus 200 is double-registered through the first fast input register 121 and the secondary register 130, and the load signal line signal and the bus data output signal in the serial universal input / output bus 200 are respectively double-registered through the second fast input register 122, the third fast input register 123 and the signal acquisition register group 140. The reason for adding the above double-registration mechanism is to enable the serial clock line signal, the load signal line signal and the bus data output signal to perform logical operations in combination with the outputs of the two-stage registers, so as to obtain more accurate output signals.
[0042] In one embodiment, as Figure 1 - Figure 2 shown, the Q pin of the first fast input register 121 is connected to the first input end of the first AND gate AND1, and the Q pin of the secondary register 130 is connected to the second input end of the first AND gate AND1 through the first NOT gate NOT1; wherein, the output end of the first AND gate AND1 is connected to the fast output register group 150.
[0043] In this embodiment, please refer to Figure 3 for combination, and Figure 3In it, Sysclk represents the high-frequency system clock output by the phase-locked loop 110. The output of the SClock first-stage register refers to the first output corresponding to the Q pin of the first fast input register 121. The output of the SClock second-stage register refers to the second output corresponding to the Q pin of the secondary register 130. The inversion of the SClock second-stage register output refers to the inversion of the second output. The rising edge of SClock refers to the rising edge valid flag SClock_posedge (after the inversion of the second-stage register output and the first-stage register output are both high only in the first clock cycle after the rising edge, that is, they are high only after the AND operation). When establishing the connection relationship between the first fast input register 121, the secondary register 130 and the fast output register group 150 based on the above circuit structure, the Q pin of the first fast input register 121 corresponds to the first output, and the Q pin of the secondary register 130 corresponds to the second output. The second output is inverted first and then ANDed with the first output to obtain Figure 3 the rising edge valid flag SClock_posedge of the clock signal on the same path as shown (i.e., Figure 3 SClock in), and the rising edge valid flag SClock_posedge is used as the enable input of the fast output register group 150, so that the Datain signal (i.e., the data input signal) of the fast output register group 150 is synchronized with the rising edge of the clock signal on the same path.
[0044] In an embodiment, as Figure 1 - Figure 2 shown, the signal acquisition register group 140 includes a first signal acquisition register 141 and a second signal acquisition register 142 connected in parallel.
[0045] In this embodiment, since the second fast input register 122 and the third fast input register 123 in the fast input register group 120 are connected to the signal acquisition register group 140, the number of signal acquisition registers set in the signal acquisition register group 140 is exactly the same as or one less than the number of fast input registers in the fast input register group 120, and the output end of each fast input register is correspondingly connected to a signal acquisition register. Moreover, each signal acquisition register processes signals as the secondary register of the corresponding fast input register.
[0046] Of course, in specific implementation, the signal acquisition register group 140 is not limited to the above 2 signal acquisition registers connected in parallel, and can be determined according to the total number of signal lines required to access the improved complex programmable logic device in the serial universal input / output bus, that is, it is exactly the same as or one less than the number of fast input registers in the fast input register group 120.
[0047] In an embodiment, as Figure 1 - Figure 2As shown, the EN pin of the first signal acquisition register 141 is connected to the output terminal of the second AND gate AND2, the clk pin of the first signal acquisition register 141 is connected to the output terminal of the phase-locked loop 110, the D pin of the first signal acquisition register 141 is connected to the Q pin of the second fast input register 122, and the Q pin of the first signal acquisition register 141 is connected to the fast output register bank 150; the EN pin of the second signal acquisition register 142 is connected to the output terminal of the second AND gate AND2, the clk pin of the second signal acquisition register 142 is connected to the output terminal of the phase-locked loop 110, the D pin of the second signal acquisition register 142 is connected to the Q pin of the third fast input register 123, and the Q pin of the second signal acquisition register is connected to the fast output register bank 150; wherein, the first input terminal of the second AND gate AND2 is connected to the Q pin of the secondary register 130, and the second input terminal of the second AND gate AND2 is connected to the Q pin of the first fast input register 121 through the second NOT gate NOT2.
[0048] In this embodiment, please refer to Figure 4 for reference, and Figure 4 in which Sysclk represents the high-frequency system clock output by the phase-locked loop 110, the output of the first-stage SClock register refers to the third output corresponding to the Q pin of the first fast input register 121, the inversion of the output of the first-stage SClock register refers to the inversion of the third output, the output of the second-stage SClock register refers to the fourth output corresponding to the Q pin of the secondary register 130, and the SClock falling edge refers to the falling-edge valid flag SClock_negedge. When establishing the connection relationship between the first fast input register 121, the secondary register 130, the first signal acquisition register 141, and the second signal acquisition register 142 based on the above circuit structure, the Q pin of the first fast input register 121 corresponds to the third output, and the Q pin of the secondary register 130 corresponds to the fourth output. The third output is inverted first and then ANDed with the fourth output to obtain the falling-edge valid flag SClock_negedge of the clock signal along the path as shown in Figure 4 (i.e., Figure 4 SClock in Figure 4Among them, after the output of the first - stage register is inverted, it is high - level simultaneously with the output of the second - stage register only in the last clock cycle before the falling edge, that is, it becomes high - level only after the AND operation of the two high - levels), and the falling - edge - effective flag SClock_negedge is used as the enable input of the first signal acquisition register 141 and the second signal acquisition register 142 respectively, so that the SLoad signal (i.e., the load signal line signal) of the first signal acquisition register 141 and the Dataout signal (i.e., the data output signal) of the second signal acquisition register 142 are synchronized with the falling edge of the clock signal on the same path.
[0049] In one embodiment, as Figure 1 - Figure 2 shown, the fast output register group 150 includes a first fast output register 151; the D pin of the first fast output register 151 is connected to the output terminal of the first AND gate AND1, the Q pin of the first signal acquisition register 141, and the Q pin of the second signal acquisition register 142.
[0050] In this embodiment, when the fast output register group 150 is specifically implemented, the first fast output register 151 is used. Similar to the first fast input register 121, the second fast input register 122, and the third fast input register 123, it also correspondingly includes a D pin, a clk pin, and a Q pin. Specifically, the D pin of the first fast output register 151 is connected to the output terminal of the first AND gate AND1, the Q pin of the first signal acquisition register 141, and the Q pin of the second signal acquisition register 142 (when specifically implemented, as Figure 3 shown, the output terminal of the first AND gate AND1, the Q pin of the first signal acquisition register 141, and the Q pin of the second signal acquisition register 142 are connected to the D pin of the first fast output register 151 through another processor 160). After the D pin of the first fast output register 151 receives the above three signals, because its output pin is the closest to the output pin, it ensures that the path delay from the first fast output register 151 to the output pin is the lowest.
[0051] In one embodiment, as Figure 1 - Figure 2 shown, the Q pin of the first fast output register 151 is used to output the output signal corresponding to the external clock or the input internal clock.
[0052] In this embodiment, the Q pin of the first fast output register 151 serves as the output pin. After receiving the three signals output from the output terminal of the first AND gate AND1, the Q pin of the first signal acquisition register 141, and the Q pin of the second signal acquisition register 142, it can output the output signal corresponding to the external clock or the input internal clock with the lowest path delay.
[0053] Please refer to Figure 1 and Figure 5 , the present utility model also provides a hard disk backplane 20, which includes the improved complex programmable logic device 10 described in the foregoing embodiment.
[0054] In this embodiment, the hard disk backplane 20 in the embodiment of the present utility model includes the improved complex programmable logic device 10. Among them, the improved complex programmable logic device 10 can refer to the foregoing embodiment. And since the hard disk backplane 20 includes all the technical solutions of the embodiments in the improved complex programmable logic device 10, therefore, the hard disk backplane 20 at least has all the beneficial effects brought by the technical solutions of the foregoing embodiment, and will not be specifically described herein.
[0055] Please refer to Figure 1 、 Figure 5 and Figure 6 , the present utility model also provides a server 30, which includes the improved complex programmable logic device 10 described in the foregoing embodiment, or includes the hard disk backplane 20 described in the foregoing embodiment.
[0056] In this embodiment, the server 30 in the embodiment of the present utility model includes the improved complex programmable logic device 10. Among them, the improved complex programmable logic device can refer to the foregoing embodiment. And since the main board includes all the technical solutions of the embodiments in the improved complex programmable logic device 10, therefore, the server 30 at least has all the beneficial effects brought by the technical solutions of the foregoing embodiment, and will not be specifically described herein.
[0057] The present utility model provides an improved complex programmable logic device, a hard disk backplane and a server, which include a phase-locked loop, a fast input register bank, a secondary register, a signal acquisition register bank and a fast output register bank; the output end of the phase-locked loop is connected to the fast input register bank, the secondary register, the signal acquisition register bank and the fast output register bank; the input end of the fast input register bank is connected to the serial universal input / output bus, and the output end of the fast input register bank is connected to the input ends of the secondary register and the signal acquisition register bank; the output end of the signal acquisition register bank is connected to the input end of the fast output register bank; the output end of the secondary register is connected to the signal acquisition register bank and the fast output register bank. The present utility model does not require multiple clock signals on the same path to drive multiple registers as clocks, improves the driving ability of signals, and the registers can normally latch data at the clock edge.
[0058] As described above, it is only the specific implementation manner of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.
Claims
1. An improved complex programmable logic device, characterized in that: include: A phase-locked loop, a fast input register group, a secondary register, a signal acquisition register group and a fast output register group; wherein the input end of the phase-locked loop is used to connect an external clock or input an internal clock, and the output end of the phase-locked loop is connected to the fast input register group, the secondary register, the signal acquisition register group and the fast output register group; the input end of the fast input register group is connected to a serial universal input / output bus, and the output end of the fast input register group is connected to the input end of the secondary register and the input end of the signal acquisition register group; the output end of the signal acquisition register group is connected to the input end of the fast output register group; the output end of the secondary register is connected to the signal acquisition register group and the fast output register group; the fast output register group is used to output an output signal corresponding to the external clock or the input internal clock.
2. The improved complex programmable logic device according to claim 1, characterized in that: The fast input register group includes a first fast input register, a second fast input register and a third fast input register connected in parallel.
3. The improved complex programmable logic device according to claim 2, characterized in that: The D pin of the first fast input register is used to access the serial clock line signal in the serial universal input / output bus, the clk pin of the first fast input register is connected to the output end of the phase-locked loop, and the Q pin of the first fast input register is connected to the D pin of the secondary register; the D pin of the second fast input register is used to access the load signal line signal in the serial universal input / output bus, the clk pin of the second fast input register is connected to the output end of the phase-locked loop, and the Q pin of the second fast input register is connected to the signal acquisition register group; the D pin of the third fast input register is used to access the bus data output signal, the clk pin of the third fast input register is connected to the output end of the phase-locked loop, and the Q pin of the third fast input register is connected to the signal acquisition register group.
4. The improved complex programmable logic device according to claim 2, characterized in that: The Q pin of the first fast input register is connected to the first input end of the first AND gate, and the Q pin of the secondary register is connected to the second input end of the first AND gate through a first NOT gate; wherein the output end of the first AND gate is connected to the fast output register group.
5. The improved complex programmable logic device according to claim 4, characterized in that: The signal acquisition register group includes a first signal acquisition register and a second signal acquisition register connected in parallel.
6. The improved complex programmable logic device according to claim 5, characterized in that: The EN pin of the first signal acquisition register is connected to the output end of the second AND gate, the clk pin of the first signal acquisition register is connected to the output end of the phase-locked loop, the D pin of the first signal acquisition register is connected to the Q pin of the second fast input register, and the Q pin of the first signal acquisition register is connected to the fast output register group; the EN pin of the second signal acquisition register is connected to the output end of the second AND gate, the clk pin of the second signal acquisition register is connected to the output end of the phase-locked loop, the D pin of the second signal acquisition register is connected to the Q pin of the third fast input register, and the Q pin of the second signal acquisition register is connected to the fast output register group; wherein, the first input end of the second AND gate is connected to the Q pin of the secondary register, and the second input end of the second AND gate is connected to the Q pin of the first fast input register through a second NOT gate.
7. The improved complex programmable logic device according to claim 6, characterized in that: The fast output register group includes a first fast output register; the D pin of the first fast output register is connected to the output end of the first AND gate, the Q pin of the first signal acquisition register and the Q pin of the second signal acquisition register.
8. The improved complex programmable logic device according to claim 7, characterized in that: The Q pin of the first fast output register is used to output the output signal corresponding to the external clock or the input internal clock.
9. A hard disk backplane, characterized in that: The invention comprises an improved complex programmable logic device as claimed in any one of claims 1 to 8.
10. A server, characterized in that: The invention comprises an improved complex programmable logic device as claimed in any one of claims 1 to 8.