Direct-current relay contact protection circuit

Abstract

The utility model discloses a direct current relay contact protection circuit, comprising a PMOS transistor, a source electrode of which is connected with one end of a relay contact K1, and a resistor R1 connected in parallel between the source electrode and the drain electrode of the PMOS transistor; wherein the other end of the relay contact K1 is connected with a signal input end, and a drain electrode of the PMOS tube is a signal output end and is connected with a load circuit; the charging delay circuit is connected with one end of the relay contact K1, the charging delay circuit sequentially comprises a resistor R2 and a capacitor C1 which are connected in series, and the resistor R2 is connected between the source electrode and the grid electrode of the PMOS tube in parallel; a capacitor C1 is connected in parallel between the base electrode and the emitting electrode of the NPN triode; wherein the collector electrode of the NPN triode is connected with the grid electrode of the PMOS tube. The protection circuit can effectively reduce generation of surge at the closing moment of the direct-current relay, and achieves the purpose of protecting contacts of the direct-current relay so as to prolong the service life of the direct-current relay.

Description

Technical Field

[0001] The utility model relates to the technical field of relay control methods. More specifically, the utility model relates to a DC relay contact protection circuit. Background Art

[0002] A DC relay is a small electronic control device powered by direct current. Due to its isolation function and simple control method, it is widely used in telemetry, remote control, automatic control, communication, and mechatronics. When the DC relay is working, due to the presence of a capacitor in the load circuit, the load circuit is approximately in a short-circuit state at the moment the contact closes, and the resistance of the load circuit is approximately zero, so that a surge current will be generated at the moment the contact closes. The surge current will generate a large amount of heat, which will accelerate the oxidation of the DC relay contact or cause the contact to melt, thereby affecting the service life of the DC relay.

[0003] At present, many explorations and researches have been carried out in China to protect the DC relay contacts and thus extend the service life of the DC relay, but there are certain limitations, especially in terms of circuit reliability and feasibility, etc., and there are problems of insufficient consideration. Summary of the Invention

[0004] The utility model provides a DC relay contact protection circuit, which can effectively reduce the generation of surge at the moment when the DC relay closes, achieving the purpose of protecting the DC relay contacts and thus extending the service life of the DC relay.

[0005] To achieve these and other advantages of the utility model, the utility model provides a DC relay contact protection circuit, including:

[0006] A PMOS transistor, whose source is connected to one end of the relay contact K1, and a resistor R1 is connected in parallel between the source and the drain of the PMOS transistor; wherein, the other end of the relay contact K1 is connected to the signal input end, and the drain of the PMOS transistor is the signal output end, which is connected to the load circuit;

[0007] A charging delay circuit, which is connected to one end of the relay contact K1. The charging delay circuit sequentially includes a resistor R2 and a capacitor C1 connected in series, and the resistor R2 is connected in parallel between the source and the gate of the PMOS transistor;

[0008] An NPN transistor, whose base and emitter are connected in parallel with the capacitor C1; wherein, the collector of the NPN transistor is connected to the gate of the PMOS transistor.

[0009] Preferably, in the DC relay contact protection circuit, the charging delay circuit further includes a resistor R3, one end of which is connected to the resistor R2 and the gate of the PMOS transistor, and the other end is connected to the capacitor C1.

[0010] Preferably, the DC relay contact protection circuit further includes a resistor R4, one end of which is connected to the collector of the NPN transistor, and the other end is connected to the gate of the PMOS transistor, the resistor R2, and the resistor R3 to limit the current of the collector of the NPN transistor.

[0011] Preferably, in the DC relay contact protection circuit, the emitter of the NPN transistor is grounded.

[0012] Preferably, in the DC relay contact protection circuit, the resistor R1 is a variable resistor; the resistor R2 needs to satisfy that the resistance value of the resistor R2 multiplied by the current flowing through the resistor R2 is greater than or equal to the turn-on threshold voltage of the PMOS transistor, and the withstand voltage value of the capacitor C1 is higher than the voltage between the base and the emitter of the NPN transistor.

[0013] The present invention has at least the following beneficial effects: Since there are a PMOS transistor and a resistor R1 connected in parallel between the source and the drain of the PMOS transistor, during the period when the relay contact is closed, when the PMOS is not conducting and is in an open circuit state, the current flowing through the relay contact K1 will flow into the load circuit through the resistor R1. By adjusting the resistance value of the resistor R1, the magnitude of the current flowing through the load circuit can be controlled, thereby preventing the overshoot current caused by the impedance discontinuity of the load circuit when a large current flows into the load circuit. The turn-on time of the PMOS transistor and the turn-on time of the NPN transistor are determined by the electrical parameters of the base and emitter voltage of the NPN transistor, the capacitor C1, the resistor R2, and the resistor R3. By adjusting the capacitance value of the capacitor C1 or the resistance values of the resistor R2 and the resistor R3, the turn-on time of the NPN transistor and the turn-on time of the PMOS transistor can be adjusted. The longer the time, the more beneficial it is to reduce the magnitude of the surge current of the relay contact K1, but the dynamic performance of the load circuit will be reduced. In summary, the present invention can effectively avoid the problem of relay contact adhesion caused by the overshoot current generated by the impedance discontinuity of the load when a large current flows in after the PMOS transistor is turned on, thereby increasing the working life of the relay and the reliability of the circuit operation. In addition, the DC relay contact protection circuit of the present invention has a simple implementation principle and method, so as to ensure the reliability of the circuit and is relatively easy to implement.

[0014] Other advantages, objectives, and features of the present invention will be partially reflected by the following description, and partially will be understood by those skilled in the art through the research and practice of the present invention. Brief Description of the Drawings

[0015] Figure 1 It is a schematic circuit diagram of the contact protection circuit of the DC relay described in the present utility model. Specific embodiments

[0016] The following further describes the present utility model in detail with reference to the accompanying drawings, so that those skilled in the art can implement it according to the text of the specification.

[0017] It should be understood that terms such as "having", "including", and "comprising" used herein do not exclude the presence or addition of one or more other elements or their combinations.

[0018] As Figure 1 shown, the DC relay contact protection circuit provided by the embodiment of the present utility model includes: a PMOS transistor Q1, whose source is connected to one end of the relay contact K1, and a resistor R1 is connected in parallel between the source and the drain of the PMOS transistor, and the resistor R1 is an adjustable resistor; wherein, the other end of the relay contact K1 is connected to the signal input terminal, the drain of the PMOS transistor Q1 is the signal output terminal and is connected to the load circuit; a charging delay circuit, which is connected to one end of the relay contact K1, and the charging delay circuit sequentially includes a resistor R2, a resistor R3 and a capacitor C1 connected in series, and the resistor R2 is connected in parallel between the source and the gate of the PMOS transistor Q1, that is, one end of the resistor R2 is connected to the relay contact K1 and the source of the PMOS transistor Q1, and the other end is connected to the gate of the PMOS transistor Q1 and the resistor R3, and one end of the resistor R3 is connected to the resistor R2 and the gate of the PMOS transistor, and the other end is connected to the capacitor C1; an NPN transistor Q2, and the capacitor C1 is connected in parallel between the base and the emitter of the NPN transistor Q2, that is, one end of the capacitor C1 is connected to the resistor R3 and the base of the NPN transistor Q2, and the other end is connected to the emitter of the NPN transistor Q2; it also includes a resistor R4, one end of which is connected to the collector of the NPN transistor, and the other end is connected to the gate of the PMOS transistor, the resistor R2, and the resistor R3 to limit the current of the collector of the NPN transistor Q2. The emitter of the NPN transistor is grounded.

[0019] In the above embodiment, when the relay contact K1 is not closed, the DC relay contact protection circuit does not work. Since it takes a certain amount of time for the relay contact to close, during the closing process of the relay contact K1, the capacitor C1 connected in parallel with the base and emitter of the NPN transistor Q2 is equivalent to a short circuit state, and the turn-on voltage of the NPN transistor Q2 cannot be reached, making the NPN transistor Q2 equivalent to an open circuit. The Vgs of the PMOS transistor Q1 also cannot reach the required turn-on threshold voltage, so the PMOS transistor Q1 is not turned on and is in an open circuit state. However, due to the existence of the resistor R1 connected in parallel between the source and drain of the PMOS transistor Q1, the current flowing through the relay contact K1 will flow into the load circuit through the resistor R1. At the same time, since the resistance value of the resistor R1 is relatively large, the current flowing through R1 will be very small.

[0020] At the moment when the relay contact K1 closes, due to the existence of the capacitance of the load circuit, the load circuit is equivalent to a short circuit. At the same time, since the PMOS transistor Q1 has not yet reached the conduction condition, the current flowing through the resistor R1 at this time is V Signal_input / R. By adjusting the resistance value of the resistor R1, the magnitude of the current flowing through the load circuit can be controlled, preventing the overshoot current caused by the impedance discontinuity of the load circuit when a large current flows into the load circuit.

[0021] When the relay contact is completely closed, after the voltage of the charging delay circuit composed of the resistor R2, the resistor R3 and the capacitor C1 reaches the turn-on voltage of the NPN transistor Q2, the NPN transistor Q2 conducts. Due to the existence of the resistor R2, a voltage drop Vgs is formed between the source and gate of the PMOS transistor Q1. When the voltage drop Vgs reaches the required turn-on threshold voltage, the PMOS transistor Q1 conducts, and a large current flows through the PMOS transistor Q1 into the load circuit, thereby effectively reducing or preventing the generation of surge current. The resistance value selection of the resistor R2 must satisfy that the current flowing through the resistor R2 multiplied by the resistance value of the resistor R2 is greater than or equal to the turn-on threshold voltage of the PMOS transistor Q1. The resistor R4 is used to limit the current flowing through the collector of the NPN transistor Q2, thereby playing a role in protecting the NPN transistor Q2.

[0022] The turn-on time of the NPN transistor Q2 and the turn-on time of the PMOS transistor Q1 are determined by the voltage between the base and the emitter of the NPN transistor Q2, the electrical parameters of the capacitor C1, the resistor R2, and the resistor R3. For a fixed NPN transistor Q2, since the base-emitter voltage is constant, the turn-on time of the NPN transistor Q2 and the turn-on time of the PMOS transistor Q1 can be adjusted by adjusting the capacitance value of the capacitor C1 or the resistance values of the resistor R2 and the resistor R3. The longer the time, the more beneficial it is to reduce the surge current magnitude of the contacts of the relay K1, but the dynamic performance of the load circuit will be reduced. The withstand voltage value of the capacitor C1 needs to be higher than the voltage between the base and the emitter of the NPN transistor Q2 to prevent the capacitor C1 from being broken down and affecting the reliability and stability of the DC relay contact protection circuit.

[0023] The number of devices and the processing scale described here are used to simplify the description of the present invention. Applications, modifications, and variations of the present invention will be apparent to those skilled in the art.

[0024] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the field, additional modifications can be easily achieved. Therefore, without departing from the general concept defined by the claims and the equivalent scope, the present invention is not limited to the specific details and the illustrated examples described herein.

Claims

1. A DC relay contact protection circuit, characterized in that: include: A PMOS tube, whose source is connected to one end of the relay contact K1, and a resistor R1 is connected in parallel between the source and drain of the PMOS tube; wherein the other end of the relay contact K1 is connected to the signal input end, and the drain of the PMOS tube is the signal output end, which is connected to the load circuit; A charging delay circuit, which is connected to one end of the relay contact K1, and the charging delay circuit comprises a resistor R2 and a capacitor C1 connected in series, and the resistor R2 is connected in parallel between the source and the gate of the PMOS tube; An NPN transistor, wherein the capacitor C1 is connected in parallel between the base and the emitter; wherein the collector of the NPN transistor is connected to the gate of the PMOS transistor.

2. The DC relay contact protection circuit according to claim 1, characterized in that: The charging delay circuit further includes a resistor R3, one end of which is connected to the resistor R2 and the gate of the PMOS tube, and the other end of which is connected to the capacitor C1.

3. The DC relay contact protection circuit according to claim 2, characterized in that: It also includes a resistor R4, one end of which is connected to the collector of the NPN transistor, and the other end of which is connected to the gate of the PMOS tube, the resistor R2, and the resistor R3, so as to limit the current of the collector of the NPN transistor.

4. The DC relay contact protection circuit according to claim 3, characterized in that: The emitter of the NPN transistor is grounded.

5. The DC relay contact protection circuit according to claim 4, characterized in that: The resistor R1 is an adjustable resistor; the resistor R2 needs to satisfy: the resistance value of the resistor R2 multiplied by the current flowing through the resistor R2 is greater than or equal to the turn-on threshold voltage of the PMOS tube, and the withstand voltage of the capacitor C1 is higher than the voltage between the base and the emitter of the NPN transistor.

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