Voltage conversion circuit

By designing a voltage conversion circuit including DASH flash circuit, charging circuit and battery pack circuit, the problem of insufficient fast charging power of the existing power bank is solved, fast charging application scenarios up to 100W are achieved, and a high-power safe and reliable charging solution is provided.

CN223024156UActive Publication Date: 2025-06-24NANYANG LIQI ELECTRONIC TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202422171312.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-09-05
Publication Date
2025-06-24
Estimated Expiration
2034-09-05

AI Technical Summary

Technical Problem

The existing power bank fast charging can only support a few dozen watts of power, which is difficult to meet users' needs for higher charging speeds.

Method used

A voltage conversion circuit is designed, including DASH flash circuit, charging circuit and battery pack circuit, using IP5389 battery management chip and specific configurations of N-channel MOS tubes and inductors, supporting up to 100W fast charging application scenarios.

Benefits of technology

It realizes high-power safe and reliable charging, reduces development costs, and meets users' needs for higher charging speeds.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a voltage conversion circuit, and belongs to the technical field of charging circuits. Comprising a DASH flash circuit, a charging circuit and a battery pack circuit which are connected with a battery management chip U1. IP5389 is adopted as the battery management chip U1; the DASH flash circuit comprises a DASH flash female seat and an N-channel MOS (Metal Oxide Semiconductor) tube Q1; the N-channel MOS tube Q1 adopts an RU3030M2, and the N-channel MOS tube Q1 adopts an RU3030M2; a VOUT1 pin of the DASH flash-stroke female seat is connected to a first pin, a second pin and a third pin of the N-channel MOS tube Q1, and a D + pin and a D-pin of the DASH flash-stroke female seat are connected to a DPA1 pin and a DMA1 pin of the battery management chip U1; pins 5, 6, 7, 8 and 9 of the N-channel MOS tube Q1 are connected in parallel to a VIO pin of the battery management chip U1, and a pin 4 of the N-channel MOS tube Q1 is connected to a VOUTIG pin of the battery management chip U1. According to the utility model, the development cost can be reduced, a 100W fast charging application scene can be supported at most, and high-power, safe and reliable charging can be provided.
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Description

Technical Field

[0001] The utility model relates to the technical field of charging circuits, and particularly relates to a voltage conversion circuit. Background Art

[0002] With the technological iteration of electronic devices, the corresponding charging speed is getting faster and faster, and there are various fast charging modes such as 27W, 60W, and 100W. When the charging power increases, the charging circuit is required to provide higher safety to meet the demand. Currently, the fast charging of power banks generally only supports up to dozens of watts, which can no longer meet the needs of users. Therefore, the applicant specifically designed a voltage conversion charging circuit according to the actual needs of customers, which can achieve a maximum power of 100W. Summary of the Utility Model

[0003] The purpose of the utility model is to propose a voltage conversion circuit to provide charging safely and reliably with high power.

[0004] To achieve the above purpose, the utility model adopts the following technical solutions:

[0005] A voltage conversion circuit includes a DASH flash charging circuit, a charging circuit, and a battery pack circuit connected to a battery management chip U1; the battery management chip U1 uses IP5389.

[0006] The DASH flash charging circuit includes: a DASH flash charging female socket and an N-channel MOS transistor Q1; the N-channel MOS transistor Q1 uses RU3030M2; the VOUT1 pin of the DASH flash charging female socket is connected to the 1st, 2nd, and 3rd pins of the N-channel MOS transistor Q1, and the D+ and D- pins are connected to the DPA1 pin and DMA1 pin of the battery management chip U1; the 5th, 6th, 7th, 8th, and 9th pins of the N-channel MOS transistor Q1 are connected in parallel to the VIO pin of the battery management chip U1, and the 4th pin is connected to the VOUTIG pin of the battery management chip U1.

[0007] In some embodiments, the charging circuit includes: N-channel MOS transistors Q2, Q3, and Q4; the N-channel MOS transistor Q2 uses RU3030M2; the 1st, 2nd, and 3rd pins of the N-channel MOS transistor Q2 are connected to the VBUS pin, the 5th, 6th, 7th, 8th, and 9th pins are connected in parallel to the VIO pin of the battery management chip U1, and the 4th pin is connected to the VBUSG pin of the battery management chip U1.

[0008] In some embodiments, the VIO pin of the battery management chip U1 is connected to a capacitor bank formed by capacitors C13, C14, C15, and C16 connected in parallel.

[0009] In some embodiments, capacitors C7 and resistors R11 and R13 in series are connected in parallel between the CSP1 and CSN1 pins of the battery management chip U1.

[0010] In some embodiments, the PCIN pin of the battery management chip U1 is connected to the 2nd, 3rd, and 4th pins of MOS transistor Q3; the 9th pin of the MOS transistor Q3 is connected to the BST1 pin of the battery management chip U1 through a series capacitor C8;

[0011] The PCON pin of the battery management chip U1 is connected to the 2nd, 3rd, and 4th pins of MOS transistor Q4; the 9th pin of the MOS transistor Q4 is connected to the BST2 pin of the battery management chip U1 through a series capacitor C9;

[0012] The MOS transistors Q3 and Q4 are of the RUH30J51M type;

[0013] An inductor L2 is connected in series between the 9th pins of the MOS transistors Q3 and Q4, and the inductor L2 is of 10 uH;

[0014] Both ends of the inductor L2 are respectively connected to the LX1 and LX2 pins of the battery management chip U1.

[0015] In some embodiments, the battery pack circuit is connected to the BAT pin of the battery management chip U1;

[0016] The battery pack circuit includes: an LDO linear voltage regulator chip LDO1;

[0017] A parallel capacitor bank is connected in series between the VDD pin of the LDO linear voltage regulator chip LDO1 and the BAT pin of the battery management chip U1, and the parallel capacitor bank includes capacitors C12, C11, C10, and C26.

[0018] In some embodiments, the parallel capacitor bank is connected to the PCON pin of the battery management chip U1 through a series resistor R12;

[0019] The parallel capacitor bank is connected to the CSN2 pin of the battery management chip U1 through a parallel capacitor C6 and resistors R12 and R10.

[0020] In some embodiments, the VOUT pin of the LDO linear voltage regulator chip LDO1 is connected to the CC2 pin of the battery management chip U1 through a series Schottky diode D1 and MOS transistor Q5;

[0021] The Schottky diode D1 is connected to the CC1 pin of the battery management chip U1 through a series MOS transistor Q6;

[0022] The parallel resistor R15 of the MOS transistor Q6 is connected to the MOS transistor Q8, and the MOS transistor Q8 is connected to the GPIO9 pin of the battery management chip U1.

[0023] In some embodiments, the KEY pin of the battery management chip U1 is connected to the switch SW1 in series with the resistor R9.

[0024] In some embodiments, the LED1, LED2, LED3, LED4, and LED5 of the battery management chip U1 are respectively connected to the LED lights.

[0025] Compared with the prior art, the present utility model provides a voltage conversion circuit, which has the following beneficial effects.

[0026] 1. The present utility model can reduce the development cost, support the fast charging application scenario with a maximum power of 100W, and provide high-power, safe and reliable charging.

[0027] Other advantages, objectives and features of the present utility model will be described to some extent in the subsequent specification; and to some extent, based on the study of the following text, it will be obvious to those skilled in the art; or, it can be taught from the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is the circuit diagram of the present utility model.

[0029] Figure 2 is the circuit diagram of the battery pack. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments.

[0031] Refer to Figure 1-2 , a voltage conversion circuit, including a DASH flash charging circuit, a charging circuit and a battery pack circuit connected to the battery management chip U1; the battery management chip U1 uses IP5389; IP5389 is a buck-boost power management SOC chip launched by Yingjixin. It integrates a buck-boost controller, protocol function and main control MCU, and integrates multiple components required in the past into a single chip, which can simplify the circuit design and reduce the development cost of manufacturers.

[0032] The DASH flash charging circuit includes: a DASH flash charging female socket and an N-channel MOS transistor Q1. The N-channel MOS transistor Q1 uses RU3030M2. The VOUT1 pin of the DASH flash charging female socket is connected to pins 1, 2, and 3 of the N-channel MOS transistor Q1, and the D+ and D- pins are connected to the DPA1 pin and DMA1 pin of the battery management chip U1. Pins 5, 6, 7, 8, and 9 of the N-channel MOS transistor Q1 are connected in parallel to the VIO pin of the battery management chip U1, and pin 4 is connected to the VOUTIG pin of the battery management chip U1.

[0033] The charging circuit includes: N-channel MOS transistors Q2, Q3, and Q4. The N-channel MOS transistor Q2 uses RU3030M2. Pins 1, 2, and 3 of the N-channel MOS transistor Q2 are connected to the VBUS pin, and pins 5, 6, 7, 8, and 9 of the N-channel MOS transistor Q2 are connected in parallel to the VIO pin of the battery management chip U1, and pin 4 is connected to the VBUSG pin of the battery management chip U1.

[0034] The VIO pin of the battery management chip U1 is connected to a capacitor bank formed by capacitors C13, C14, C15, and C16 connected in parallel. Capacitors C7 and series resistors R11 and R13 are connected in parallel between the CSP1 and CSN1 pins of the battery management chip U1.

[0035] The PCIN pin of the battery management chip U1 is connected to pins 2, 3, and 4 of the MOS transistor Q3. The 9th pin of the MOS transistor Q3 is connected in series with the capacitor C8 to the BST1 pin of the battery management chip U1. The PCON pin of the battery management chip U1 is connected to pins 2, 3, and 4 of the MOS transistor Q4. The 9th pin of the MOS transistor Q4 is connected in series with the capacitor C9 to the BST2 pin of the battery management chip U1. The MOS transistors Q3 and Q4 use RUH30J51M. An inductor L2 is connected in series between the 9th pins of the MOS transistors Q3 and Q4. The inductor L2 uses 10uH. The two ends of the inductor L2 are respectively connected to the LX1 and LX2 pins of the battery management chip U1.

[0036] The battery pack circuit is connected to the BAT pin of the battery management chip U1. The battery pack circuit includes: an LDO linear voltage regulator chip LDO1. A parallel capacitor bank is connected in series between the VDD pin of the LDO linear voltage regulator chip LDO1 and the BAT pin of the battery management chip U1. The parallel capacitor bank includes capacitors C12, C11, C10, and C26. Among them, C12 uses 100uf, and C11, C10, and C26 use 22uf.

[0037] The parallel capacitor bank is connected in series with the resistor R12 to the PCON pin of the battery management chip U1. The parallel capacitor bank is connected in parallel with the capacitor C6 and the resistors R12 and R10 to the CSN2 pin of the battery management chip U1.

[0038] The VOUT pin of the LDO linear voltage regulator chip LDO1 is connected in series with a Schottky diode D1 and a MOS transistor Q5 to the CC2 pin of the battery management chip U1; the Schottky diode D1 is connected in series with the MOS transistor Q6 to the CC1 pin of the battery management chip U1; the MOS transistor Q6 is connected in parallel with a resistor R15 to the MOS transistor Q8, and the MOS transistor Q8 is connected to the GPIO9 pin of the battery management chip U1.

[0039] The KEY pin of the battery management chip U1 is connected in series with a resistor R9 to the switch SW1; it is set to power on by a short press and power off by a long press of 2S; the LED1, LED2, LED3, LED4, and LED5 of the battery management chip U1 are respectively connected to the LED lights; the battery of the battery pack circuit uses a 4-cell 5000ma battery.

[0040] In the present utility model, IP5389 is adopted, which can reduce the development cost; at the same time, it is matched with the peripheral circuit to support a fast charging application scenario of up to 100W, providing high-power, safe, and reliable charging.

[0041] As mentioned above, it is only the preferred specific implementation manner of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model, according to the technical solution and the inventive concept of the present utility model, makes equivalent substitutions or changes, and should be covered within the protection scope of the present utility model.

[0042] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0043] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present utility model.

Claims

1. A voltage conversion circuit, characterized in that: It includes a DASH flash circuit, a charging circuit and a battery pack circuit connected to a battery management chip U1; the battery management chip U1 adopts IP5389; The DASH flash circuit includes: a DASH flash mother socket and an N-channel MOS tube Q1; the N-channel MOS tube Q1 adopts RU3030M2; the VOUT1 pin of the DASH flash mother socket is connected to the 1, 2, and 3 pins of the N-channel MOS tube Q1, and the D+ and D- pins are connected to the DPA1 pin and DMA1 pin of the battery management chip U1; the 5, 6, 7, 8, and 9 pins of the N-channel MOS tube Q1 are connected in parallel to the VIO pin of the battery management chip U1, and the 4th pin is connected to the VOUTIG pin of the battery management chip U1.

2. The voltage conversion circuit according to claim 1, characterized in that: The charging circuit includes: N-channel MOS tubes Q2, Q3, and Q4; the N-channel MOS tube Q2 adopts RU3030M2; pins 1, 2, and 3 of the N-channel MOS tube Q2 are connected to the VBUS pin, pins 5, 6, 7, 8, and 9 are connected in parallel to the VIO pin of the battery management chip U1, and pin 4 is connected to the VBUSG pin of the battery management chip U1.

3. The voltage conversion circuit according to claim 2, characterized in that: The VIO pin of the battery management chip U1 is connected to a capacitor group consisting of capacitors C13, C14, C15, and C16 connected in parallel.

4. The voltage conversion circuit according to claim 3, characterized in that: The CSP1 and CSN1 pins of the battery management chip U1 are connected in parallel with a capacitor C7 and resistors R11 and R13 in series.

5. The voltage conversion circuit according to claim 2, characterized in that: The PCIN pin of the battery management chip U1 is connected to the 2nd, 3rd and 4th pins of the MOS tube Q3; the 9th pin of the MOS tube Q3 is connected to the BST1 pin of the battery management chip U1 in series with the capacitor C8; The PCON pin of the battery management chip U1 is connected to the 2nd, 3rd and 4th pins of the MOS tube Q4; the 9th pin of the MOS tube Q4 is connected to the BST2 pin of the battery management chip U1 through a capacitor C9 in series; the MOS tubes Q3 and Q4 are RUH30J51M; an inductor L2 is connected in series between the 9th pins of the MOS tube Q3 and the MOS tube Q4, and the inductor L2 is 10uH; the two ends of the inductor L2 are respectively connected to the LX1 and LX2 pins of the battery management chip U1.

6. The voltage conversion circuit according to claim 1, characterized in that: The battery pack circuit is connected to the BAT pin of the battery management chip U1; the battery pack circuit includes: an LDO linear regulator chip LDO1; a parallel capacitor group is connected in series between the VDD pin of the LDO linear regulator chip LDO1 and the BAT pin of the battery management chip U1, and the parallel capacitor group includes capacitors C12, C11, C10, and C26.

7. The voltage conversion circuit according to claim 6, characterized in that: The parallel capacitor group is connected in series with the resistor R12 to the PCON pin of the battery management chip U1 ; the parallel capacitor C6 of the parallel capacitor group and the resistors R12 and R10 are connected to the CSN2 pin of the battery management chip U1 .

8. The voltage conversion circuit according to claim 6, characterized in that: The VOUT pin of the LDO linear regulator chip LDO1 is connected in series with a Schottky diode D1 and a MOS tube Q5, and is connected to the CC2 pin of the battery management chip U1; the Schottky diode D1 is connected in series with a MOS tube Q6 and is connected to the CC1 pin of the battery management chip U1; the MOS tube Q6 is connected in parallel with a resistor R15 and is connected to the MOS tube Q8, and the MOS tube Q8 is connected to the GPIO9 pin of the battery management chip U1.

9. The voltage conversion circuit according to claim 1, characterized in that: The KEY pin of the battery management chip U1 is connected in series with a resistor R9 to the switch SW1 .

10. The voltage conversion circuit according to claim 1, characterized in that: LED1, LED2, LED3, LED4, and LED5 of the battery management chip U1 are connected to LED lights respectively.