Operational amplifier

Abstract

The utility model relates to an operational amplifier. The operational amplifier includes: an input stage including: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common tail transistor configured to define a bias current; and a second common-tail transistor selectively coupled to the first inverter and the second inverter via a second switch; and an output stage comprising: a third inverter and a fourth inverter coupled together, the third inverter and the fourth inverter selectively coupled to a supply voltage via a third switch and selectively coupled to ground via a fourth switch; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and a second capacitive coupling configured to couple the fourth inverter to a second output of the input stage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 516,713, filed on July 31, 2023, which is hereby incorporated by reference in its entirety. Technical field

[0003] Example embodiments of the present disclosure generally relate to operational amplifiers, and more particularly to low - noise inverter - based amplifiers with wide output swing. Background art

[0004] The applicant has found many technical challenges and difficulties associated with operational amplifiers. Through effort, ingenuity, and innovation, the applicant has solved many of these identified problems by developing the embodiments of the present disclosure, which are described in detail below. Summary of the utility model

[0005] Various embodiments described herein relate to operational amplifiers with low noise and wide output swing.

[0006] According to one aspect of the present disclosure, an operational amplifier is provided. In some embodiments, the operational amplifier includes an input stage. The input stage includes: a first inverter and a second inverter coupled together and configured to operate differentially; a first common - tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common - tail transistor being configured to define a bias current; and a second common - tail transistor selectively coupled to the first inverter and the second inverter via a second switch. The operational amplifier further includes an output stage. The output stage includes: a third inverter and a fourth inverter coupled together, the third inverter and the fourth inverter being selectively coupled to a supply voltage via a third switch and selectively coupled to ground via a fourth switch; a first capacitive coupling member configured to couple the third inverter to a first output of the input stage; and a second capacitive coupling member configured to couple the fourth inverter to a second output of the input stage.

[0007] In some embodiments, the first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor; and the second inverter includes a second PMOS transistor and a second NMOS transistor, the second PMOS transistor and the second NMOS transistor being coupled together via the drain terminal of the second PMOS transistor and the drain terminal of the second NMOS transistor.

[0008] In some embodiments, the first PMOS transistor and the second PMOS transistor are coupled together via the source terminal of the first PMOS transistor and the source terminal of the second PMOS transistor; and the first NMOS transistor and the second NMOS transistor are coupled together via the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor.

[0009] In some embodiments, the third inverter includes a third PMOS transistor and a third NMOS transistor, and the third PMOS transistor and the third NMOS transistor are coupled together via the drain terminal of the third PMOS transistor and the drain terminal of the third NMOS transistor; and the fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, and the fourth PMOS transistor and the fourth NMOS transistor are coupled together via the drain terminal of the fourth PMOS transistor and the drain terminal of the fourth NMOS transistor.

[0010] In some embodiments, the third PMOS transistor and the fourth PMOS transistor are coupled together via the source terminal of the third PMOS transistor and the source terminal of the fourth PMOS transistor; and the third NMOS transistor and the fourth NMOS transistor are coupled together via the source terminal of the third NMOS transistor and the source terminal of the fourth NMOS transistor.

[0011] In some embodiments, the gate terminal of the third PMOS transistor and the gate terminal of the third NMOS transistor are coupled to the first output of the input stage via a first capacitive coupling component; and the gate terminal of the fourth PMOS transistor and the gate terminal of the fourth NMOS transistor are coupled to the second output of the input stage via a second capacitive coupling component.

[0012] In some embodiments, the first capacitive coupling component includes a first switched capacitor circuit.

[0013] In some embodiments, the second capacitive coupling component includes a second switched capacitor circuit.

[0014] In some embodiments, the operational amplifier further includes a bias current circuit coupled to the first common tail transistor.

[0015] In some embodiments, a common mode feedback circuit coupled to the second common tail transistor is further included.

[0016] In some embodiments, the operational amplifier is configured to operate in one or more of a bias phase and an amplification phase.

[0017] In some embodiments, during the bias phase, each of the first switch, the second switch, the third switch, and the fourth switch is in an open state.

[0018] According to another aspect of the present disclosure, an operational amplifier is provided. In some embodiments, the operational amplifier includes an input stage. The input stage includes: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor coupled to the first inverter and the second inverter, the first common-tail transistor being configured to define a bias current; and a second common-tail transistor coupled to the first inverter and the second inverter. The operational amplifier further includes an output stage. The output stage includes: a third inverter and a fourth inverter coupled together; a first capacitive coupling member configured to couple the third inverter to a first output of the input stage; and a second capacitive coupling member configured to couple the fourth inverter to a second output of the input stage.

[0019] In some embodiments, the first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and the second inverter includes a second PMOS transistor and a second NMOS transistor, the second PMOS transistor and the second NMOS transistor being coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

[0020] In some embodiments, the first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; and the first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

[0021] In some embodiments, the third inverter includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor and the third NMOS transistor being coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and the fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor being coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

[0022] In some embodiments, the third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; and the third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

[0023] In some embodiments, the gate terminals of the third PMOS transistor and the third NMOS transistor are coupled to the first output of the input stage via a first capacitive coupling; and the gate terminals of the fourth PMOS transistor and the fourth NMOS transistor are coupled to the second output of the input stage via a second capacitive coupling.

[0024] In some embodiments, the operational amplifier further includes a bias current circuit coupled to the first cascode transistor.

[0025] In some embodiments, the operational amplifier further includes a common-mode feedback circuit coupled to the second cascode transistor.

[0026] The foregoing illustrative overview, as well as other exemplary objects and / or advantages of the present disclosure and its implementations, are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description of the illustrative embodiments can be read in conjunction with the accompanying drawings. It should be appreciated that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale unless otherwise described. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise described. With respect to the figures presented herein, embodiments incorporating teachings of the present disclosure are shown and described, in which:

[0028] Figure 1 An example multiplying digital-to-analog converter (MDAC) of a pipelined analog-to-digital converter (ADC) is provided, in which an operational amplifier may be used.

[0029] Figure 2 An example operational amplifier in accordance with at least one embodiment of the present disclosure is illustrated.

[0030] Figure 3 A flowchart depicting the operation of an example operational amplifier in a bias phase in accordance with at least one example embodiment of the present disclosure is provided.

[0031] Figure 4A A flowchart depicting the operation of an example operational amplifier in an amplification phase in accordance with at least one example embodiment of the present disclosure is provided.

[0032] Figure 4B An example timing diagram corresponding to the bias phase and the amplification phase in accordance with at least one example embodiment of the present disclosure is provided.

[0033] Figure 5 An example operational amplifier in accordance with at least one embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0034] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the disclosure are shown. In fact, the disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0035] As used herein, terms such as "front", "rear", "top", etc. are used for explanatory purposes in the examples provided below to describe the relative positions of certain components or portions of components. Additionally, according to the present disclosure, it will be apparent to those of ordinary skill in the art that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within the applicable engineering tolerances.

[0036] As used herein, the term "comprising" means including but not limited to and should be construed in the manner commonly used in the patent context. The use of broader terms such as including, containing, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting substantially of.

[0037] Phrases such as "in one embodiment", "according to one embodiment", etc. generally mean that the particular feature, structure, or characteristic following such phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0038] The word "example" or "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] If the specification states that a component or feature "may", "can", "might", "should", "will", "preferably", "possibly", "ordinarily", "optionally", "for example", "often", or "may" (or other such language) be included or have a certain characteristic, then it is not required that the particular component or feature be included or have that characteristic. Such a component or feature may optionally be included in some embodiments or it may be excluded.

[0040] As used herein, the term "or" is used in the alternative sense and the conjunctive sense, unless otherwise indicated. The terms "illustrative" and "example" are used as examples and do not indicate a level of quality. Terms such as "calculate," "determine," "generate," and / or similar words are used interchangeably herein to refer to the creation, modification, or identification of data. Additionally, "based on," "partially based on," "at least based on," "based upon," and / or similar words are used interchangeably herein in an open-ended manner such that they do not indicate being based solely or only on one or more of the recited elements, unless so indicated. Like reference numerals refer to like elements throughout.

[0041] In some examples, an operational amplifier may refer to an electronic component that increases the amplitude or intensity of an input signal, e.g., without changing its original shape or characteristics. As described above, there are many technical challenges and difficulties associated with operational amplifiers. For example, many applications such as high-speed analog-to-digital converters (ADCs) require operational amplifiers with high bandwidth and high gain. However, to meet such high bandwidth and high gain requirements, an operational amplifier may consume a large amount of power. As another example, the amount of current consumed may vary significantly among process, voltage, and temperature (PVT), which in turn may result in large variations in other parameters associated with the operational amplifier (e.g., gain, bandwidth, noise, and / or other parameters). As yet another example, to meet high bandwidth and high gain requirements, a large amount of sample noise voltage variance (e.g., KT / C noise) may be generated, which may have a negative impact on the overall noise performance of the operational amplifier.

[0042] Embodiments of the present disclosure address the above-mentioned challenges and difficulties, as well as other challenges and difficulties associated with operational amplifiers. Specifically, embodiments of the present disclosure provide operational amplifiers with low noise and wide output swing, which can meet the high bandwidth and high gain requirements associated with many applications using operational amplifiers. Moreover, embodiments of the present disclosure provide for reducing the amount of power consumed. Some embodiments include two amplifier stages, where the first amplifier stage (e.g., input stage) includes a current-biased inverting amplifier, and the second amplifier stage (e.g., output stage) includes a capacitively-biased inverting amplifier. In some embodiments, the current-biased inverting amplifier includes one or more inverters comprising PMOS and NMOS transistors. In some embodiments, the capacitively-biased inverting amplifier includes one or more inverters comprising PMOS and NMOS transistors. In some embodiments, the PMOS and NMOS transistors of the first amplifier stage and / or the PMOS and NMOS transistors of the second amplifier stage are configured as drivers. For example, some embodiments utilize the respective PMOS and NMOS transistors of the first amplifier stage to drive the second amplifier stage and / or the load. Some embodiments utilize a common-tail transistor at the first amplifier stage to define the bias current for the operational amplifier.

[0043] By using a current-biased inverting amplifier (e.g., having a common-tail transistor) at the first amplifier stage and a capacitively-biased inverting amplifier at the second amplifier stage, embodiments of the present disclosure avoid any KT / C noise at the input of the first amplifier stage and mitigate / reduce the impact of KT / C noise generated at the input of the second amplifier stage. In this regard, embodiments of the present disclosure improve the overall noise performance of the operational amplifier, thus providing a low-noise operational amplifier that can be used in various applications, environments, systems, etc.

[0044] In addition, by using a common-tail transistor at the first amplifier stage of the operational amplifier for current biasing purposes and for applying common-mode feedback purposes, embodiments of the present disclosure have a good common-mode rejection ratio, especially for the first amplifier stage. When used in an external feedback loop, such as in the case of a multiplication DAC in a pipelined ADC, this mitigates the impact of any change in the input common mode of the operational amplifier on its performance and helps ensure the common-mode stability of the two-stage operational amplifier.

[0045] In addition, embodiments of the present disclosure provide a wide output swing with a stable output common mode by using a capacitively biased inverter amplifier at a second amplifier stage corresponding to the output stage of an operational amplifier. This is possible because the effective supply of the output stage, which is the difference between the potentials of the source terminals of the PMOS and NMOS transistors that form the output stage, remains almost fixed at the difference between the external supply and ground and does not vary with process and temperature. This ensures the maximum headroom for the transistors of the output stage, thereby enabling a wide output swing that can be centered around the midpoint of the supply.

[0046] In addition, by using both PMOS and NMOS transistors as drivers, the transconductance of the corresponding amplifier stage (e.g., g m ) is effectively doubled. It will be appreciated that noise, bandwidth, and current consumption are generally related to the transconductance of the operational amplifier (e.g., input gm) (e.g., linked). Thus, by using both PMOS and NMOS transistors of the amplifier stage as drivers, embodiments of the present disclosure provide lower noise, higher bandwidth, and lower current consumption, e.g., at least in part due to the increased transconductance achieved by utilizing the dual PMOS and NMOS driver configuration.

[0047] As described above, operational amplifiers can be used in various applications, environments, and / or systems. Non-limiting examples of applications, environments, and / or systems in which operational amplifiers can be used include pipelined ADCs, pipelined SAR ADCs, etc. Various applications, environments, and / or systems can have different operational amplifier requirements (e.g., different bandwidth requirements, different noise requirements, etc.). Additionally or alternatively, various applications, environments, and / or systems can use operational amplifiers in different ways. For example, in an example context, a pipelined ADC can use an operational amplifier as a residue amplifier.

[0048] Figure 1 An example application in which an operational amplifier can be used is illustrated. Specifically, Figure 1 an example MDAC circuit 100 of a pipelined ADC is illustrated. As Figure 1 shown, the MDAC circuit includes an operational amplifier 102, which serves as the core for implementing gain in the MDAC. In various embodiments, in order to use the operational amplifier in a pipelined ADC as a residue amplifier, the pipelined ADC requires the operational amplifier to have high gain, low noise, and a wide output swing. Moreover, it is desirable to meet these operational amplifier requirements (e.g., high gain, low noise, and wide output swing) while consuming power efficiently. Example operational amplifiers according to embodiments of the present disclosure can be used to meet the above high gain, low noise, and wide output swing requirements while also reducing the amount of power consumed. In some embodiments, the example operational amplifier is a two-stage operational amplifier.

[0049] Although the above description provides examples of MDACs and / or pipelined ADCs, it should be noted that the scope of the present disclosure is not limited to the above description. Example embodiments of the present disclosure may be implemented in other applications and / or systems. For example, in addition to using an operational amplifier as a residue amplifier, other applications and / or systems may require an operational amplifier with high gain, low noise, and wide output swing for various reasons.

[0050] Figure 2 An example operational amplifier 200 in accordance with at least one embodiment of the present disclosure is illustrated. Specifically, Figure 2 An example discrete-time implementation of an example operational amplifier circuit in accordance with at least one embodiment of the present disclosure is illustrated. In some embodiments, the example operational amplifier 200 includes a first amplifier stage 20a representing an input stage of the operational amplifier and a second amplifier stage 20b representing an output stage of the operational amplifier 200. For example, in some embodiments, the first amplifier stage 20a is the input stage of the operational amplifier 200, and the second amplifier stage 20b is the output stage of the operational amplifier 200. In this regard, the first amplifier stage 20a may include a first gain stage of the operational amplifier 200, and the second amplifier stage 20b may include a second gain stage of the operational amplifier 200.

[0051] In some embodiments, the first amplifier stage 20a includes a first inverter 22a and a second inverter 22b. In some embodiments, the first inverter 22a includes a first PMOS transistor 224a and a first NMOS transistor 226a. In some embodiments, the second inverter 22b includes a second PMOS transistor 224b and a second NMOS transistor 226b. The first inverter 22a and the second inverter 22b may be configured to operate in a differential manner. For example, in some embodiments, the first inverter 22a and the second inverter 22b include differential inverters or otherwise function as differential inverters. It should be recognized that in some embodiments, the first inverter 22a and the second inverter 22b may include different inverter configurations. For example, in some embodiments, the first inverter 22a may include different types of transistors and / or transistors arranged in different configurations.

[0052] In some embodiments, the gate terminals of the first PMOS transistor 224a and the first NMOS transistor 226a form or otherwise define a first input 220a. In some embodiments, the gate terminals of the second PMOS transistor 224b and the second NMOS transistor 226b form or otherwise define a second input 220b. For example, in some embodiments, the gate terminals of each of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together, and the gate terminals of each of the second PMOS transistor 224b and the second NMOS transistor 226b are coupled together.

[0053] In some embodiments, the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together and form or otherwise define a first output 232a of the first amplifier stage 20a. In some embodiments, the drain terminals of the second PMOS transistor 224b and the second NMOS transistor 226b are coupled together and form or otherwise define a second output 232b of the first amplifier stage 20a. For example, in some embodiments, the first amplifier stage 20a is configured to output the first output 232a via the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a, and output the second output 232b via the drain terminals of the second PMOS transistor 224b and the second NMOS transistor 226b.

[0054] In some embodiments, the first output 232a and the second output 232b of the first amplifier stage 20a are coupled to a second amplifier stage 20b. As described herein, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b. In some embodiments, the first output 232a is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the first output 232a is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a first RC circuit, where the first RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the first output 232a is selectively coupled to a voltage 278 via a switch 276a. The switch 276a may be referred to as a bias switch.

[0055] In some embodiments, the second output 232b is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the second output 232b is coupled to a portion of the second amplifier stage 20b via a second RC circuit (e.g., coupled to one or more components of the second amplifier stage 20b), where the second RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the second output 232b is selectively coupled to the voltage 278 via a switch 276b. The switch 276b may be referred to as a bias switch.

[0056] In some embodiments, the source terminal of the first NMOS transistor 226a and the source terminal of the second NMOS transistor 226b are selectively coupled to a first common drain transistor 222a configured to define a bias current. As Figure 2 shown, in some embodiments, the gate terminal of the first common drain transistor 222a is coupled to the bias voltage 230. For example, the first common drain transistor 222a may be connected to the bias current circuit 201. In this regard, the first inverter 22a and the second inverter 22b may have input currents of the respective first and second inverters 22a, 22b biased by the first common drain transistor 222a (e.g., defining the gate potential of the first common drain transistor 222a). Although the first common drain transistor 222a is Figure 2 depicted as an NMOS-type transistor in the figure, it should be appreciated that the first common drain transistor 222a may be of a different type, such as a PMOS type.

[0057] In some embodiments, a first switch 228a is deployed between the drain terminal of the first common drain transistor 222a and the source terminals of the first and second NMOS transistors 226a, 226b to facilitate selectively coupling the first common drain transistor 222a to the first and second NMOS transistors 226a, 226b. In some embodiments, a first end of the first switch 228a is coupled to the drain terminal of the first common drain transistor 222a, and a second end of the first switch 228a is coupled to the source terminals of the first and second NMOS transistors 226a, 226b. The first switch 228a may be referred to as an amplifier switch.

[0058] In some embodiments, embodiments of the present disclosure mitigate or reduce the impact of any variations in the input common mode of an amplifier on its performance by utilizing cascode transistors, such as utilizing a first cascode transistor 222a at a first amplifier stage (e.g., an input stage) to define a bias current and a second cascode transistor 222b to apply common-mode feedback. Thus, embodiments of the present disclosure provide a good common-mode rejection ratio and, in turn, good common-mode stability. For example, the absence of cascode transistors may result in a poor common-mode rejection ratio (CMRR). In various contexts, a poor CMRR is particularly undesirable in a two-stage operational amplifier when used within an external feedback loop. Here, the external loop may provide negative feedback in the differential mode, while in the common mode, the operational amplifier will be in positive feedback. Thus, a poor CMRR coupled with positive feedback may lead to common-mode instability.

[0059] In some embodiments, the source terminals of the first PMOS transistor 224a and the second PMOS transistor 224b are selectively coupled to the second cascode transistor 222b. As Figure 2 shown, in some embodiments, the gate terminal of the second cascode transistor 222b is coupled to a common-mode feedback circuit (CMFB) 30 (depicted as a functional block for ease of illustrating the example operational amplifier 200). For example, the gate voltage of the second cascode transistor 222b can be controlled by the output of the common-mode feedback circuit 30. Although the second cascode transistor 222b is Figure 2 depicted as a PMOS-type transistor in

[0060] it should be appreciated that the second cascode transistor 222b can be an NMOS-type.

[0061] In some embodiments, and as Figure 2 shown, the first amplifier stage 20a does not include a bias capacitor. In this regard, the first amplifier stage 20a will not be associated with a bias capacitor or otherwise generate the KT / C noise typically associated with bias capacitors. Thus, embodiments of the present disclosure provide an operational amplifier with low noise, at least in part due to the absence of (one or more) bias capacitors in the first amplifier stage.

[0062] In some embodiments, the first and second switches 228a, 228b are configured to facilitate multi-stage operation of the exemplary operational amplifier 200. For example, in some embodiments, the operational amplifier 200 is configured to operate in a first stage corresponding to a bias stage and a second stage corresponding to an amplification stage. In some embodiments, switches 228a and 228b are open (e.g., in an open state) during the bias stage.

[0063] As Figure 2 shown, in some embodiments, PMOS and NMOS transistors of both the first and second amplifier stages are used as drivers, thereby effectively doubling the transconductance (e.g., g m ) of the amplifier stage using both PMOS and NMOS transistors as drivers. For example, when both the NMOS transistor and the PMOS transistor have the same transconductance, the transconductance of the operational amplifier 200 is effectively doubled, which in turn facilitates reducing noise, increasing bandwidth, and reducing current consumption.

[0064] In some embodiments, the second amplifier stage 20b corresponding to the output stage of the exemplary operational amplifier 200 includes a third inverter 24a and a fourth inverter 24b. In some embodiments, the third inverter 24a includes a third PMOS transistor 244a and a third NMOS transistor 246a. In some embodiments, the fourth inverter 24b includes a fourth PMOS transistor 244b and a fourth NMOS transistor 246b. In some embodiments, the third inverter 24a and the fourth inverter 24b are configured to operate differentially. For example, in some embodiments, the third inverter 24a and the fourth inverter 24b include differential inverters or otherwise function as differential inverters. It should be appreciated that in some embodiments, the third inverter 24a and the fourth inverter 24b may include different inverter configurations. For example, in some embodiments, the third inverter 24a may include different types of transistors and / or transistors arranged in different configurations.

[0065] In some embodiments, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are each coupled to the second output 232b of the first amplifier stage 20a. As further described herein, in some embodiments, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a.

[0066] In some embodiments, the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are coupled together and define the first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are coupled together and define the second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. As Figure 2 shown, in some embodiments, the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are coupled to the first output 232a of the first amplifier stage 20a via a first RC circuit, and the drain terminal of the fourth NMOS transistor 246b is coupled to the second output 232b of the first amplifier stage 20a via a second RC circuit.

[0067] In some embodiments, the source terminals of the third NMOS transistor 246a and the fourth NMOS transistor 246b are selectively coupled to ground 290a. In some embodiments, a third switch 248a is deployed between ground 290a and the source terminals of the third and fourth NMOS transistors 246a, 246b to facilitate selectively coupling ground 290a to the third and fourth NMOS transistors 246a, 246b. The third switch 248a may be referred to as an amplifier switch. In some embodiments, the first end of the third switch 248a is coupled to ground 290a, and the second end of the third switch 248a is coupled to the source terminals of the third and fourth NMOS transistors 246a, 246b.

[0068] In some embodiments, the source terminals of the third PMOS transistor 244a and the fourth PMOS transistor 244b are selectively coupled to the voltage supply 290b. In some embodiments, a fourth switch 248b is deployed between the voltage supply 290b and the source terminals of the third and fourth PMOS transistors 244a, 244b to facilitate selectively coupling the voltage supply 290b to the third and fourth NMOS transistors 246a, 246b. The fourth switch 248b may be referred to as an amplifier switch. In some embodiments, a first end of the fourth switch 248b is coupled to the voltage supply 290b, and a second end of the fourth switch 248b is coupled to the source terminals of the third and fourth PMOS transistors 244a, 244b. In some embodiments, the third and fourth switches 248a, 248b are configured to facilitate multi-stage operation of the exemplary operational amplifier 200. For example, as described above, in some embodiments, the operational amplifier 200 is configured to operate in a first stage corresponding to a bias stage and a second stage corresponding to an amplification stage. In some embodiments, the third switch 248a and the fourth switch 248b are open (e.g., in an open state) during the bias stage and closed (e.g., in a closed state) during the amplification stage.

[0069] As described above, in some embodiments, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a. In this regard, in some embodiments, the second amplifier stage 20b is capacitively biased. In some embodiments and as Figure 2As depicted, the second amplifier stage 20b includes a first switched capacitor circuit coupled to the third inverter 24a. For example, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are capacitively coupled to the first output 232a via the first switched capacitor circuit, where a portion of the first switched capacitor circuit can be coupled to the gate terminal of the third PMOS transistor 244a, and a portion of the first switched capacitor circuit can be coupled to the gate terminal of the third NMOS transistor 246a. Additionally or alternatively, in some embodiments, the second amplifier stage 20b includes a second switched capacitor circuit coupled to the fourth inverter 24b. For example, the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are capacitively coupled to the second output 232b via the second switched capacitor circuit, where a portion of the second switched capacitor circuit can be coupled to the gate terminal of the fourth PMOS transistor 244b, and a portion of the second switched capacitor circuit can be coupled to the gate terminal of the fourth NMOS transistor 246b.

[0070] In some embodiments, the first switched capacitor circuit includes a first capacitor 272a and a second capacitor 272b, each capacitor coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the first capacitor 272a is coupled to the gate terminal of the third NMOS transistor 246a. In some embodiments, the second capacitor 272b is coupled to the gate terminal of the third PMOS transistor 244a. In some embodiments, the second switched capacitor circuit includes a third capacitor 274a and a fourth capacitor 274b, each capacitor coupled to the second output 232b of the first amplifier stage 20a. In some embodiments, the third capacitor 274a is coupled to the gate terminal of the fourth NMOS transistor 246b. In some embodiments, the fourth capacitor 274b is coupled to the gate terminal of the fourth PMOS transistor 244b.

[0071] In some embodiments, the first switched capacitor circuit includes a first switch 262a and a second switch 262b. The first switch 262a and the second switch 262b can each be referred to as a bias switch. The first end of the first switch 262a can be coupled to the capacitor 272a and the gate of the third NMOS transistor 246a, and the second end of the first switch 262a can be coupled to the bias voltage 282a. The first end of the second bias switch 262b can be coupled to the capacitor 272b and the gate of the third PMOS transistor 244a, and the second end of the second bias switch 262b can be coupled to the bias voltage 282b.

[0072] In some embodiments, the second switched capacitor circuit includes a third switch 264a and a fourth switch 264b. The third switch 264a and the fourth switch 264b may each be referred to as a bias switch. A first end of the third switch 264a may be coupled to the capacitor 274a and the gate of the fourth NMOS transistor 246b, and a second end of the third switch 264a may be coupled to a bias voltage 282a. A first end of the fourth switch 264b may be coupled to the capacitor 274b and the gate of the fourth PMOS transistor 244b, and a second end of the fourth switch 264b may be coupled to a bias voltage 282b. In some embodiments, the bias voltage 282a corresponds to or otherwise defines the gate potential of the third NMOS transistor 246a and the fourth NMOS transistor 246b. In some embodiments, the bias voltage 282b corresponds to or otherwise defines the gate potential of the third PMOS transistor 244a and the fourth PMOS transistor 244b.

[0073] In this regard, the gate terminals of the third NMOS transistor 246a and the fourth NMOS transistor 246b are selectively coupled to the bias voltage 282a via the first switch 262a and the third switch 264a, and the gate terminals of the third PMOS transistor 244a and the fourth PMOS transistor 244b are selectively coupled to the bias voltage 282b via the first switch 262a and the fourth switch 264b.

[0074] In some embodiments, the switches 262a, 262b, 264a, 264b are configured to facilitate multi-stage operation of the example operational amplifier 200. For example, as described above, in some embodiments, the operational amplifier 200 may be configured to operate in a first stage corresponding to a bias stage and a second stage corresponding to an amplification stage. In some embodiments, in the first stage (e.g., the bias stage), the switches 262a, 262b, 264a, 264b are closed (e.g., in a closed state), such that the third NMOS transistor 246a and the fourth NMOS transistor 246b are coupled to the bias voltage 282a, and such that the gate terminals of the third PMOS transistor 244a and the fourth PMOS transistor 244b are coupled to the bias voltage 282b. In some embodiments, in the second stage (e.g., the amplification stage), the switches 262a, 262b, 264a, 264b are open (e.g., in an open state), such that changes in the input are reflected on the gates of each of the PMOS and NMOS transistors (e.g., 244a, 244b, 246a, 246b) of the inverter pair 24a, 24b of the second amplifier stage 20b, while the center points about which they vary remain at the gate potential / bias voltage 282a, 282b.

[0075] In some embodiments, the bias capacitors 272a, 272b, 274a, 274b may be refreshed (e.g., periodically) with bias voltages 282a, 282b during a bias phase (e.g., when the operational amplifier 200 is not in use) and used as a floating battery between an input and the gate terminals of the PMOS and NMOS transistors of the inverter pairs 24a, 24b of the second amplifier stage 20b. As described above, the input may include or otherwise correspond to the first output 232a and the second output 232b of the first amplifier stage 20a.

[0076] In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of a third PMOS transistor 244a and a third NMOS transistor 246a. In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a first RC circuit including a resistor and a capacitor. In some embodiments, the second output 232b of the first amplifier stage is coupled to a fourth capacitor 274b of the second amplifier stage 20b and the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the second output 232b of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a second RC circuit including a resistor and a capacitor.

[0077] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and form or otherwise define a first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the drain terminal of the fourth NMOS transistor 246b are coupled together and form or otherwise define a second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. In some embodiments, the first output 252a and the second output 252b of the second amplifier stage 20b are coupled to a common-mode feedback circuit 30. For example, in some embodiments, the first output 252a and the second output 252b are provided as inputs to the common-mode feedback circuit 30.

[0078] As described above, the example operational amplifier 200 is capable of operating in two phases. In some embodiments, the operational amplifier 200 is capable of operating in a first phase representing a bias phase and a second phase representing an amplification phase. Figure 3 FIG. illustrates a flowchart of the operation of an example operational amplifier in a bias phase in accordance with at least one example embodiment of the present disclosure. Specifically, Figure 3 an example process 300 is depicted. In some embodiments, the example method 300 may be implemented by the example operational amplifier 200 described herein in connection with Figure 2 the description.

[0079] According to some examples, the method includes, at operation 302, turning on the amplification switches of the operational amplifier. For example, the example method includes turning on switches 228a, 228b of the inverter coupled to the first amplifier stage 20a and turning on switches 248a and 248b coupled to the second amplifier stage 20b, such that the inverter pairs of the first amplifier stage and the inverter pairs of the second amplifier stage are disconnected from their respective supplies and grounds.

[0080] According to some examples, the method includes, at operation 304, closing the bias switches of the operational amplifier. For example, the example method includes closing switches 262a, 262b, 264a, 264b of the inverter coupled to the second amplifier stage 20b and closing switches 276a, 276b coupled to the first output and the second output of the first amplifier stage 20a. In this regard, by closing the bias switches of the PMOS and NMOS transistors coupled to the second stage, the corresponding bias potentials are applied to each gate of the PMOS and NMOS transistors of the second stage. For example, in some embodiments, the gate terminals of the PMOS and NMOS transistors of the inverter of the second amplifier stage are coupled to their respective bias potentials during the bias phase. For example, PMOS transistors 244a, 244b are coupled to bias voltage 282b, and NMOS transistors 246a, 246b are coupled to bias voltage 282a. In this regard, by closing the bias switches coupled to the first output 232a and the second output 232b of the first amplifier stage 20a, the first and second outputs of the first amplifier stage are coupled to voltage 278, for example, switched to a fixed voltage. In this regard, in some embodiments, the voltage drops (e.g., “Vbp - VCM1” and “Vbn - VCM1”) are stored across the bias capacitors. In some embodiments, this stored voltage drop is used as a floating battery during the amplification phase to set an appropriate current bias in the second amplifier stage.

[0081] In this regard, during the bias phase, both the first amplifier stage and the second amplifier stage are turned off. For example, during the bias phase, neither the first amplifier stage nor the second amplifier stage consumes current. Thus, embodiments of the present disclosure promote efficient power consumption in various applications. For example, in a pipelined ADC that includes a sampling phase and a multiplication phase, where the operational amplifier is used during the multiplication phase but not during the sampling phase. In such an example, the operational amplifier can be operated in the bias phase as described herein during the sampling phase of the pipelined ADC.

[0082] Figure 4A A flowchart depicting the operation of an example operational amplifier in an amplification phase in accordance with at least one example embodiment of the present disclosure is illustrated. Specifically, Figure 4A An example process 400 is depicted. In some embodiments, the example method 400 can be implemented by the example operational amplifier 200 described herein in connection with Figure 2 the description.

[0083] According to some examples, the method includes, at operation 402, turning on the bias switches of the operational amplifier. For example, the example method includes turning on switches 262a, 262b, 264a, 264b of the inverter coupled to the second amplifier stage 20b, and turning on switches 276a, 276b coupled to the first output and the second output of the first amplifier stage 20a. In this regard, by turning on the bias switches of the PMOS and NMOS transistors of the second amplifier stage 20b, the corresponding bias potentials are not applied to the gates of the PMOS and NMOS transistors of the second amplifier stage 20b. For example, in some embodiments, during the amplification phase, the gate terminals of the PMOS and NMOS transistors of the inverter of the second amplifier stage 20b are not coupled to their respective bias potentials. For example, PMOS transistors 244a, 244b are not coupled to bias voltage 282b, and NMOS transistors 246a, 246b are not coupled to bias voltage 282a. In this regard, by turning on the bias switches coupled to the first output and the second output of the first amplifier, the first and second outputs of the first amplifier stage are not coupled to voltage 278, for example, do not switch to a fixed voltage.

[0084] According to some examples, the method includes, at operation 404, closing the amplification switches of the operational amplifier. For example, the example method includes closing switches 228a, 228b of the inverter coupled to the first amplifier stage 20a, and closing switches 248a and 248b coupled to the second amplifier stage 20b, such that the inverter pairs of the first amplifier stage and the inverter pairs of the second amplifier stage are connected to their respective supplies and grounds.

[0085] According to some examples, the method includes applying an operational amplifier at operation 406. In some embodiments, applying the operational amplifier includes causing a first inverter stage to generate an output voltage input to a second amplifier stage and causing the second amplifier stage to generate an output.

[0086] Figure 4B Provided is an example timing diagram corresponding to a bias phase and an amplification phase in accordance with at least one example embodiment of the present disclosure. As Figure 4B shown, in some embodiments, the operation phases (e.g., bias phase 420 and amplification phase 440) are non-overlapping.

[0087] Figure 5 Illustrated is an example operational amplifier 200 in accordance with at least one embodiment of the present disclosure. Specifically, Figure 5 Illustrated is an example continuous-time implementation of an example operational amplifier circuit in accordance with at least one embodiment of the present disclosure. The operational amplifier 500 includes aspects, parts, etc. similar to the example operational amplifier 500. Thus, aspects Figure 2 similar and already incorporated Figure 2 shown are depicted in Figure 5 with the same reference numerals.

[0088] Figure 5 The example operational amplifier 500 shown in may be configured to have a continuous current flowing through the operational amplifier 500. In this regard, the operational amplifier 500 may operate in a single stage. In some embodiments, Figure 5 the operational amplifier 500 shown in includes a first amplifier stage 20a corresponding to an input stage of the operational amplifier and a second amplifier stage 20b corresponding to an output stage of the operational amplifier 500. The first amplifier stage 20a and the second amplifier stage 20b may include gain stages of the operational amplifier 500. In some embodiments and as Figure 5 shown in, each amplifier stage (e.g., the first amplifier stage 20a and the second amplifier stage 20b) includes an inverter.

[0089] In some embodiments, a first amplifier stage 20a representing an input stage of an exemplary operational amplifier includes a first inverter 22a and a second inverter 22b. In some embodiments, the first inverter 22a includes a first PMOS transistor 224a and a first NMOS transistor 226a. In some embodiments, the second inverter 22b includes a second PMOS transistor 224b and a second NMOS transistor 226b. The first inverter 22a and the second inverter 22b may be configured to operate in a differential manner. For example, in some embodiments, the first inverter 22a and the second inverter 22b include differential inverters or otherwise function as differential inverters. It should be appreciated that in some embodiments, the first inverter 22a and the second inverter 22b may include different inverter configurations. For example, in some embodiments, the first inverter 22a may include different types of transistors and / or transistors arranged in different configurations.

[0090] In some embodiments, the gate terminals of the first PMOS transistor 224a and the first NMOS transistor 226a are each coupled to a first input 220a. In some embodiments, the gate terminals of the second PMOS transistor 224b and the second NMOS transistor 226b are each coupled to a second input 220b. For example, in some embodiments, the gate terminals of each of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together, and the gate terminals of each of the second PMOS transistor 224b and the second NMOS transistor 226b are coupled together.

[0091] In some embodiments, the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a are coupled together and define a first output 232a of the first amplifier stage 20a. In some embodiments, the drain terminal of the second PMOS transistor 224b and the gate terminal of the second NMOS transistor 226b are coupled together and define a second output 232b of the first amplifier stage 20a. For example, in some embodiments, the first amplifier stage 20a is configured to output the first output 232a via the drain terminals of the first PMOS transistor 224a and the first NMOS transistor 226a, and to output the second output 232b via the drain terminals of the second PMOS transistor 224b and the second NMOS transistor 226b. In some embodiments, the first output 232a and the second output 232b of the first inverter stage are coupled to a second amplifier stage 20b. For example, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b.

[0092] In some embodiments, the first output 232a and the second output 232b of the first amplifier stage 20a are coupled to the second amplifier stage 20b. As described herein, in some embodiments, the first output 232a and the second output 232b are provided as inputs to the second amplifier stage 20b. In some embodiments, the first output 232a is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the first output 232a is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a first RC circuit, where the first RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the first output 232a is coupled to a first resistor, where the resistor is coupled to voltage 278.

[0093] In some embodiments, the second output 232b is capacitively coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b). Additionally or alternatively, in some embodiments, the second output 232b is coupled to a portion of the second amplifier stage 20b (e.g., coupled to one or more components of the second amplifier stage 20b) via a second RC circuit, where the second RC circuit includes a resistor and a capacitor. Additionally or alternatively, in some embodiments, the second output 232b is coupled to a second resistor, where the resistor is coupled to voltage 278.

[0094] In some embodiments, the source terminals of the first NMOS transistor 226a and the second NMOS transistor 226b are coupled to a first cascode transistor 222a configured to define a bias current. As Figure 5 shown, in some embodiments, the gate terminal of the first cascode transistor 222a is coupled to a bias voltage 230 (e.g., defining the gate potential of the first cascode transistor 222a). For example, the first cascode transistor 222a may be connected to a bias current circuit 201. In this regard, the first inverter 22a and the second inverter 22b may have input currents of the first and second inverters 22a, 22b biased by the first cascode transistor 222a. Although the first cascode transistor 222a is Figure 2 depicted as an NMOS-type transistor, it should be appreciated that the first cascode transistor 222a may be of a different type, such as a PMOS-type.

[0095] As described above in connection with Figure 2As described, embodiments of the present disclosure mitigate the effects of any variations in the input common mode by utilizing a common-tail transistor 222a at a first amplifier stage (e.g., an input stage) to define a bias current at the input stage of the operational amplifier 500 and by utilizing another common-tail transistor 222b at the input stage to apply common-mode feedback, thereby providing common-mode stability. For example, the absence of a common-tail transistor may result in a poor common-mode rejection ratio (CMRR).

[0096] In some embodiments, the source terminal of the first PMOS transistor 224a and the source terminal of the second PMOS transistor 224b are coupled to the second common-tail transistor 222b. In some embodiments, the gate terminal of the second common-tail transistor 222b is coupled to a common-mode feedback circuit 30 (depicted as a functional block for illustrative purposes of the example operational amplifier 500). For example, the gate voltage of the second common-tail transistor 222b may be controlled by the output of the common-mode feedback circuit 30. Although the second common-tail transistor 222b is depicted as a PMOS-type transistor in Figure 5 , it should be appreciated that the second common-tail transistor 222b may be an NMOS-type.

[0097] In some embodiments, and as Figure 2 shown, the first amplifier stage 20a does not include a bias capacitor. In this regard, the first amplifier stage 20a will not be associated with a bias capacitor or otherwise generate KT / C noise caused by a bias capacitor. Thus, embodiments of the present disclosure provide an operational amplifier with low noise, which is at least in part due to the absence of a bias capacitor in the first amplifier stage (e.g., the input stage).

[0098] As shown, in some embodiments, the PMOS and NMOS transistors of the first amplifier stage are configured to act as drivers. By using both PMOS and NMOS transistors as drivers, the transconductance (e.g., g m ) of the first amplifier stage 20a is effectively doubled. For example, when both the NMOS transistor and the PMOS transistor have the same transconductance, the transconductance of the operational amplifier 500 is effectively doubled, which in turn facilitates lower noise, higher bandwidth, and lower current consumption.

[0099] In some embodiments, a second amplifier stage 20b corresponding to the output stage of the exemplary operational amplifier 500 includes a third inverter 24a and a fourth inverter 24b. In some embodiments, the third inverter 24a includes a third PMOS transistor 244a and a third NMOS transistor 246a. In some embodiments, the fourth inverter 24b includes a fourth PMOS transistor 244b and a fourth NMOS transistor 246b. In some embodiments, the third inverter 24a and the fourth inverter 24b are configured to operate in a differential manner. For example, in some embodiments, the third inverter 24a and the fourth inverter 24b include differential inverters or otherwise function as differential inverters. It should be appreciated that in some embodiments, the third inverter 24a and the fourth inverter 24b may include different inverter configurations. For example, in some embodiments, the third inverter 24a may include different types of transistors and / or transistors arranged in different configurations.

[0100] In some embodiments, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are each coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are each coupled to the second output 232b of the first amplifier stage 20a. As further described herein, in some embodiments, the gate terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a.

[0101] In some embodiments, the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a are coupled together and define a first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b are coupled together and define a second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and to output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b.

[0102] In some embodiments, the source terminal of the fourth NMOS transistor 246b and the source terminal of the fourth NMOS transistor 246b are coupled to ground 290a. In some embodiments, the source terminal of the third PMOS transistor 244a and the source terminal of the fourth PMOS transistor 244b are coupled to voltage supply 290b.

[0103] As described above, in some embodiments, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a of the first amplifier stage 20a, and the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b of the first amplifier stage 20a. In this regard, in some embodiments, the second amplifier stage 20b is capacitively biased. In some embodiments and as Figure 5 depicted, the second amplifier stage 20b includes a first capacitor circuit (which may also be referred to as a first RC circuit) coupled to the third inverter 24a. For example, the gate terminal of the third PMOS transistor 244a and the gate terminal of the third NMOS transistor 246a are capacitively coupled to the first output 232a via the first capacitor circuit, where a portion of the first capacitor circuit may be coupled to the gate terminal of the third PMOS transistor 244a, and a portion of the first capacitor circuit may be coupled to the gate terminal of the third NMOS transistor 246a. Additionally or alternatively, in some embodiments, the second amplifier stage 20b includes a second capacitor circuit (which may also be referred to as a second RC circuit) coupled to the fourth inverter 24b. For example, the gate terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are capacitively coupled to the second output 232b via the second capacitor circuit, where a portion of the second capacitor circuit may be coupled to the gate terminal of the fourth PMOS transistor 244b, and a portion of the second capacitor circuit may be coupled to the gate terminal of the fourth NMOS transistor 246b.

[0104] In some embodiments, the first capacitor circuit includes a first capacitor 272a and a second capacitor 272b, each capacitor coupled to the first output 232a of the first amplifier stage 20a. In some embodiments, the second capacitor circuit includes a third capacitor 274a and a fourth capacitor 274b, each capacitor coupled to the second output 232b of the first amplifier stage 20a.

[0105] In some embodiments, the first capacitor circuit includes a first resistor 562a and a second resistor 562b, which are configured to facilitate the biasing of the third PMOS transistor 244a and the third NMOS transistor 246a, respectively. A first end of the first resistor 562a may be coupled to the capacitor 272a and the gate of the third NMOS transistor 246a, and a second end of the first resistor 562a may be coupled to the bias voltage 282a. A first end of the second resistor 562b may be coupled to the capacitor 272b and the gate of the third PMOS transistor 244a, and a second end of the second resistor 562b may be coupled to the bias voltage 582b.

[0106] In some embodiments, the second capacitor circuit includes a third resistor 564a and a fourth resistor 564b, which are configured to facilitate the biasing of the fourth MOS transistor 244b and the fourth NMOS transistor 246b, respectively. A first end of the third resistor 564a may be coupled to the capacitor 274a and the gate of the fourth NMOS transistor 246b, and a second end of the third resistor 564a may be coupled to the bias voltage 282a. A first end of the fourth resistor 564b may be coupled to the capacitor 274b and the gate of the fourth PMOS transistor 244b, and a second end of the fourth resistor 564b may be coupled to the bias voltage 582b. In some embodiments, the bias voltage 282a corresponds to or otherwise defines the gate potential of the third NMOS transistor 246a and the fourth NMOS transistor 246b. In some embodiments, the bias voltage 282b corresponds to or otherwise defines the gate potential of the third PMOS transistor 244a and the fourth PMOS transistor 244b.

[0107] In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the first capacitor circuit of the second amplifier stage 20b (e.g., at a node between the first capacitor 272a and the second capacitor 272b) and the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the first output 232a of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a first RC circuit including a resistor and a capacitor.

[0108] In some embodiments, the second output 232b of the first amplifier stage is coupled to the second capacitor circuit of the second amplifier stage 20b (e.g., at the node between the third capacitor 274a and the fourth capacitor 274b) and the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a. In some embodiments, the second output 232b of the first amplifier stage 20a is coupled to the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a via a second RC circuit including a resistor and a capacitor.

[0109] In some embodiments, the drain terminal of the third PMOS transistor 244a and the drain terminal of the third NMOS transistor 246a are coupled together and define the first output 252a of the second amplifier stage 20b. In some embodiments, the drain terminal of the fourth PMOS transistor 244b and the gate terminal of the fourth NMOS transistor 246b are coupled together and define the second output 252b of the second amplifier stage 20b. For example, in some embodiments, the second amplifier stage 20b is configured to output the first output 252a via the drain terminals of the third PMOS transistor 244a and the third NMOS transistor 246a, and output the second output 252b via the drain terminals of the fourth PMOS transistor 244b and the fourth NMOS transistor 246b. In some embodiments, the first output 252a and the second output 252b of the second amplifier stage 20b are coupled to the common mode feedback circuit 30. For example, in some embodiments, the first output 252a and the second output 252b are provided as inputs to the common mode feedback circuit 30.

[0110] Conclusion

[0111] Those skilled in the art to which the present disclosure pertains, having the benefit of the foregoing description and the teachings presented in the related drawings, will envision many modifications and other embodiments of the present disclosure set forth herein. Accordingly, it is to be understood that the embodiments are not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description and the related drawings describe example embodiments in the context of certain example combinations of elements and / or functions, it should be recognized that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, combinations of elements and / or functions different from those explicitly described above are also contemplated, as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a general and descriptive sense only and not for purposes of limitation.

[0112] Although this specification contains many specific implementation details, these should not be construed as limitations on any disclosed scope or the scope that may be claimed, but rather as descriptions of features specific to particular embodiments of a particular disclosure. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Moreover, although the features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features of the claimed combination can be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variant of the sub-combination.

[0113] Similarly, although the operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. Moreover, the separation of the various system components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0114] Accordingly, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the acts recited in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In some implementations, multitasking and parallel processing can be advantageous.

[0115] In addition, although this detailed description has set forth some embodiments of the present disclosure, the appended claims can cover other embodiments of the present disclosure that are different from the described embodiments according to various modifications and improvements. For example, in some embodiments, the first amplifier stage and / or the second amplifier stage can include transistors of different types. As another example, in some embodiments, the transistors of the first amplifier stage and / or the transistors of the second amplifier can be arranged and / or coupled in different ways without departing from the scope of the present disclosure.

[0116] In addition, within the appended claims, unless the specific terms "means for... " or "step for... " are used in a given claim, it is not intended to invoke 35 U.S.C. § 112, paragraph (f) to interpret that claim.

Claims

1. An operational amplifier, characterized in that: include: An input stage, the input stage comprising: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common-tail transistor being configured to define a bias current; and a second common-tail transistor selectively coupled to the first inverter and the second inverter via a second switch; and An output stage, the output stage comprising: a third inverter and a fourth inverter coupled together, the third inverter and the fourth inverter selectively coupled to a supply voltage via a third switch and selectively coupled to ground via a fourth switch; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and A second capacitive coupling is configured to couple the fourth inverter to a second output of the input stage.

2. The operational amplifier according to claim 1, wherein: The first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and The second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

3. The operational amplifier according to claim 2, wherein: The first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; and The first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

4. The operational amplifier according to claim 1, wherein: The third inverter includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor and the third NMOS transistor being coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

5. The operational amplifier according to claim 4, wherein: The third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; and The third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

6. The operational amplifier according to claim 5, wherein: a gate terminal of the third PMOS transistor and a gate terminal of the third NMOS transistor coupled to a first output of the input stage via the first capacitive coupling; as well as A gate terminal of the fourth PMOS transistor and a gate terminal of the fourth NMOS transistor are coupled to a second output of the input stage via the second capacitive coupling.

7. The operational amplifier according to claim 1, wherein: The first capacitive coupling includes a first switched capacitor circuit.

8. The operational amplifier according to claim 1, wherein: The second capacitive coupling includes a second switched capacitor circuit.

9. The operational amplifier according to claim 1, wherein: Also includes: A bias current circuit is coupled to the first common-tail transistor.

10. The operational amplifier according to claim 1, wherein: Also includes: A common-mode feedback circuit is coupled to the second common-tail transistor.

11. The operational amplifier according to claim 1, wherein: The operational amplifier is configured to operate in one or more of a biasing phase and an amplification phase.

12. The operational amplifier according to claim 11, wherein: In the bias phase, each of the first switch, the second switch, the third switch, and the fourth switch is in an open state.

13. An operational amplifier, characterized in that: include: An input stage, the input stage comprising: a first inverter and a second inverter coupled together and configured to operate in a differential manner; a first common-tail transistor coupled to the first inverter and the second inverter, the first common-tail transistor being configured to define a bias current; and a second common-tail transistor coupled to the first inverter and the second inverter; and An output stage, the output stage comprising: a third inverter and a fourth inverter coupled together; a first capacitive coupling configured to couple the third inverter to a first output of the input stage; and A second capacitive coupling is configured to couple the fourth inverter to a second output of the input stage.

14. The operational amplifier according to claim 13, wherein: The first inverter includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; and The second inverter includes a second PMOS transistor and a second NMOS transistor, which are coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor.

15. The operational amplifier according to claim 14, wherein: The first PMOS transistor and the second PMOS transistor are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor; and The first NMOS transistor and the second NMOS transistor are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor.

16. The operational amplifier according to claim 13, wherein: The third inverter includes a third PMOS transistor and a third NMOS transistor, the third PMOS transistor and the third NMOS transistor being coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor; and The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor, which are coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor.

17. The operational amplifier according to claim 16, wherein: The third PMOS transistor and the fourth PMOS transistor are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor; and The third NMOS transistor and the fourth NMOS transistor are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor.

18. The operational amplifier according to claim 17, wherein: a gate terminal of the third PMOS transistor and a gate terminal of the third NMOS transistor coupled to a first output of the input stage via the first capacitive coupling; as well as A gate terminal of the fourth PMOS transistor and a gate terminal of the fourth NMOS transistor are coupled to a second output of the input stage via the second capacitive coupling.

19. The operational amplifier according to claim 13, wherein: Also includes: A bias current circuit is coupled to the first common-tail transistor.

20. The operational amplifier according to claim 13, wherein: Also includes: A common-mode feedback circuit is coupled to the second common-tail transistor.

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