Multiplexing sampling system and electronic equipment

Abstract

The utility model discloses a multiplexing sampling system and an electronic device, the multiplexing sampling system comprises a main control chip, a preprocessing circuit and a plurality of single-path sampling circuits, and each single-path sampling circuit comprises an analog switch sub-circuit and an analog-to-digital conversion sub-circuit; the analog switch sub-circuit is configured to determine a working state according to a control signal output by the main control chip and a preprocessing signal output by the preprocessing circuit, and when the working state is gating, an analog signal output by the signal input end is transmitted to the analog conversion sub-circuit; the analog-to-digital conversion sub-circuit is configured to convert an analog signal into a digital signal; the main control chip is configured to control the working state of the analog switching circuit and read the digital signal output by the analog switching circuit; the pre-processing circuit is configured to pre-process the control signal and the clock signal. The multiplexing sampling system provided by the embodiment of the utility model can obtain a group of high-sampling-rate data in a low-cost manner, so that the sampling rate of the system is multiplied.

Description

Technical Field

[0001] This application relates to the technical field of analog-to-digital conversion, and more particularly to a multiplexed sampling system and an electronic device. Background Art

[0002] In the field of data acquisition, the communication rate of the device under test is getting higher and higher, and the requirement for the signal restoration ability of the test device is also getting higher and higher. For signal acquisition, it means the need for high sampling bits and high sampling rates. Most of the ADCs (Analog-to-Digital Converters) in the related art cannot meet the requirements of high sampling bits and high sampling rates at the same time, and the price of ADC chips that meet both requirements is relatively expensive, which is not conducive to mass production of products and will also increase the difficulty of product software development. Summary of the Utility Model

[0003] The present utility model is proposed to solve at least one of the above problems. According to a first aspect of the present application, there is provided a multiplexed sampling system, the sampling system comprising: a main control chip, a preprocessing circuit, and a plurality of single-channel sampling circuits, wherein the single-channel sampling circuit comprises an analog switch sub-circuit and an analog-to-digital conversion sub-circuit; the analog switch sub-circuit, connected to the main control chip, the preprocessing circuit, the analog-to-digital conversion sub-circuit, and a signal input terminal, is configured to determine an operating state according to a control signal output by the main control chip and a preprocessing signal output by the preprocessing circuit, and when the operating state is gated, transmit an analog signal output by the signal input terminal to the analog conversion sub-circuit, wherein the operating state includes gated and ungated; the analog-to-digital conversion sub-circuit, configured to convert the analog signal into the digital signal; the main control chip, respectively connected to the analog switch sub-circuit and the analog-to-digital conversion sub-circuit, is configured to control the operating state of the analog switch circuit and read the digital signal output by the analog conversion circuit; the preprocessing circuit, respectively connected to the analog switch sub-circuit, the main control chip, and a clock signal generation module, is configured to preprocess the control signal and a clock signal output by the clock signal generation module, and output the preprocessing signal.

[0004] In an embodiment of the present application, the analog switch sub-circuit comprises: a first comparator, a second comparator, and an analog switch; a first input terminal of the first comparator and a first input terminal of the second comparator are connected to the main control chip, a second input terminal of the first comparator and a second input terminal of the second comparator are connected to the preprocessing circuit, an output terminal of the first comparator is connected to a first input terminal of the analog switch, a second input terminal of the analog switch is connected to the signal input terminal, and an output terminal of the analog switch and an output terminal of the second comparator are connected to the main control chip.

[0005] In one embodiment of the present application, the single-channel sampling circuit further includes: an RC level holding sub-circuit, a first end of the RC level holding sub-circuit is connected between an output end of the first comparator and a first input end of the analog switch, and a second end of the RC level holding sub-circuit is grounded.

[0006] In one embodiment of the present application, the RC level holding sub-circuit includes a first resistor and a first capacitor, the first resistor is connected in parallel with the first capacitor, a first end of the first capacitor is connected between an output end of the first comparator and a first input end of the analog switch, and a second end of the first capacitor is grounded.

[0007] In one embodiment of the present application, denoting the number of the single-channel sampling circuits as n, the preprocessing circuit includes: a first preprocessing sub-circuit to an (n - 1)-th preprocessing sub-circuit; the first preprocessing sub-circuit to the (n - 1)-th preprocessing sub-circuit are respectively and correspondingly connected to n - 1 of the single-channel sampling circuits, wherein n is greater than or equal to 2.

[0008] In one embodiment of the present application, the first preprocessing sub-circuit includes a second resistor and two diodes; a first end of the second resistor is connected to a preset power supply, a negative electrode of one of the diodes in the first preprocessing sub-circuit is connected to the clock signal generation module, a negative electrode of the other diode is connected to the main control chip, and a second end of the second resistor and positive electrodes of the two diodes are respectively connected to the analog switch sub-circuit; the (n - 1)-th preprocessing sub-circuit includes an n-th resistor and n diodes; a first end of the n-th resistor is connected to a preset power supply, a negative electrode of one of the diodes in the n-th preprocessing sub-circuit is connected to the clock signal generation module, negative electrodes of the remaining diodes are connected to the main control chip, and a second end of the n-th resistor and positive electrodes of the n diodes are respectively connected to the analog switch sub-circuit.

[0009] In one embodiment of the present application, the analog-to-digital conversion sub-circuit includes an ADC driver; an input end of the ADC driver is connected to the analog switch, and a first output end and a second output end of the ADC driver are connected to the main control chip.

[0010] In one embodiment of the present application, the analog-to-digital conversion sub-circuit further includes a gain module, connected to the ADC driver and configured to perform gain on an output of the ADC driver.

[0011] In one embodiment of the present application, the single-channel sampling circuit further includes: a filtering sub-circuit, connected between the ADC driver and the main control chip.

[0012] In one embodiment of the present application, the filtering sub - circuit includes: a second capacitor, a third capacitor, a fourth capacitor, a first voltage - dividing resistor, and a second voltage - dividing resistor; the second capacitor, the third capacitor, and the fourth capacitor are connected in series in sequence, the first end of the second capacitor is grounded, the second end of the second capacitor is connected to the first output end of the ADC driver through the first voltage - dividing resistor, the first end of the fourth capacitor is connected to the second output end of the ADC driver through the second voltage - dividing resistor, and the second end of the fourth capacitor is grounded.

[0013] In one embodiment of the present application, the number of the main control chips is multiple, and the multiple main control chips are connected to the multiple single - channel sampling circuits in one - to - one correspondence.

[0014] According to the second aspect of the present application, an electronic device is provided, and the electronic device includes: any one of the above - mentioned multiplexed sampling systems.

[0015] According to the multiplexed sampling system and the electronic device provided by the embodiments of the present application, in the multiplexed sampling system of the present application, a plurality of single - channel sampling circuits with low sampling rates jointly sample an analog signal, and can obtain a set of high - sampling - rate data in a low - cost manner, so that the sampling rate of the system is increased exponentially. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic structural diagram of a multiplexed sampling system provided by an embodiment of the present invention;

[0018] Figure 2 It is a schematic structural diagram of an analog switch sub - circuit provided by an embodiment of the present invention;

[0019] Figure 3 It is a schematic structural diagram of an analog - to - digital conversion sub - circuit provided by an embodiment of the present invention;

[0020] Figure 4 It is a schematic flow chart of the working process of a main control chip provided by an embodiment of the present invention;

[0021] Figure 5 It is a sampling trigger timing diagram provided by an embodiment of the present invention;

[0022] Figure 6The circuit schematic diagram of the multiplexing sampling system provided by an embodiment of the present utility model;

[0023] Figure 7 The structural schematic diagram of the electronic device provided by an embodiment of the present utility model. Detailed implementation manners

[0024] In order to make the objectives, technical solutions and advantages of the present utility model more apparent, exemplary embodiments according to the present utility model will be described in detail below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments of the present utility model. It should be understood that the present utility model is not limited by the exemplary embodiments described herein. Based on the embodiments of the present utility model described herein, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present utility model.

[0025] In the following description, numerous specific details are given to provide a more thorough understanding of the present utility model. However, it is obvious to those skilled in the art that the present utility model can be implemented without one or more of these details. In other instances, some well-known technical features are not described in order to avoid confusion with the present utility model.

[0026] It should be understood that the present utility model can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present utility model to those skilled in the art.

[0027] To thoroughly understand the present utility model, detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present utility model. The optional embodiments of the present utility model are described in detail below. However, in addition to these detailed descriptions, the present utility model can also have other implementation manners.

[0028] The following will describe in detail some implementation manners of the present utility model with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] This application provides a multiplexing sampling system, as Figure 1 shown, the multiplexing sampling system 10 includes: a main control chip 101, a preprocessing circuit 102, and a plurality of single-channel sampling circuits 103. Among them, the single-channel sampling circuit 103 includes an analog switch sub-circuit 1031 and an analog-to-digital conversion sub-circuit 1032.

[0030] It should be noted that Figure 1The number of single-channel sampling circuits 103 given in [reference] is 2, which is only an example. The specific number of single-channel sampling circuits 103 can be determined according to the actual application situation.

[0031] The analog switch sub-circuit 1031 is connected to the main control chip 101, the preprocessing circuit 102, the analog-to-digital conversion sub-circuit 1032, and the signal input terminal 20, and is configured to determine the working state according to the control signal output by the main control chip 101 and the preprocessing signal output by the preprocessing circuit 102. When the working state is gated, the analog signal output from the signal input terminal is transmitted to the analog conversion sub-circuit, where the working state includes gated and ungated.

[0032] As an example, the signal input terminal includes, but is not limited to, various analog signals.

[0033] The analog-to-digital conversion sub-circuit 1032 is configured to convert the analog signal into a digital signal.

[0034] As an example, if the number of single-channel sampling circuits 103 is n, the overall sampling rate of the multiplexed sampling system 10 of the present application is equal to n times the sampling rate of the single-channel sampling circuit 103. Users can configure the number of corresponding single-channel sampling circuits 103 according to their needs.

[0035] The main control chip 101 is respectively connected to the analog switch sub-circuit 1031 and the analog-to-digital conversion sub-circuit 1032, and is configured to control the working state of the analog switch circuit and read the digital signal output by the analog conversion circuit.

[0036] It should be noted that the main control chip 101 can be various single-chip microcomputers, FPGAs (Field Programmable Gate Arrays), and other chips with a control core. The main control chip 101 can start the corresponding single-channel sampling circuit 103 in turn according to the sampling rate configured by the system for data conversion and reading (the communication methods of the main control chip 101 include, but are not limited to, common serial communication, SPI (Serial Peripheral Interface) communication, I2C (Inter-Integrated Circuit) communication, parallel port, etc.), so as to obtain a set of sampling data output by multiple single-channel sampling circuits 103, thereby improving the sampling rate of the entire system.

[0037] Specifically, the number of main control chips 101 can be multiple, and multiple main control chips 101 are connected to multiple single-channel sampling circuits 103 in one-to-one correspondence.

[0038] The preprocessing circuit 102 is respectively connected to the analog switch sub-circuit 1031, the main control chip 101, and the clock signal generation module, and is configured to preprocess the control signal and the clock signal output by the clock signal generation module, and output a preprocessed signal.

[0039] In the multiplexed sampling system 10 according to the embodiment of the present invention, a plurality of single-channel sampling circuits 103 with low sampling rates jointly sample an analog signal, and can obtain a set of high-sampling-rate data in a low-cost manner, so that the sampling rate of the system is doubled.

[0040] In some embodiments, as Figure 2 shown, the analog switch sub-circuit 1031 includes: a first comparator U1, a second comparator U2, and an analog switch K1; the first input terminal of the first comparator U1 and the first input terminal of the second comparator U2 are connected to the main control chip 101, the second input terminal of the first comparator U1 and the second input terminal of the second comparator U2 are connected to the preprocessing circuit 102, the output terminal of the first comparator U1 is connected to the first input terminal of the analog switch K1, the second input terminal of the analog switch K1 is connected to the signal input terminal, and the output terminal of the analog switch K1 and the output terminal of the second comparator U2 are connected to the main control chip 101.

[0041] As an example, the control signals of the main control chip 101 include a plurality of conversion busy signals (CNV_BUSY), and the number of conversion busy signals is the same as the number of single-channel sampling circuits 103. The first input terminal 1IN- of the first comparator U1 and the first input terminal 2IN- of the second comparator U2 receive the conversion busy signal, the second input terminal 1IN+ of the first comparator U1 and the second input terminal 2IN+ of the second comparator U2 receive the preprocessed signal output by the preprocessing circuit 102, the output terminal 1OUT of the first comparator U1 outputs an analog switch gating signal to the analog switch K1, and the output terminal 2OUT of the second comparator U2 outputs a CNV conversion signal to the main control chip 101. The main control chip 101 reads the digital signal output by the single-channel sampling circuit 103 corresponding to the CNV conversion signal according to the CNV conversion signal.

[0042] Optionally, when the corresponding single-channel sampling circuit 103 needs to work, the conversion busy signal corresponding to the single-channel sampling circuit 103 is at a low level, otherwise it is at a high level.

[0043] In this embodiment, through the settings of the first comparator U1 and the second comparator U2, the comparison and selection of signals can be realized to meet different sampling requirements.

[0044] In some embodiments, as Figure 2As shown in the figure, the single-channel sampling circuit 103 further includes: an RC level holding sub-circuit 1033. The first end of the RC level holding sub-circuit 1033 is connected between the output end of the first comparator U1 and the first input end of the analog switch K1, and the second end of the RC level holding sub-circuit 1033 is grounded.

[0045] Specifically, the RC level holding sub-circuit 1033 includes a first resistor R4 and a first capacitor C6. The first resistor R4 and the first capacitor C6 are connected in parallel. The first end of the first capacitor C6 is connected between the output end of the first comparator U1 and the first input end of the analog switch K1, and the second end of the first capacitor C6 is grounded.

[0046] In this embodiment, by setting the RC level holding sub-circuit 1033, after the first comparator U1 outputs an analog switch gating signal, the analog switch K1 can be kept closed for a period of time, thereby ensuring the accuracy of the sampling result of the analog-to-digital conversion sub-circuit 1032.

[0047] In some embodiments, the number of single-channel sampling circuits 103 is denoted as n. The preprocessing circuit 102 includes: a first preprocessing sub-circuit to an (n - 1)th preprocessing sub-circuit; the first preprocessing sub-circuit to the (n - 1)th preprocessing sub-circuit are respectively and correspondingly connected to n - 1 single-channel sampling circuits 103, where n is greater than or equal to 2.

[0048] Specifically, the first preprocessing sub-circuit includes a second resistor and two diodes; the first end of the second resistor is connected to a preset power supply. The negative electrode of one diode in the first preprocessing sub-circuit is connected to the clock signal generation module, and the negative electrode of the other diode is connected to the main control chip 101. The second end of the second resistor and the positive electrodes of the two diodes are respectively connected to the analog switch sub-circuit 1031; the (n - 1)th preprocessing sub-circuit includes an nth resistor and n diodes; the first end of the nth resistor is connected to a preset power supply. The negative electrode of one diode in the nth preprocessing sub-circuit is connected to the clock signal generation module, and the negative electrodes of the remaining diodes are connected to the main control chip 101. The second end of the nth resistor and the positive electrodes of the n diodes are respectively connected to the analog switch sub-circuit 1031.

[0049] As an example, the main control chip 101 may include n main control sub-chips. The first main control sub-chip is connected to n single-channel sampling circuits 103, the second main control sub-chip is connected to n - 1 single-channel sampling circuits 103... the nth main control sub-chip is connected to 1 single-channel sampling circuit 103. The first main control sub-chip to the nth main control sub-chip respectively output CNV_BUSY1 to CNV_BUSYn.

[0050] It should be noted that, for the single-channel sampling circuit 103 that is not connected to any pre-processing sub-circuit, its input signal passes through the pre-processing circuit 102, but the input signal is not processed.

[0051] In some embodiments, Figure 3 As shown, the analog-to-digital conversion subcircuit 1032 includes an ADC driver U3 ; an input end of the ADC driver U3 is connected to the analog switch K1 , and a first output end and a second output end of the ADC driver U3 are connected to the main control chip 101 .

[0052] As an example, ADC driver U3 may be a differential output op amp.

[0053] Next, see Figure 4 , explaining the working process of the main control chip 101 of the utility model:

[0054] After starting sampling, first output the clock signal according to the set sampling rate, and set the number m of ADC drivers U3 that need to work, and set the ADC bit number to n=1; then, output the corresponding conversion busy signal Pn (n represents the bit number of ADC, that is, 1 represents the first ADC, and n represents the nth ADC) according to the sampling clock pulse; then wait for the ADC driver U3 to complete the data conversion; if it is not completed, continue to wait; the main control chip 101 reads the sampling data of the current ADCn, and stores it in FIFO (FirstIn First Out) in order, and postpones the ADC bit number n by 1; judge whether n is equal to m at this time. If n=m, it means that a round of ADC conversion has been completed, and n is reset to 1, and the ADC conversion enters the next round; if n≠m, continue the above process until a round of ADC conversion is completed. At this time, the main control chip 101 can obtain a data set consisting of n groups of sampling data. If the sampling rate of each ADC is a, the overall sampling rate of the system is n*a. By increasing the sampling rate, the test signal input bandwidth of the system can be increased.

[0055] Next, taking the multiplexed sampling system 10 including three ADC drivers U3 (ADC1, ADC2, ADC3) as an example, the process of the ADC driver U3 converting the analog signal is described:

[0056] Assuming that the sampling rate of the ADC driver U3 is p, the frequency of the clock signal CLK of the clock signal generating module configured by the system is 3p, see Figure 5When the first clock pulse passes, ADC1 starts conversion. After ADC1 conversion is completed, the main control chip 101 reads the sampling data of ADC1 and stores it in the FIFO. When the second clock pulse passes, ADC2 starts conversion. After ADC2 conversion is completed, the main control chip 101 reads the sampling data of ADC2 and stores it in the FIFO. When the third clock pulse passes, ADC3 starts conversion. After ADC3 conversion is completed, the main control chip 101 reads the sampling data of ADC3 and stores it in the FIFO. When the fourth clock pulse passes, at this time ADC1 is already idle, and then ADC1 starts conversion. After ADC1 conversion is completed, the main control chip 101 reads the sampling data of ADC1 and stores it in the FIFO... and so on. Each ADC can provide p data per second. In this way, the entire multiplexed sampling system 10 can obtain 3p continuous digital signals in each cycle, and the overall sampling rate of the multiplexed sampling system 10 is 3p.

[0057] In some embodiments, the analog-to-digital conversion sub-circuit 1032 further includes a gain module, connected to the ADC driver U3, and configured to perform gain on the output of the ADC driver U3.

[0058] As an example, the gain module can adjust the gain through the three pins A2 / A1 / A0 of the ADC driver U3.

[0059] In this embodiment, through the gain module, the analog signal can be within the effective range before entering the ADC driver U3, thereby improving the sampling accuracy.

[0060] In some embodiments, as Figure 3 shown, the single-channel sampling circuit 103 further includes: a filtering sub-circuit 1034, connected between the ADC driver U3 and the main control chip 101.

[0061] Specifically, the filtering sub-circuit 1034 includes: a second capacitor C7, a third capacitor C8, a fourth capacitor C10, a first voltage-dividing resistor R6, and a second voltage-dividing resistor R11; the second capacitor C7, the third capacitor C8, and the fourth capacitor C10 are connected in series in sequence. The first end of the second capacitor C7 is grounded, the second end of the second capacitor C7 is connected to the first output end of the ADC driver U3 through the first voltage-dividing resistor R6, the first end of the fourth capacitor C10 is connected to the second output end of the ADC driver U3 through the second voltage-dividing resistor R11, and the second end of the fourth capacitor C10 is grounded.

[0062] In this embodiment, the low-pass filter circuit composed of the second capacitor C7, the third capacitor C8, the fourth capacitor C10, the first voltage-dividing resistor R6, and the second voltage-dividing resistor R11 can effectively filter out external stray interference signals and ensure the purity of the digital signal.

[0063] Next, referring to Figure 6 , taking the multiplexed sampling system 10 including three single-channel sampling circuits 103 as an example, the working process of the present invention will be described:

[0064] S1. ADC1, ADC2, and ADC3 are in an idle state. When the first clock signal arrives, the first master sub-chip outputs a low-level CNV_BUSY1, the second master sub-chip outputs a high-level CNV_BUSY2, and the third master sub-chip outputs a high-level CNV_BUSY3.

[0065] S2. The first comparator corresponding to ADC1 outputs an analog switch selection signal, and the second comparator outputs a CNV1 conversion signal; the first and second comparators corresponding to ADC2 and ADC3 do not output signals.

[0066] S3. The analog switch corresponding to ADC1 sends the analog signal to ADC1, and then ADC1 samples and converts the analog signal, and the first master sub-chip reads the digital signal of the current ADC1.

[0067] S4. When the second clock signal arrives, the first master sub-chip outputs a high-level CNV_BUSY1, the second master sub-chip outputs a low-level CNV_BUSY2, and the third master sub-chip outputs a high-level CNV_BUSY3.

[0068] S5. The first comparator corresponding to ADC2 outputs an analog switch selection signal, and the second comparator outputs a CNV2 conversion signal; the first and second comparators corresponding to ADC1 and ADC3 do not output signals.

[0069] S6. The analog switch corresponding to ADC2 sends the analog signal to ADC2, and then ADC2 samples and converts the analog signal, and the second master sub-chip reads the digital signal of the current ADC2.

[0070] S7. When the third clock signal arrives, the first master sub-chip outputs a high-level CNV_BUSY1, the second master sub-chip outputs a high-level CNV_BUSY2, and the third master sub-chip outputs a low-level CNV_BUSY3.

[0071] S8. The first comparator corresponding to ADC3 outputs an analog switch selection signal, and the second comparator outputs a CNV3 conversion signal; the first and second comparators corresponding to ADC1 and ADC2 do not output signals.

[0072] In S9, the analog switch corresponding to ADC3 sends the analog signal to ADC3. Immediately afterwards, ADC3 samples and converts the analog signal, and the third main control sub-chip reads the digital signal of the current ADC3.

[0073] In S10, when the fourth clock signal comes, return to step S1 again, and so on.

[0074] In addition, the present application provides an electronic device 1, as Figure 7 shown. The electronic device 1 includes: the multiplexed sampling system 10 described above.

[0075] The electronic device 1 of the embodiment of the present utility model can reduce the production and manufacturing cost of the electronic device 1 by using the multiplexed sampling system 10.

[0076] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application thereto. Those of ordinary skill in the art can make various changes and modifications therein without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed by the appended claims.

[0077] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0078] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known structures and techniques are not shown in detail so as not to obscure the understanding of this specification.

[0079] Similarly, it should be understood that, in order to streamline the present application and assist in understanding one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. The present application as claimed requires more features than are expressly recited in each claim. More precisely, as reflected by the corresponding claims, the inventive point lies in being able to solve the corresponding technical problems with features less than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, where each claim itself serves as a separate embodiment of the present application.

[0080] Those skilled in the art will appreciate that, except where features are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings), as well as all the units of any device so disclosed. Each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0081] In addition, those skilled in the art will understand that, although some of the embodiments described herein include certain features included in other embodiments rather than other features, the combination of features of different embodiments means that it is within the scope of this application and forms different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0082] It should be noted that the above embodiments illustrate rather than limit this application, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words may be interpreted as names.

[0083] As described above, this is only a specific implementation manner or an illustration of the specific implementation manner of this application, and the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all such changes or substitutions should be covered by the protection scope of this application. The protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A multiplexed sampling system, characterized in that: The sampling system comprises: a main control chip, a preprocessing circuit and a plurality of single-channel sampling circuits, wherein the single-channel sampling circuit comprises an analog switch subcircuit and an analog-to-digital conversion subcircuit; The analog switch subcircuit is connected to the main control chip, the preprocessing circuit, the analog-to-digital conversion subcircuit and the signal input terminal, and is configured to determine the working state according to the control signal output by the main control chip and the preprocessing signal output by the preprocessing circuit, and when the working state is selected, transmit the analog signal output by the signal input terminal to the analog-to-digital conversion subcircuit, wherein the working state includes selected and unselected; The analog-to-digital conversion subcircuit is configured to convert the analog signal into a digital signal; The main control chip is connected to the analog switch subcircuit and the analog-to-digital conversion subcircuit respectively, and is configured to control the working state of the analog switch subcircuit and read the digital signal output by the analog-to-digital conversion subcircuit; The preprocessing circuit is connected to the analog switch subcircuit, the main control chip and the clock signal generating module respectively, and is configured to preprocess the control signal and the clock signal output by the clock signal generating module, and output the preprocessing signal.

2. The multiplexed sampling system according to claim 1, characterized in that: The analog switch subcircuit includes: a first comparator, a second comparator and an analog switch; The first input end of the first comparator and the first input end of the second comparator are connected to the main control chip, the second input end of the first comparator and the second input end of the second comparator are connected to the preprocessing circuit, the output end of the first comparator is connected to the first input end of the analog switch, the second input end of the analog switch is connected to the signal input end, and the output end of the analog switch and the output end of the second comparator are connected to the main control chip.

3. The multiplexed sampling system according to claim 2, characterized in that: The single-channel sampling circuit further includes: an RC level holding subcircuit, a first end of the RC level holding subcircuit is connected between the output end of the first comparator and the first input end of the analog switch, and a second end of the RC level holding subcircuit is grounded.

4. The multiplexed sampling system according to claim 3, characterized in that: The RC level holding subcircuit includes a first resistor and a first capacitor, the first resistor is connected in parallel with the first capacitor, a first end of the first capacitor is connected between the output end of the first comparator and the first input end of the analog switch, and a second end of the first capacitor is grounded.

5. The multiplexed sampling system according to claim 1, characterized in that: The number of the single-channel sampling circuits is n, and the preprocessing circuit includes: a first preprocessing subcircuit to an n-1th preprocessing subcircuit; The first preprocessing subcircuit to the n-1th preprocessing subcircuit are connected to the n-1 single-channel sampling circuits in a one-to-one correspondence, where n is greater than or equal to 2.

6. The multiplexed sampling system according to claim 5, characterized in that: The first pre-processing sub-circuit includes a second resistor and two diodes; A first end of the second resistor is connected to a preset power supply, a cathode end of a diode in the first preprocessing subcircuit is connected to the clock signal generating module, a cathode end of another diode is connected to the main control chip, and a second end of the second resistor and anode ends of two diodes are respectively connected to the analog switch subcircuit; The n-1th preprocessing subcircuit comprises an nth resistor and n diodes; The first end of the nth resistor is connected to a preset power supply, the cathode end of a diode in the nth preprocessing subcircuit is connected to the clock signal generating module, the cathode ends of the remaining diodes are connected to the main control chip, and the second end of the nth resistor and the positive ends of the n diodes are respectively connected to the analog switch subcircuit.

7. The multiplexed sampling system according to claim 2, characterized in that: The analog-to-digital conversion subcircuit includes an ADC driver; The input end of the ADC driver is connected to the analog switch, and the first output end and the second output end of the ADC driver are connected to the main control chip.

8. The multiplexed sampling system according to claim 7, characterized in that: The analog-to-digital conversion subcircuit also includes a gain module connected to the ADC driver and configured to gain the output of the ADC driver.

9. The multiplexed sampling system according to claim 7, characterized in that: The single-channel sampling circuit further includes: a filtering subcircuit connected between the ADC driver and the main control chip.

10. The multiplexed sampling system according to claim 9, characterized in that: The filtering subcircuit comprises: a second capacitor, a third capacitor, a fourth capacitor, a first voltage-dividing resistor and a second voltage-dividing resistor; The second capacitor, the third capacitor and the fourth capacitor are connected in series in sequence, the first end of the second capacitor is grounded, the second end of the second capacitor is connected to the first output end of the ADC driver through the first voltage-dividing resistor, the first end of the fourth capacitor is connected to the second output end of the ADC driver through the second voltage-dividing resistor, and the second end of the fourth capacitor is grounded.

11. The multiplexed sampling system according to claim 1, characterized in that: There are multiple main control chips, and the multiple main control chips are connected to the multiple single-channel sampling circuits in a one-to-one correspondence.

12. An electronic device, characterized in that: The method comprises the multiplexed sampling system as described in any one of claims 1 to 11.

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