Semiconductor structure with alignment mark
By adding virtual graphics to the outer and inner marking areas of the dielectric layer of the semiconductor structure, the problem of insufficient wear resistance of the alignment mark is solved, and the alignment accuracy and yield of the wafer is improved.
Patent Information
- Application Number
- CN202421574738.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-07-04
AI Technical Summary
In the existing semiconductor process, the abrasion resistance of the alignment marks is poor, resulting in serious damage during chemical mechanical grinding, affecting the alignment and yield of the wafer.
A semiconductor structure is designed in which the dielectric layer contains external and internal marking areas and virtual graphics are added to these areas to increase the pattern density and thus enhance the wear resistance of the alignment marks.
By adding virtual graphics, the wear resistance of the alignment marks is improved, the wear of the alignment marks is reduced in the grinding process, and the alignment accuracy and yield of the wafer is improved.
Smart Images
Figure CN223038955U_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor structure with alignment marks. Background Art
[0002] Alignment marks (AIM Marks) play a very important role in the semiconductor manufacturing process. During the wafer manufacturing process, in order to correctly transfer the patterns on the photomask (also known as the reticle) to the wafer, the key step lies in the alignment of the photomask and the wafer. However, the abrasion resistance of the alignment marks is poor. After chemical mechanical polishing, if the marks are severely damaged, it will directly affect the alignment of the wafer, resulting in a decrease in the wafer yield. Summary of the Utility Model
[0003] The purpose of this application is to provide a semiconductor structure with alignment marks, aiming to reduce the wear of the alignment marks and improve the yield.
[0004] This application provides a semiconductor device with alignment marks, including:
[0005] A substrate;
[0006] An alignment mark layer located on the substrate, and including a dielectric layer and a first alignment mark and a dummy pattern located in the dielectric layer. The first alignment mark includes a plurality of first rectangular mark groups, and the plurality of first rectangular mark groups are configured in a rectangular area, and the first rectangular mark groups are adjacent to the right-angle parts of the rectangular area; the dielectric layer includes an external mark area and an internal mark area, the external mark area is located outside the rectangular area, and the internal mark area is located inside the rectangular area;
[0007] Wherein, the dummy pattern is disposed in at least one of the external mark area and the internal mark area.
[0008] In some embodiments, the dummy pattern is spaced apart from the first alignment mark.
[0009] In some embodiments, the first rectangular mark group includes a plurality of first mark units arranged at intervals;
[0010] The dummy pattern includes dummy units, and the density of the dummy units in the dummy pattern is greater than or equal to the density of the first mark units in the first rectangular mark group.
[0011] In some embodiments, the dummy units fill at least one of the external mark area and the internal mark area.
[0012] In some embodiments, a plurality of the virtual cells are disposed in the internal marking region and form a plurality of virtual marking groups. The virtual marking groups are in one-to-one correspondence with and adjacent to the first rectangular marking groups, and the extending direction of the virtual cells in the virtual marking group is the same as that of the corresponding first marking unit.
[0013] In some embodiments, a plurality of the virtual cells are disposed in the external marking region. The virtual cells extend along a first direction, and the first direction is parallel to the substrate.
[0014] In some embodiments, the distance between adjacent virtual cells is less than the distance between adjacent first marking units; or,
[0015] the width of the virtual cell is greater than the width of the first marking unit.
[0016] In some embodiments, a plurality of the virtual cells are disposed in the internal marking region and a plurality of the virtual cells are also disposed in the external marking region;
[0017] the width of the virtual cell is the same as the width of the first marking unit, and the distance between adjacent virtual cells is the same as the distance between adjacent first marking units.
[0018] In some embodiments, the semiconductor structure further includes:
[0019] an upper storage stack located on a side of the alignment marking layer away from the substrate. The upper storage stack covers the virtual pattern and has an opening exposing the first alignment mark;
[0020] a mask layer located on a side of the upper storage stack away from the substrate and filling the opening;
[0021] a second alignment mark located on a side of the mask layer away from the substrate and corresponding to the internal marking region.
[0022] In some embodiments, the semiconductor structure includes an array region and a scribe line located between adjacent array regions. The first alignment mark and the virtual pattern are located in the scribe line. The semiconductor structure further includes:
[0023] lower storage cells located in the dielectric layer and in the array region;
[0024] word lines located on a side of the lower storage cells away from the substrate;
[0025] wherein the word lines are disposed on the same layer as the first alignment mark and the virtual pattern and are exposed on a surface of the dielectric layer away from the substrate.
[0026] The present application provides a semiconductor structure with alignment marks. The semiconductor structure includes a substrate and an alignment mark layer located on the substrate. The alignment mark layer includes a dielectric layer and a first alignment mark and dummy patterns located in the dielectric layer. The first alignment mark includes a plurality of first rectangular mark groups. The plurality of first rectangular mark groups are configured in a rectangular area, and the first rectangular mark groups are adjacent to the right-angle portions of the rectangular area. The dielectric layer includes an external mark area and an internal mark area. The external mark area is located outside the rectangular area, and the internal mark area is located inside the rectangular area. Among them, the dummy patterns are disposed in at least one of the external mark area and the internal mark area. By adding dummy patterns in the external mark area and / or the internal mark area, the pattern density of the external and / or internal areas of the first alignment mark is increased, the anti-polishing ability is improved, the first alignment mark is protected, and the wear of the first alignment mark in the polishing process is reduced, thereby improving the yield. Description of the Drawings
[0027] The technical solutions and other beneficial effects of the present application will become obvious by describing the specific embodiments of the present application in detail in conjunction with the drawings.
[0028] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application;
[0029] Figure 2 is provided by some embodiments of the present application Figure 1 of the semiconductor structure in the top view structure diagram;
[0030] Figure 3 is a schematic top view structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application;
[0031] Figures 4A - 4C is a schematic top view structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application;
[0032] Figures 5A - 5B is a schematic top view structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application;
[0033] Figure 6 is a schematic cross-sectional structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application;
[0034] Figure 7 is provided by some embodiments of the present application Figure 6 of the semiconductor structure in the top view structure diagram;
[0035] Figure 8It is a schematic cross-sectional structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application. Detailed implementation manners
[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0037] It should be understood that although terms such as first and second can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component without departing from the scope of the present application.
[0038] It should be understood that when a component is said to be "on" another component or "connected" to another component, it can be directly on the other component or connected to the other component, or there can also be inserted components. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0039] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically, and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above, and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers, contact layers, and one or more dielectric layers.
[0040] It should be noted that the drawings provided in the embodiments of the present application only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the drawings and are not drawn according to the number, shape, and size of the components in actual implementation, the type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0041] The lithography process is a key step in semiconductor integrated circuit manufacturing. The lithography process is widely used in the manufacturing processes of various semiconductor devices such as field effect devices, semiconductor special devices, composite transistors, diodes, and laser devices. The quality of the alignment marks will directly affect the alignment of the wafers. The present utility model provides a semiconductor structure with alignment marks, which can reduce the wear of the alignment marks, thereby improving the alignment effect between layers on the wafer, enhancing the yield rate, and can be applied to the manufacturing processes of various semiconductor devices.
[0042] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic cross-sectional structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application, Figure 2 and Figure 1 is a schematic top view structure diagram of the semiconductor structure in
[0043] The semiconductor structure 100 includes a substrate 10 and an alignment mark layer 20 located on the substrate 10. The alignment mark layer 20 includes a dielectric layer 21 and a first alignment mark 22 and dummy patterns 23 located in the dielectric layer 21. The first alignment mark 22 includes a plurality of first rectangular mark groups 220. The plurality of first rectangular mark groups 220 are arranged in a rectangular region R, and the first rectangular mark groups 220 are adjacent to the right-angle part R1 of the rectangular region R. The dielectric layer 21 includes an external mark region 211 and an internal mark region 212. The external mark region 211 is located outside the rectangular region R, and the internal mark region 212 is located inside the rectangular region R. Among them, the dummy patterns 23 are disposed in at least one of the external mark region 211 and the internal mark region 212. By adding dummy patterns 23 in the external mark region 211 and / or the internal mark region 212, the first alignment mark 22 can be protected, and the wear of the first alignment mark 22 in the grinding process can be reduced, thereby improving the yield rate.
[0044] That is to say, the virtual pattern 23 can be disposed only in the inner marking region 212, or only in the outer marking region 211, or in both the inner marking region 212 and the outer marking region 211. Regardless of which region the virtual pattern 23 is disposed in, as long as it is adjacent to the first alignment mark 22, it can protect the first alignment mark 22 and reduce its wear. Generally, the edge position of the first alignment mark 22 is prone to wear during the grinding process. When the virtual pattern 23 is disposed only in the inner marking region 212, it mainly protects the inner edge of the first alignment mark 22. The "inner edge" refers to the edge of the first rectangular mark group 220 that does not adjoin the boundary of the rectangular region R. When the virtual pattern 23 is disposed only in the outer marking region 211, it mainly protects the outer edge of the first alignment mark 22. The "outer edge" refers to the edge of the first rectangular mark group 220 that adjoins the boundary of the rectangular region R (i.e., the two edges adjacent to the right-angle portion R1). When the virtual pattern 23 is disposed in both the inner marking region 212 and the outer marking region 211, it can provide good protection for both the inner edge and the outer edge of the first alignment mark 22.
[0045] In some embodiments, as Figure 2 shown, the virtual pattern 23 is disposed in the inner marking region 212.
[0046] The substrate 10 can be selected as a silicon (Si) substrate, for example, to fabricate MOS transistors. In another embodiment, the substrate 10 can also be a gallium nitride (GaN) substrate to fabricate light-emitting diodes (LEDs) and semiconductor lasers. In other embodiments, the substrate 10 can also be a silicon carbide (SiC) substrate 10 to fabricate power devices such as Schottky diodes and insulated gate bipolar transistors (IGBTs). The dielectric layer 21 can include an insulating layer, such as an oxide.
[0047] In some embodiments, the semiconductor structure 100 may further include a peripheral circuit layer ( Figure 1 (not shown), which is located between the substrate 10 and the dielectric layer 21.
[0048] In some embodiments, the first rectangular mark group 220 includes a plurality of first mark units M1 arranged at intervals, and the plurality of first mark units M1 in one first rectangular mark group 220 are arranged in parallel with each other, and the distance between adjacent two first mark units M1 is equal.
[0049] In some embodiments, the first marking units M1 in one of the first rectangular marking groups 220 extend along a first direction Y, and the first marking units M1 in the other first rectangular marking group 220 extend along a second direction X. The first direction Y and the second direction X are parallel to and perpendicular to each other with respect to the substrate 10. That is to say, in some of the first rectangular marking groups 220, the first marking units M1 extend along the first direction Y, and in some of the first rectangular marking groups 220, the first marking units M1 extend along the second direction X.
[0050] Specifically, the extending directions of the first marking units M1 in two adjacent first rectangular marking groups 220 are different. "Two adjacent first rectangular marking groups 220" refers to two first rectangular marking groups 220 located at adjacent right-angle portions R1 of the rectangular region R.
[0051] In some embodiments, the virtual pattern 23 may be spaced apart from the first alignment mark 22. The virtual pattern 23 includes a plurality of virtual units M2 that are spaced apart. It should be noted that Figure 2 Only the region where the virtual pattern 23 is shown. Actually, the virtual pattern 23 includes Figure 1 The plurality of virtual units M2 that are spaced apart as shown. When the density of the virtual units M2 is very high, the virtual pattern 23 appears as a single piece to the naked eye.
[0052] In some embodiments, the density of the virtual units M2 in the virtual pattern 23 is greater than or equal to the density of the first marking units M1 in the first rectangular marking group 220, so that the virtual pattern 23 can better protect the first marking units M1.
[0053] Among them, the "density" can be represented by the ratio of the sum of the areas of the respective virtual units M2 to the occupied area of the virtual pattern 23. Among them, the occupied area of the virtual pattern 23 can be the area of the rectangular region R minus the areas of the four first rectangular marking groups 220.
[0054] In some embodiments, the virtual units M2 fill at least one of the external marking region 211 and the internal marking region 212.
[0055] In some embodiments, the extending directions of the plurality of virtual units M2 may be the same or different. The shape, size, distance, and area of the virtual pattern 23 can all be designed according to the actual process, and the present application does not limit this.
[0056] In some embodiments, the extending directions of the plurality of virtual units M2 are the same. For example, the plurality of virtual units M2 may all be arranged along the first direction Y, or all be arranged along the second direction X. Moreover, the distance between adjacent virtual units M2 may be less than the distance between adjacent first marking units M1 in the first rectangular marking group 220, such that the density of the virtual units M2 is greater than the density of the first marking units M1 in the first rectangular marking group 220.
[0057] Please refer to Figure 3 , Figure 3 FIG. is a top view structural schematic diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application. The semiconductor structure 200 shows a specific top view structure of a virtual pattern 23, which is located in the internal marking area 212, and the extending directions of the plurality of virtual units M2 are different.
[0058] In some embodiments, the plurality of virtual units M2 form a plurality of virtual marking groups 230. The virtual marking groups 230 are arranged adjacent to and in one-to-one correspondence with the first rectangular marking group 220, and the extending direction of the virtual units M2 in the virtual marking group 230 is the same as the extending direction of the corresponding first marking unit M1.
[0059] Specifically, for example, as Figure 3 shown, the virtual units M2 in some virtual marking groups 230 are arranged along the first direction Y, and the virtual units M2 in some other virtual marking groups 230 are arranged along the second direction X.
[0060] In some embodiments, the density of the virtual units M2 is greater than the density of the first marking units M1 in the first rectangular marking group 220.
[0061] Specifically, the top view pattern of the virtual unit M2 is a long strip, and the distance between adjacent virtual units M2 in the virtual marking group 230 is less than the distance between adjacent first marking units M1 in the first rectangular marking group 220 (under the same other conditions), so that the density of the virtual units M2 is greater than the density of the first marking units M1, and the protection effect on the first marking units M1 can be enhanced.
[0062] In some embodiments, the width of the virtual unit M2 may be set to be greater than the width of the first marking unit M1, where the "width" is the dimension of the long-strip virtual unit M2 along the width direction and the dimension of the long-strip first marking unit M1 along the width direction. Under the condition that other conditions remain unchanged, increasing the width of the virtual unit M2 can increase the area occupied by the virtual unit M2, thereby increasing the density of the virtual unit M2.
[0063] Please refer to Figures 4A - 4C , Figures 4A - 4CIt is a top - view structural schematic diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application. For the convenience of understanding and brief description, the same structures as those in the above embodiments continue to use the same reference numerals, and the same structures will not be described in detail. Only the different structures in this embodiment will be described in detail.
[0064] Figure 4A The difference between the semiconductor structure 300 in Figure 3 and the semiconductor structure 200 in Figure 3 is that the dummy pattern 23 is not only located in the internal marking area 212 but also in the external marking area 211. That is, a plurality of dummy cells M2a are disposed in the internal marking area 212, and a plurality of dummy cells M2b are disposed in the external marking area 211. Among them, the dummy cells M2a in the internal marking area 212 can have the
[0065] same shape and arrangement as the dummy cells M2 in
[0066] Figure 4B The difference between the semiconductor structure 400 in Figure 4A and the semiconductor structure 300 in
[0067] Figure 4C is that the distance between adjacent dummy cells M2b in the external marking area 211 is increased to enhance the protection of the first marking unit M1. Figure 4B The difference between the semiconductor structure 500 in
[0068] and the semiconductor structure 400 in Figures 4A - 4C is that the distance between adjacent dummy cells M2a in the internal marking area 212 is equal to the distance between adjacent first marking units M1 in the first rectangular marking group 220. Therefore, the density of the dummy cells M2a in the internal marking area 212 is equal to the density of the first marking units M1.
[0069] Specifically, the width of the dummy cells M2b and the width of the dummy cells M2a can both be equal to the width of the first marking unit M1, and the distance between adjacent dummy cells M2b and the distance between adjacent dummy cells M2a are both the same as the distance between adjacent first marking units M1.
[0070] Please refer to Figures 5A - 5B , Figures 5A - 5B which is a top - view structural schematic diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application. For the sake of easy understanding and brief description, the same structures in this embodiment as those in the above - mentioned embodiments continue to use the same reference numerals, and the same structures will not be described in detail. Only the different structures in this embodiment will be described in detail.
[0071] Figure 5A The difference between the semiconductor structure 600 in Figure 4A and the semiconductor structure 300 in Figure 5B is that the dummy pattern 23 is only located in the external mark region 211, that is, the dummy cell M2’ is only located in the external mark region 211. Figure 5A The difference between the semiconductor structure 700 in
[0072] Please refer to Figure 6 and Figure 7 , Figure 6 which is a cross - sectional structural schematic diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application, Figure 7 and Figure 6 is a top - view structural schematic diagram of the semiconductor structure in
[0073] provided by some embodiments of the present application. For the sake of easy understanding and brief description, the same structures in this embodiment as those in the above - mentioned embodiments continue to use the same reference numerals, and the same structures will not be described in detail. Only the different structures in this embodiment will be described in detail. Figure 1 The difference between the semiconductor structure 800 and the semiconductor structure 100 in
[0074] is that the semiconductor structure 800 further includes an upper storage stack 30, a mask layer 40, and a second alignment mark 50. The second alignment mark 50 and the mask layer 40 are used to etch the upper storage stack 30 to form the upper storage unit.
[0075] In some embodiments, the mask layer 40 is a light-transmissive material, and the upper storage stack 30 is a light-impermeable material. Therefore, the virtual pattern 23 will not affect the second alignment mark 50. The combination of the second alignment mark 50 of the layer and the first alignment mark 22 of the lower layer can achieve alignment etching of the upper storage stack 30.
[0076] In some embodiments, the material of the second alignment mark 50 can be photoresist.
[0077] In some embodiments, the second alignment mark 50 may include a second rectangular mark group 510, and the second rectangular mark group 510 includes a plurality of second mark units M3 arranged at intervals. The second mark units M3 in one second rectangular mark group 510 extend along the first direction Y, and the second mark units M3 in the other second rectangular mark group 510 extend along the second direction X.
[0078] In some embodiments, the semiconductor structure 100 includes an array region and a scribe line located between adjacent array regions. The first alignment mark 22 and the virtual pattern 23 are both located in the scribe line. The scribe line is used for subsequent cutting of the semiconductor structure to form a plurality of chips.
[0079] Please refer to Figure 8 , Figure 8 which is a schematic cross-sectional structure diagram of a semiconductor structure with alignment marks provided by some embodiments of the present application.
[0080] The semiconductor structure 900 includes adjacent scribe lines S1 and array regions S2. The first alignment mark 22 (including the first mark unit M1) and the virtual pattern 23 (including the virtual unit M2) are both located in the scribe line S1, and the virtual pattern 23 is located in the internal mark region 212. The upper storage stack 30a may include an adhesion layer, a first electrode layer, a gate layer, a second electrode layer, a phase change layer, and a third electrode layer stacked in sequence, and the film layers of the storage stack can be set according to the type of memory.
[0081] In some embodiments, the semiconductor structure 900 further includes a lower storage unit 60 and a word line WL. The lower storage unit 60 is located in the dielectric layer 21 and in the array region S2, and the word line WL is located on the side of the lower storage unit 60 away from the substrate 10. Among them, the word line WL is arranged on the same layer as the first alignment mark 22 and the virtual pattern 23, and is exposed on the surface of the dielectric layer 21 away from the substrate 10.
[0082] That is to say, the word line WL is formed together with the first alignment mark 22. Specifically, after forming the lower-layer memory cell 60, tungsten is deposited by a deposition process, and then the lower-layer word line WL and the first alignment mark 22 are etched from the tungsten. The dummy pattern 23 can also be formed together with the word line WL. After forming the word line WL, a chemical mechanical polishing process is required. At this time, the dummy pattern 23 can protect the first alignment mark 22 and reduce the wear of the first alignment mark 22. The first alignment mark 22 and the second alignment mark 50 are used for photolithographic alignment between the upper-layer memory stack 30a and the lower-layer memory cell 60, so that the upper-layer memory cell (which can be called the current-layer memory cell) aligned with the lower-layer memory cell 60 (which can be called the previous-layer memory cell) is formed by an etching process. Therefore, reducing the wear of the first alignment mark 22 can improve the photolithographic alignment accuracy between the current-layer memory cell and the previous-layer memory cell, and further improve the alignment accuracy of the subsequent etching process.
[0083] The semiconductor structure provided by the embodiment of the present application includes a substrate 10 and an alignment mark layer 20 located on the substrate 10. The alignment mark layer 20 includes a dielectric layer 21 and a first alignment mark 22 and a dummy pattern 23 located in the dielectric layer 21. The first alignment mark 22 includes a plurality of first rectangular mark groups 220. The plurality of first rectangular mark groups 220 are arranged in a rectangular area R, and the first rectangular mark groups 220 are adjacent to the right-angle part R1 of the rectangular area R. The dielectric layer 21 includes an external mark area 211 and an internal mark area 212. The external mark area 211 is located outside the rectangular area R, and the internal mark area 212 is located inside the rectangular area R. Among them, the dummy pattern 23 is disposed in at least one of the external mark area 211 and the internal mark area 212. By adding the dummy pattern 23 in the external mark area 211 and / or the internal mark area 212, the first alignment mark 22 can be protected, the wear of the first alignment mark 22 in the polishing process can be reduced, and further the alignment accuracy of the subsequent photolithographic process and etching process can be improved, and the yield can be improved.
[0084] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor structure having an alignment mark, characterized in that: include: substrate; an alignment mark layer, located on the substrate, and comprising a dielectric layer and a first alignment mark and a dummy pattern located in the dielectric layer, wherein the first alignment mark comprises a plurality of first rectangular mark groups, wherein the plurality of first rectangular mark groups are arranged in a rectangular area, and the first rectangular mark groups are adjacent to the right angle portion of the rectangular area; the dielectric layer comprises an external mark area and an internal mark area, wherein the external mark area is located outside the rectangular area, and the internal mark area is located inside the rectangular area; Wherein, the virtual graphic is set in at least one of the external marking area and the internal marking area.
2. The semiconductor structure with alignment mark according to claim 1, characterized in that: The dummy pattern is spaced apart from the first alignment mark.
3. The semiconductor structure with alignment mark according to claim 1, characterized in that: The first rectangular marking group includes a plurality of first marking units arranged at intervals; The virtual pattern includes virtual units, and a density of the virtual units in the virtual pattern is greater than or equal to a density of the first marking units in the first rectangular marking group.
4. The semiconductor structure with alignment mark according to claim 3, characterized in that: The virtual cell fills up at least one of the outer marking area and the inner marking area.
5. The semiconductor structure with alignment mark according to claim 3, characterized in that: The plurality of virtual units are arranged in the inner marking area and constitute a plurality of virtual marking groups, the virtual marking groups correspond to the first rectangular marking groups one by one and are arranged adjacent to each other, and the extension direction of the virtual units in the virtual marking groups is the same as the extension direction of the corresponding first marking units.
6. The semiconductor structure with alignment mark according to claim 3, characterized in that: A plurality of the dummy units are disposed in the external marking region, and the dummy units extend along a first direction, and the first direction is parallel to the substrate.
7. The semiconductor structure with alignment marks according to any one of claims 3 to 6, characterized in that: The distance between adjacent virtual units is smaller than the distance between adjacent first marking units; or, The width of the dummy unit is greater than the width of the first marking unit.
8. The semiconductor structure with alignment mark according to claim 3, characterized in that: A plurality of the virtual units are disposed in the inner marking area, and a plurality of the virtual units are disposed in the outer marking area; The width of the virtual unit is the same as the width of the first marking unit, and the distance between adjacent virtual units is the same as the distance between adjacent first marking units.
9. The semiconductor structure with alignment mark according to claim 1, characterized in that: The semiconductor structure further comprises: an upper storage stack, located on a side of the alignment mark layer away from the substrate, the upper storage stack covering the dummy pattern and having an opening exposing the first alignment mark; A mask layer, located on a side of the upper storage stack away from the substrate and filling the opening; The second alignment mark is located on a side of the mask layer away from the substrate and corresponds to the inner mark area.
10. The semiconductor structure with alignment mark according to claim 1, characterized in that: The semiconductor structure includes an array region and a cutting path between adjacent array regions, the first alignment mark and the dummy pattern are located in the cutting path, and the semiconductor structure further includes: A lower storage unit is located in the dielectric layer and in the array area; A word line, located at a side of the lower memory cell away from the substrate; The word line is arranged in the same layer as the first alignment mark and the dummy pattern, and is exposed on a surface of the dielectric layer away from the substrate.