Power supply turn-off and residual electricity elimination circuit

Abstract

The embodiment of the utility model discloses a power supply turn-off and residual electricity elimination circuit, which comprises a power supply voltage detection unit, a power supply switch unit and a power supply discharge unit, and is characterized in that the power supply voltage detection unit is used for detecting the voltage of a power supply and outputting a driving signal when the voltage is smaller than a set threshold value; the power switch unit is used for turning off a power supply according to the driving signal and turning on the power discharge unit; and the power supply discharging unit is used for discharging residual current when the power supply switch unit is in an on state. By implementing the circuit provided by the embodiment of the utility model, the problem that equipment crashes due to the fact that the main control chip is powered on again when the power supply voltage is not completely discharged in an ultra-low power consumption mode can be solved.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and particularly to a power-off and residual power elimination circuit. Background Art

[0002] For ultra-low power consumption products, the key lies in minimizing the power consumption in the sleep standby state to extend the standby time of the battery. However, in actual use, the product may need to replace the general battery regularly to ensure continuous use. Usually, an ultra-low power consumption microcontroller is used as the main controller, and its current in the sleep state is only a few microamperes. However, when replacing the battery, due to the existence of energy storage components, the self-discharge time of the main board is long.

[0003] If the main control chip is powered on again without being completely depleted, due to possible defects in some chips, it cannot run normally to the application layer during the startup phase, resulting in the system falling into a loop of crashing.

[0004] Therefore, it is necessary to design a new circuit to solve the problem of the device crashing when the main control chip is powered on again when the supply voltage has not been completely discharged in the ultra-low power consumption mode. Summary of the Utility Model

[0005] The technical problem to be solved by the utility model is to provide a power-off and residual power elimination circuit.

[0006] To solve the above technical problem, the purpose of the utility model is achieved through the following technical solutions: providing a power-off and residual power elimination circuit, including: a power supply voltage detection unit, a power switch unit, and a power discharge unit. The power supply voltage detection unit is used to detect the voltage of the power supply and output a drive signal when the voltage is less than a set threshold. The power switch unit is used to disconnect the path between the power supply and the backend power supply according to the drive signal and turn on the power discharge unit. The power discharge unit is used to discharge the current of the residual backend power supply when the power switch unit is in the on state.

[0007] Its further technical solution is: the power supply voltage detection unit includes a voltage detection chip U101, and the voltage detection chip U101 is connected to the power switch unit.

[0008] One end of the voltage detection chip U101 connected to the power switch unit is connected with a pull-up resistor R183; one end of the voltage detection chip U101 is connected with a capacitor C118 grounded at one end; the capacitor C118 is connected in parallel with a resistor R190 grounded at one end.

[0009] Its further technical solution is as follows: The power switch unit includes MOS transistor Q106, MOS transistor Q18, and MOS transistor Q20. The gate of MOS transistor Q106 is connected to the voltage detection chip U101; the drain of MOS transistor Q106 is connected to the gate of MOS transistor Q18; the drain of MOS transistor Q18 is connected to the drain of MOS transistor Q20; the source of MOS transistor Q20 is connected to the backend power supply; the source of MOS transistor Q18 is connected to the power supply.

[0010] Its further technical solution is as follows: The drain of MOS transistor Q106 is connected to the gate of MOS transistor Q18 through resistor R179; the source of MOS transistor Q18 is connected to resistor R179 through resistor R178.

[0011] Its further technical solution is as follows: The backend power supply is connected to the power discharge unit; the discharge unit is connected to the drain of MOS transistor Q106.

[0012] Its further technical solution is as follows: The power discharge unit includes MOS transistor Q105 and discharge resistor R0303; the gate of MOS transistor Q105 is connected to the drain of MOS transistor Q106; the drain of MOS transistor Q105 is connected to the backend power supply through the discharge resistor R0303.

[0013] Its further technical solution is as follows: The drain of MOS transistor Q106 is sequentially connected to the gate of MOS transistor Q105 through resistor R191 and resistor R181.

[0014] Its further technical solution is as follows: The source of MOS transistor Q105 is grounded.

[0015] Its further technical solution is as follows: A capacitor C117 with one end grounded is connected to the gate of MOS transistor Q105.

[0016] The beneficial effects of the present utility model compared with the prior art are as follows: By setting a power voltage detection unit, a power switch unit, and a power discharge unit, when equipment battery replacement is required, the power supply is manually disconnected. During this process, the power detection unit will detect the change in the power supply voltage and generate a drive signal; once the drive signal is received, the power switch unit will quickly cut off the connection between the power supply and the backend power supply and turn on the power discharge unit; at the same time, the power discharge unit starts to discharge the residual current in the backend power supply to solve the problem of the equipment crashing when the main control chip is powered on again when the power supply voltage has not been fully discharged in the ultra-low power consumption mode.

[0017] The following further describes the present utility model in conjunction with the accompanying drawings and specific embodiments. Description of the Drawings

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic block diagram of a power-off and residual power elimination circuit provided by an embodiment of the present invention;

[0020] Figure 2 It is a specific circuit schematic diagram of a power supply voltage detection unit provided by an embodiment of the present invention;

[0021] Figure 3 It is a specific circuit schematic diagram of a power switch unit and a power discharge unit provided by an embodiment of the present invention;

[0022] Explanation of the labels in the figure:

[0023] 10. Power supply voltage detection unit; 20. Power switch unit; 30. Power discharge unit; 40. Back-end power supply; 50. Power supply. Specific embodiments

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0025] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0026] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0027] It should be further understood that the term "and / or" used in the specification and appended claims of the present utility model refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] Please refer to Figure 1 , Figure 1 FIG. is a schematic block diagram of a power-off and residual charge elimination circuit provided for an embodiment of the present utility model, which can be applied to devices that need to discharge residual current, enabling the device to turn off the working power supply in a timely manner below the effective working voltage and quickly discharging the residual charge of the backend power supply 40 to ensure that the system reaches a stable working state. At the same time, in the normal working state, the leakage current of the entire circuit is small, facilitating the extended use of ultra-low power consumption products.

[0029] Please refer to Figure 1 , a power-off and residual charge elimination circuit, comprising: a power voltage detection unit 10, a power switch unit 20, and a power discharge unit 30. The power voltage detection unit 10 is configured to detect the voltage of the power supply 50 and output a driving signal when the voltage is less than a set threshold; the power switch unit 20 is configured to disconnect the path between the power supply 50 and the backend power supply 40 according to the driving signal and turn on the power discharge unit 30; the power discharge unit 30 is configured to discharge the residual current of the backend power supply 40 when the power switch unit 20 is in an open state.

[0030] In this embodiment, one end of the power supply 50 is connected to a capacitor C123 with one end grounded, and a capacitor C115 and C116 are connected in parallel across both ends of the capacitor C123.

[0031] In this embodiment, by detecting the change in the power supply voltage during the process of manual power-off as a trigger point, the normal operation of the device after power supply replacement is achieved through the rapid disconnection of the front-end power supply, i.e., the power supply 50, and the rapid discharge of the backend power supply 40, solving the problem of the device freezing BUG that occurred when the power supply voltage was not fully discharged and the device was re-powered on in the ultra-low power consumption mode of some previous MCUs.

[0032] Specifically, the power voltage detection unit 10 is responsible for monitoring the voltage of the power supply 50. When the voltage is lower than the set threshold, it generates a driving signal; once receiving the driving signal from the power voltage detection unit 10, the power switch unit 20 turns on the power discharge unit 30, thereby cutting off the connection between the power supply 50 and the backend power supply 40; when the power switch unit 20 is closed, the power discharge unit 30 starts to discharge the residual current in the backend power supply 40. This ensures that the residual current in the backend power supply 40 has been fully discharged before the device is re-powered on, avoiding the problem of the device freezing BUG when re-powered on.

[0033] The above circuit can effectively solve the device freeze BUG in the ultra-low power consumption mode of the MCU. By quickly cutting off the power supply 50 and discharging the residual current in the backend power supply 40, it ensures that the device can operate normally when powered on again, improving the stability and reliability of the system.

[0034] In one embodiment, please refer to Figure 2 , the above power supply voltage detection unit 10 includes a voltage detection chip U101, and the voltage detection chip U101 is connected to the power switch unit 20.

[0035] In one embodiment, please refer to Figure 2 , one end of the above voltage detection chip U101 connected to the power switch unit 20 is connected with a pull-up resistor R183; one end of the voltage detection chip U101 is connected with a capacitor C118 grounded at one end; the capacitor C118 is connected in parallel with a resistor R190 grounded at one end.

[0036] In this embodiment, the model of the above voltage detection chip U101 is but not limited to SGM809. Among them, one end of the above voltage detection chip U101 connected to the power supply 50 is connected with a capacitor C121 grounded at one end.

[0037] In this embodiment, the above power supply voltage detection unit 10 is compatible with two defined packages, including that PIN1 of the voltage detection chip U101 is GND, and PIN2 is the signal output pin (corresponding to resistor R190, resistor R185 is 0Ω, capacitor C118 is 100nF, resistor R186 and resistor R184 are empty pasted NC with capacitor C120); PIN2 of the voltage detection chip U101 is GND, and PIN1 is the signal output pin (corresponding to resistor R186, resistor R184 is 0Ω, capacitor C120 is 100nF, resistor R190, resistor R185 are empty pasted NC with capacitor C118). The voltage detection chip U101 is a high-precision and low-power voltage detection chip. The typical value of the voltage detection value selected for this chip is 2V, the falling voltage threshold is 1.96V, and the rising voltage threshold is 2.04V. The voltage value corresponding to the specific selected chip can be selected according to the actual circuit requirements. The power supply 50 of this chip is provided by the external battery VBAT, which is used to detect the change of the VBAT voltage value and output a feedback signal. When the voltage of the external power supply 50 VBAT is lower than its falling trigger threshold voltage of 1.96V, the PWR_EN signal corresponding to the RESET pin outputs a low level for the subsequent power control circuit to use. The pull-up resistor R183 is an external pull-up compatible resistor. When the voltage of the external power supply 50 VBAT is higher than its rising trigger threshold voltage of 2.04V, the PWR_EN signal corresponding to the RESET pin remains at a high level state.

[0038] The voltage detection chip U101 has high-precision voltage detection capabilities and can accurately monitor the voltage changes of the external power supply 50VBAT. This ensures the system's rapid response to voltage changes in the power supply 50, improving the system's stability and reliability; the voltage detection chip U101 itself has low-power consumption characteristics, which helps reduce the power consumption of the entire circuit, extend the battery life of the device, and improve the sustainable usage time of the device; the falling and rising voltage thresholds of the voltage detection chip U101 can be adjusted and configured according to actual application requirements. This means that users can set the trigger conditions for power control according to specific situations to adapt to different working environments and power supply conditions; when the voltage of the external power supply 50VBAT is lower than the threshold voltage for falling trigger, the PWR_EN signal corresponding to the RESET pin will output a low level, providing a stable feedback signal so that the subsequent power control circuit can respond in a timely manner and take necessary measures to protect the device from the impact of too low voltage of the power supply 50.

[0039] In one embodiment, please refer to Figure 3 , the above-mentioned power switch unit 20 includes MOS transistor Q106, MOS transistor Q18, and MOS transistor Q20. The gate of MOS transistor Q106 is connected to the voltage detection chip U101; the drain of MOS transistor Q106 is connected to the gate of MOS transistor Q18; the drain of MOS transistor Q18 is connected to the drain of MOS transistor Q20; the source of MOS transistor Q20 is connected to the backend power supply 40; the source of MOS transistor Q18 is connected to the power supply 50.

[0040] In one embodiment, please refer to Figure 3 , the drain of the above-mentioned MOS transistor Q106 is connected to the gate of MOS transistor Q18 through resistor R179; the source of MOS transistor Q18 is connected to resistor R179 through resistor R178. One end of the gate of MOS transistor Q106 is connected to a capacitor C122 grounded at one end.

[0041] In one embodiment, please refer to Figure 3 , the above-mentioned backend power supply 40 is connected to the power discharge unit 30; the discharge unit is connected to the drain of MOS transistor Q106.

[0042] Specifically, when the PWR_EN output signal of the voltage detection circuit is at a high level (the input voltage with the level of VBAT), the Vgs of the N-MOS transistor Q106 is greater than Vth; the MOS transistor Q106 is saturated and turned on. At the same time, the gates of the P-MOS transistors Q18 and Q20 are both pulled low. The source of the MOS transistor Q18 is connected to the VBAT power supply. The Vgs of the P-MOS transistor Q18 is less than Vth, and the MOS transistor Q18 is saturated and turned on. The drain of the MOS transistor Q16 is pulled up to VBAT, and after passing through its body diode, the source of the MOS transistor Q16 is also pulled up. The Vgs of the P-MOS transistor Q16 is less than Vth, and the MOS transistor Q16 is also saturated and turned on. In this way, the entire power supply 50 is turned on, and the VBAT voltage such as VMCU is supplied. When the PWR_EN output signal of the voltage detection circuit is at a low level of 0V, the gate of the N-MOS transistor Q106 is pulled low, and the MOS transistor Q106 is in the cut-off state. In this way, the gates of the MOS transistors Q18 and Q20 are pulled up by the resistors R178 and R179, and the MOS transistors Q18 and Q20 are also cut off. At the same time, the subsequent VMCU power supply is turned off, and since the MOS transistors Q18 and Q20 are two P-MOS transistors with their drains connected, there is no leakage of VMCU to the VBAT terminal. In the off state, the VBAT and VMCU power supplies are in an independent state.

[0043] Through the combination of the MOS transistors Q106, Q18, and Q20, the switching control of the power supply 50 can be realized. When the PWR_EN output signal of the voltage detection circuit is at a high level, that is, when the power supply is working normally, the N-MOS transistor Q106 is turned on, causing the P-MOS transistors Q18 and Q20 to also be turned on, thereby opening the entire power supply 50 link and enabling the circuits such as VMCU to work normally. When the PWR_EN output signal is at a low level, that is, when the power supply is abnormal or turned off, the MOS transistor Q106 is cut off, resulting in the MOS transistors Q18 and Q20 also being cut off, thereby closing the power supply 50 link and protecting the device from power abnormalities or leakage.

[0044] Through the configuration of the MOS transistors Q18 and Q20, the leakage of the VMCU power supply to the VBAT terminal can be effectively prevented. In the off state of the power supply 50, since the MOS transistors Q18 and Q20 are both in the cut-off state and there is no circuit path, the occurrence of power leakage is effectively prevented, improving the safety of the device.

[0045] In the off state of the power supply 50, the VBAT and VMCU power supplies are in an independent state and do not affect each other. This improves the reliability and stability of the system.

[0046] Generally speaking, the design of this power switch unit 20 helps to achieve effective control and protection of the power supply 50, ensuring that the device can respond in a timely manner when the power supply is abnormal or turned off, and protecting the device from power anomalies or leakage, thereby improving the reliability and stability of the system.

[0047] In one embodiment, please refer to Figure 3 , the above-mentioned power discharge unit 30 includes MOS transistor Q105 and discharge resistor R0303; the gate of MOS transistor Q105 is connected to the drain of MOS transistor Q106; the drain of MOS transistor Q105 is connected to the backend power supply 40 through discharge resistor R0303.

[0048] In one embodiment, please refer to Figure 3 , the drain of the above-mentioned MOS transistor Q106 is sequentially connected to the gate of MOS transistor Q105 through resistor R191 and resistor R181.

[0049] In one embodiment, please refer to Figure 3 , the source of the above-mentioned MOS transistor Q105 is grounded.

[0050] In one embodiment, please refer to Figure 3 , a capacitor C117 with one end grounded is connected to the gate of the above-mentioned MOS transistor Q105.

[0051] In this embodiment, when the PWR_EN output signal of the voltage detection circuit is at a high level (the input voltage with the level of VBAT), the Vgs of N-MOS transistor Q106 is greater than Vth, MOS transistor Q106 is saturated and turned on, and at the same time the gate of N-MOS transistor Q105 is pulled low, MOS transistor Q105 is in the cut-off state, and the discharge path composed of VMCU and discharge resistor R0303 is cut off, and there is no leakage. When the PWR_EN output signal of the voltage detection circuit is at a low level of 0V, the gate of N-MOS transistor Q106 is pulled low, MOS transistor Q106 is in the cut-off state, and at this time the gate of N-MOS transistor Q105 is pulled high by resistors R178, R179, R191, and R181, its Vgs is greater than Vth, MOS transistor Q105 is in the on state, and the discharge path composed of backend power supply 40VMCU and discharge resistor R0303 is opened, and the residual charge on the backend power supply 40VMCU network can be quickly discharged through discharge resistor R0303.

[0052] Through the combination of MOS transistor Q105 and discharge resistor R0303, effective discharge of the backend power supply 40 can be achieved. When the PWR_EN output signal of the voltage detection circuit is at a low level, that is, when the power supply is turned off, MOS transistor Q105 conducts, opening the discharge path formed by the backend power supply 40 and discharge resistor R0303, enabling the residual charge in the backend power supply 40 to be quickly discharged through the discharge resistor R0303, protecting the device from the influence of the residual charge in the backend power supply 40, and improving the safety of the device.

[0053] In the power-on state, the gate of MOS transistor Q105 is pulled low, causing MOS transistor Q105 to be cut off, preventing power leakage and protecting the safety of the device and the power supply.

[0054] Through the discharge path of MOS transistor Q105 and discharge resistor R0303, rapid discharge of the residual charge in the backend power supply 40 can be achieved, ensuring that the device can quickly enter a safe state after the power supply is turned off, and improving the reliability and stability of the system.

[0055] Generally speaking, the design of this power supply discharge unit 30 helps to quickly discharge the backend power supply 40 when the power supply is turned off, thereby protecting the device and the power supply and improving the safety and reliability of the system.

[0056] In the above-mentioned power-off and residual charge elimination circuit, when the device battery has sufficient power and the battery voltage is above the threshold voltage of the U101 voltage detection chip, MOS transistors Q106, Q18, and Q20 are in the on state, and MOS transistor Q105 is in the off state. The device operates normally powered by VBAT. When the device battery has insufficient power or during the process of changing the battery, and the battery voltage is below the threshold voltage of the voltage detection chip U101, MOS transistors Q106, Q18, and Q20 are in the off state, and MOS transistor Q105 is in the on state. The backend power supply 40VMCU of the device is in a power-off state, independent of the front-end VBAT power supply 50, and can discharge the residual charge on the network of the backend power supply 40VMCU of the main board in a timely manner through the discharge resistor R0303. The capacitance reserved by capacitor C122 can be used as the delay of the power switch to ensure that after the front-end VBAT power supply is powered on again, the backend VMCU is powered on with a delay, further ensuring the discharge of the residual charge.

[0057] The above-mentioned power-off and residual power elimination circuit, by setting the power voltage detection unit 10, the power switch unit 20 and the power discharge unit 30, when equipment power replacement is required, the power supply 50 is manually disconnected. During this process, the power detection unit will detect the change in the power supply voltage and generate a driving signal; once receiving the driving signal, the power switch unit 20 will cut off the connection between the power supply 50 and the backend power supply 40 and quickly turn on the power discharge unit 30; at the same time, the power discharge unit 30 starts to discharge the residual current in the backend power supply 40 to solve the problem of the device freezing when the main control chip is powered on again when the power supply voltage has not been completely discharged in the ultra-low power consumption mode.

[0058] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or replacements, and these modifications or replacements should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A power shut-off and residual power elimination circuit, characterized in that: include: A power supply voltage detection unit, a power supply switch unit and a power supply discharge unit, wherein the power supply voltage detection unit is used to detect the voltage of the power supply and output a driving signal when the voltage is less than a set threshold; The power switch unit is used to disconnect the path between the power supply and the back-end power supply according to the driving signal and open the power discharge unit; the power discharge unit is used to discharge the residual current of the back-end power supply when the power switch unit is in the open state.

2. A power shut-off and residual power elimination circuit according to claim 1, characterized in that: The power supply voltage detection unit includes a voltage detection chip U101, and the voltage detection chip U101 is connected to the power supply switch unit.

3. A power shut-off and residual power elimination circuit according to claim 2, characterized in that: One end of the voltage detection chip U101 connected to the power switch unit is connected to a pull-up resistor R183; one end of the voltage detection chip U101 is connected to a capacitor C118 with one end grounded; the capacitor C118 is connected in parallel to a resistor R190 with one end grounded.

4. A power shut-off and residual power elimination circuit according to claim 2, characterized in that: The power switch unit includes a MOS tube Q106, a MOS tube Q18 and a MOS tube Q20. The gate of the MOS tube Q106 is connected to the voltage detection chip U101; the drain of the MOS tube Q106 is connected to the gate of the MOS tube Q18; the drain of the MOS tube Q18 is connected to the drain of the MOS tube Q20; the source of the MOS tube Q20 is connected to the back-end power supply; and the source of the MOS tube Q18 is connected to the power supply.

5. A power shut-off and residual power elimination circuit according to claim 4, characterized in that: The drain of the MOS transistor Q106 is connected to the gate of the MOS transistor Q18 through a resistor R179; the source of the MOS transistor Q18 is connected to the resistor R179 through a resistor R178.

6. A power shut-off and residual power elimination circuit according to claim 5, characterized in that: The back-end power supply is connected to the power supply discharge unit; the discharge unit is connected to the drain of the MOS tube Q106.

7. A power shut-off and residual power elimination circuit according to claim 6, characterized in that: The power supply discharge unit includes a MOS tube Q105 and a discharge resistor R0303; the gate of the MOS tube Q105 is connected to the drain of the MOS tube Q106; the drain of the MOS tube Q105 is connected to the back-end power supply through the discharge resistor R0303.

8. A power shut-off and residual power elimination circuit according to claim 7, characterized in that: The drain of the MOS transistor Q106 is connected to the gate of the MOS transistor Q105 through the resistor R191 and the resistor R181 in sequence.

9. A power shut-off and residual power elimination circuit according to claim 8, characterized in that: The source of the MOS tube Q105 is grounded.

10. A power shut-off and residual power elimination circuit according to claim 9, characterized in that: The gate of the MOS transistor Q105 is connected to a capacitor C117 with one end being grounded.

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