Peripheral structure for improving reliability of power device chip

Abstract

The utility model discloses a peripheral structure for improving the reliability of a power device chip, relates to the technical field of power semiconductors, and particularly relates to a device peripheral structure for preventing pollutant ions from invading the interior of the chip. According to the technical scheme of the utility model, the ion intrusion prevention region for preventing external pollutant ions from entering the interior of the chip is arranged between the device region and the electric field cut-off region, and the ion intrusion prevention region and the adjacent device region are located below the same top metal layer. More than one section of first-type groove surrounding the device area is arranged in the device area, an external electrode electrically isolated from the semiconductor groove is arranged in the first-type groove, and the potential of the external electrode is between the potential of the top metal and the potential of the bottom metal or equal to the potential of the bottom metal when the device is reversely biased. And the device stability is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductors, in particular to a peripheral structure for improving the reliability of a power device chip in a trench-type vertical power device. Background Technique

[0002] Common vertical power devices, such as MOSFETs, IGBTs, diodes, etc., have a vertical current path from the top to the bottom and are withstand voltage in the vertical direction of the device when reverse-biased. The peripheral structure of such vertical power device chips will affect the reliability during long-term use, especially for trench-type devices. Generally, trench-type devices have semiconductor trenches, and insulating isolation materials and electrode materials are filled in the trenches. There are many lattice mismatches and defects between the insulating materials and the semiconductor trenches, which are easy to capture charged ions and cause reliability problems. A structure of an existing N-type trench-type vertical power device chip is as Figure 1 shown.

[0003] This structure includes a bottom metal (102), a semiconductor (100) above the bottom metal, a metal isolation layer (115) above the semiconductor (100), a top metal layer (117) above the metal isolation layer, and a passivation layer (118) above the top metal layer. The passivation layer (118) plays a role in protecting against moisture and pollutants from invading the inside of the chip.

[0004] In the above structure, according to the chip area, a device area (120) located inside the chip is also included: in the semiconductor (100) within the device area (120), at least a series of cell trench structures (110) are included, and a buried electrode (105) is provided in the trench. A trench insulating layer (106) is provided between the buried electrode (105) and the semiconductor. In addition, a part of the semiconductor (100) and the buried electrode (105) between the trenches are connected to the top metal layer (117) through a contact hole in the metal isolation layer (115). The top metal layer (117), and the buried electrode (105) connected to the top metal layer (117), may be a gate electrode or a low-potential electrode such as a source / emitter when the device is reverse-biased according to the type of the specific device, and the bottom metal layer (102) is a high-potential electrode when the device is reverse-biased.

[0005] The outermost periphery of the device area (120) has a terminal structure of the device, and this structure may include a terminal trench (111). When the device is reverse-biased, the electric field is laterally cut off within the terminal structure. In addition, at the outermost periphery of the terminal structure, an electric field cut-off area (130) may also be included. The electric field cut-off area (130) is generally provided at the outermost periphery of the chip to ensure that the lateral electric field is cut off within the chip internal area. The electric field cut-off area is at a high potential when the device is reverse-biased.

[0006] After the above-mentioned device is packaged, there is usually a molding compound (119) above the passivation layer. The common molding compound has a large coefficient of thermal expansion and will generate thermal stress on the passivation layer. A common reliability failure mode is as follows Figure 1 shown in the figure: The molding compound (119) in the peripheral area of the chip squeezes the passivation layer (118) at the edge of the top metal (117) during the process of thermal expansion and contraction, causing cracks to appear. Pollutant ions penetrate through the passivation layer 118 and enter the metal isolation layer (115). In an N-type device, when reverse-biased, the potential inside the chip is low and the potential outside the chip is high. Therefore, positively charged pollutant ions (such as H+, Na+, K+) move from the outside of the chip to the inside under the action of a high electric field and finally stay at the lattice mismatch or lattice defect of the semiconductor trench and trench insulation layer (106), forming fixed positive charges. These fixed positive charges will increase the leakage current between the top and bottom of the device, affect the breakdown ability of the device, and also reduce the threshold voltage of the device, resulting in gate leakage. Summary of the Invention

[0007] In view of the problems of the existing trench-type vertical power devices mentioned above, it is necessary to propose a device peripheral structure that prevents pollutant ions from invading the inside of the chip and improves the reliability of the device.

[0008] A peripheral structure for improving the reliability of a power device chip provided by the present invention. The device includes a device area inside the chip and an electric field cut-off area located at the outermost periphery of the device area. An anti-ion invasion area for preventing external pollutant ions from entering the inside of the chip is also provided between the device area and the electric field cut-off area. The anti-ion invasion area and the adjacent device area are located under the same top metal layer. One or more first-type trenches surrounding the device area are provided in the anti-ion invasion area. External electrodes that are electrically isolated from the semiconductor trenches are provided in the first-type trenches. The external electrodes are connected to other metal layers or semiconductor areas other than the top metal layer. The potential of the external electrodes is between the potential of the top metal and the potential of the bottom metal or equal to the potential of the bottom metal when the device is reverse-biased.

[0009] Furthermore, the minimum distance d1 between the first-type trenches and the terminal structure in the device area is greater than the depth of the drift region of the devices in the device area.

[0010] Furthermore, the electric field cut-off area includes one or more cut-off trenches surrounding the chip and one or more protection ring trenches surrounding the cut-off trenches. The cut-off trenches and the protection ring trenches are located under the same cut-off metal layer. The cut-off electrodes in the cut-off trenches are connected to the cut-off metal layer.

[0011] Further, one or more second trenches are provided on the periphery of the first trenches within the anti-ion invasion region, and the buried electrodes within the second trenches are connected to the top metal layer.

[0012] Furthermore, multiple first trenches and second trenches are arranged in a trench network manner; or,

[0013] multiple first trenches and / or second trenches are arranged in an annular trench manner; or,

[0014] multiple first trenches and second trenches are alternately arranged in a spiral trench manner.

[0015] Furthermore, in the annular trench arrangement or the spiral trench arrangement, the first trenches and the second trenches are chamfered at the four corners of the quadrilateral chip to adjust the distance from the first trenches to the cut-off trenches.

[0016] Further, the first trenches are connected to the peripheral trenches provided on the periphery of the top metal layer through a connecting trench, and the external electrodes within the first trenches are connected to the electrodes within the connecting trench and the peripheral trenches; or

[0017] the first trenches are connected to an external potential through a connecting metal provided at the top of the trenches.

[0018] Furthermore, the electrodes within the first trenches, the connecting trenches, and the peripheral trenches are the same, and the height of the electrodes within the first trenches and the peripheral trenches is higher than the height of the electrodes within the connecting trenches.

[0019] The present utility model provides a peripheral structure of a trench-type vertical power device, which is beneficial to preventing pollutant ions from invading the inside of the chip and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a cross-sectional structural schematic diagram of an existing N-type trench-type vertical power device chip;

[0021] Figure 2 is a cross-sectional structural schematic diagram of an N-type trench-type device according to an embodiment of the present utility model;

[0022] Figure 3 is a cross-sectional structural schematic diagram of an N-type trench-type device according to another embodiment of the present utility model and a schematic diagram of an ion invasion path;

[0023] Figure 4 is a top view of a trench structure of two connection methods of an external electrode (205) within a first trench (210) of the present utility model;

[0024] Figure 5Schematic cross-sectional structure diagram of an embodiment, where 5A is a schematic cross-sectional structure diagram of tangent line A in the groove embodiment of 4A, and 5B is a schematic cross-sectional structure diagram of another embodiment of the present invention;

[0025] Figure 6 Top view of the groove structure, where 6A is a top view of the groove structure of another embodiment of the present invention, and 6B is a top view of the groove structure of another embodiment of the present invention;

[0026] Figure 7 Top view of the groove structure of another embodiment of the present invention.

[0027] Figure 8 Schematic diagram of the groove connection method, where 8A is a top view of the structure of the first type of groove (210) and the second type of groove (211) in an embodiment of the present invention, and 8B and 8C are top views of the groove connection methods on different sides of the quadrilateral chip in the embodiment of 8A;

[0028] Figure 9 Schematic diagram of the groove connection method, 9A is a top view of the structure of the first type of groove (210) and the second type of groove (211) in another embodiment, and 9B and 9C are top views of the groove connection methods on different sides of the quadrilateral chip in the embodiment of 8A. Detailed implementation manner

[0029] The relevant technical background of the existing power devices will be described below. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", and "vertical" described in this document are relative positions corresponding to the reference drawings. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to scale. The straight lines shown at the boundaries of the doped regions and grooves in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0030] The present utility model will be described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that in the following description of the trench device and its manufacturing method of the present utility model, the semiconductor substrate of the trench device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for manufacturing trench devices, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A semiconductor region of P-type conductivity can be formed by doping one or several impurities into the original semiconductor region, and these impurities can be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc. A semiconductor region of N-type conductivity can also be formed by doping one or several impurities into the original semiconductor region, and these impurities can be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H+), etc. In the following description, a heavily doped semiconductor region of P-type conductivity is marked as P+ region, and a heavily doped semiconductor region of N-type conductivity is marked as N+ region. For example, in a silicon material substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally between 1×10 19 cm -3 and 1×10 21 cm -3 . Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in the present utility model can be interchanged.

[0031] Those skilled in the art should know that the present utility model can be applied to P-type (second conductivity type) and N-type (first conductivity type) semiconductor devices. For the device formed after the interchange of the P-type (second conductivity type) and N-type (first conductivity type) regions, the corresponding potential level, current direction, positive and negative of charged ions, etc. will also be reversed.

[0032] Figure 2 FIG. is a cross-sectional structural schematic diagram of an N-type trench device according to an embodiment of the present utility model.

[0033] The structure includes a bottom metal (102), a semiconductor (100) above the bottom metal, a metal isolation layer (115) above the semiconductor (100), a top metal layer (117) above the metal isolation layer, and a passivation layer (118) above the top metal layer. Among them, the passivation layer (118) plays a role in protecting the chip interior from the intrusion of moisture and contaminants.

[0034] In the above structure, according to the chip region, it further includes a device region (120) inside the chip, and an anti-ion intrusion region (220) outside the device region (120).

[0035] The described ion-invasion prevention region (220) and the adjacent device region (120) are located below the same segment of the top metal layer (117).

[0036] The ion-invasion prevention region (220) includes one or more segments of first-type trenches (210) surrounding the device region (120), and external electrodes (205) electrically isolated from the semiconductor trenches are disposed within the first-type trenches (210).

[0037] The described external electrode (205) is connected to a non-top-metal potential (referring to positions other than the top metal, such as electrodes within the cutoff trench (112) and the guard ring trench (213), the metal on top of the cutoff trench (112), or the connecting metal (121) mentioned later, or the first additional trench (231), the second additional trench (232), and the region between the first additional trench (231) and the second additional trench (232). These metal regions have different potentials from the top metal during reverse bias), and its potential during reverse bias is between the potential of the top metal 117 and the potential of the bottom metal 102, or the same as the potential of the bottom metal; the described external electrode (205) can also be connected to other semiconductor regions (such as the semiconductor region between the second-type trench (211) and the cutoff trench (122) later or the semiconductor region between the annular first additional trench (231) and the annular second additional trench (232) surrounding the ion-invasion prevention region (220)).

[0038] In the semiconductor (100) within the above-mentioned device region (120), there are at least a series of cell trench structures (110), with buried electrodes (105) disposed within the trenches, and a trench insulating layer (106) is provided between the buried electrodes (105) and the semiconductor. In addition, a part of the semiconductor (100) between the trenches and the buried electrodes (105) are connected to the top metal layer (117) through contact holes in the metal isolation layer (115). The top metal layer (117), and the buried electrodes (105) connected to the top metal layer (117), may be gate electrodes or source / emitters, etc., depending on the type of the specific device, and are low-potential electrodes during reverse bias of the device, while the bottom metal layer (102) is a high-potential electrode during reverse bias of the device. The outermost periphery of the device region (120) has a terminal structure of the device, and the terminal structure may include a terminal trench (111), and the electric field is laterally cut off within the terminal structure during reverse bias of the device.

[0039] As Figure 2In the N-type device, since the potential of the external electrode (205) in the first type of trench (210) is higher than the potentials of the top metal layer (117) and the buried electrode (105) in the device region (120), the semiconductor near the first type of trench (210) and the direction of the electric field in the metal isolation layer (115) above it are changed, thereby reducing the lateral intrusion of positive ions into the chip interior and avoiding Figure 1 the device failure caused by the intrusion of positive ions into the device region (120) as described in

[0040] Generally, the minimum distance d1 between the first type of trench (210) and the terminal structure in the device region (120) is greater than the depth of the drift region of the device in the device region (usually about the depth of the cell trench structure 110) to ensure that the breakdown voltage of the device during reverse bias is not affected by the potential of the first type of trench (210). In a 30V device embodiment, this distance d1 is between 2 - 10 um.

[0041] In addition, in some embodiments, the outermost periphery of the terminal structure may further include an electric field cutoff region (130). The function of the electric field cutoff region (130) is to cutoff the internal electric field of the chip and prevent the internal electric field of the chip from extending to the dicing channel to form a lateral leakage path. This region may include cutoff trenches (112) surrounding the chip and a cutoff metal layer (116) above the cutoff trenches. In addition, in some embodiments, there may be one or more protection ring trenches (213) surrounding the cutoff trenches (112) outside the cutoff trenches. The cutoff metal layer (116) is generally connected to the cutoff electrode in the cutoff trench (112) and the semiconductor outside the cutoff trench, and its potential is the same as the lower surface metal during reverse bias of the device.

[0042] Furthermore, another embodiment of the N-type device of the present invention is shown in Figure 3A.

[0043] and Figure 2 is different from that in

[0044] When the device is reverse-biased, the potential of the external electrode (205) in the first type of trench (210) is higher than that of the buried electrode (105) in the second type of trench (211). Therefore, in the region between the first type of trench (210) and the second type of trench (211), the metal isolation layer (115) above it, and the nearby semiconductor region, there is an electric field direction from the inside of the chip to the outside, and the magnitude of this electric field is related to the potential difference between the external electrode (205) and the buried electrode (105). Therefore, the positive ions invading from the outside of the chip to the inside stay near the second type of trench (211) under the action of the reverse electric field in the ion invasion prevention region (220), and do not invade the device region (120), as shown in 3B.

[0045] In addition, for the combined structure of the first type of trench (210) and the second type of trench (211) described in the above N-type structure, even if a small amount of contaminant negative ions invade, they will be concentrated near the first type of trench (210) under the built-in electric field in the ion invasion prevention region (220), preventing ions from invading the device region (120).

[0046] The external electrode (205) in the first type of trench (210) needs to be connected to an appropriate peripheral structure to be at the required potential during reverse biasing. A connection method for the external electrode (205) may be as shown in 4A and 4B.

[0047] As shown in the top view of the trench structure in 4A, which is an example of a connection method for an external electrode (205), the first type of trench (210) is connected to the peripheral trench (222) through a connection trench (212) with a different direction, and the external electrode (205) is connected in the first type of trench (210), the connection trench (212), and the peripheral trench (222). The peripheral trench (222) is located at the periphery of the top metal layer (117).

[0048] As shown in the top view of the trench structure in 4B, which is another example of a connection method for an external electrode (205), the difference from 4A is that there are multiple segments of the second type of trench (211) parallel to the first type of trench (210) around the first type of trench (210). The second type of trench (211) surrounds the first type of trench (210) and is all located under the same segment of the top metal layer (117). The connection trench (212) passes through the gaps between the multiple segments of the second type of trench (211) and is connected to the peripheral trench (222) at the periphery.

[0049] In some embodiments, the above-mentioned peripheral trench (222) may be a cutoff trench (112) or a guard ring trench (213), and the electrodes in the trench have the same potential as the device bottom metal (102) when the device is reverse-biased.

[0050] In some embodiments, the above-mentioned peripheral trench (222) may also be an additional semiconductor trench located between the cutoff trench (112) and the ion-invasion prevention region (220). When the device is reverse-biased, the potential of the electrode in the trench is between the potential of the top metal layer (117) and the potential of the bottom metal (102).

[0051] Figure 5A is a schematic cross-sectional structure diagram of the tangent line A in the trench embodiment of Figure 4A. Among them, the external electrode (205) is located in the first type of trench (210), the connection trench (212), and the peripheral trench (222), and the height of its upper surface is the same as that of the buried electrode (105) in the cell trench structure (110) in the device region (120).

[0052] In one embodiment, as shown in Figure 5B, the external electrode (205) is located in the first type of trench (210), the connection trench (212), and the peripheral trench (222), and the height of its upper surface has high and low variations. In a specific embodiment of a shield-gate trench field-effect transistor device, for the external electrode (205) located in the first type of trench (210) and the peripheral trench (222), the height of its upper surface is relatively high, and the distance from the semiconductor upper surface is 0.05 - 0.5 μm; for the external electrode (205) in the connection trench (212), the height of its upper surface is relatively low, and the distance from the semiconductor upper surface is 0.4 - 2 μm. In this structure, the external electrode (205) in the connection trench (212) is far from the semiconductor upper surface, which is beneficial to reducing the influence of the external electrode (205) on the electric field distribution near the semiconductor upper surface in the direction along the connection trench (212).

[0053] In the above-described illustrated embodiments, only one trench is marked for the second type of trench (211) and the first type of trench (210) in the ion-invasion prevention region (220). In fact, in some embodiments, multiple first type of trenches (210) / second type of trenches (211) parallel to each other may be provided in the ion-invasion prevention region (220) to increase the ion-invasion path length and enhance the effect of preventing ion invasion, as shown in the embodiment shown in Figure 6A.

[0054] In some embodiments, a trench combination in which multiple second type of trenches (211) and first type of trenches (210) are adjacent to each other may also be provided, and the outermost trench located under the top metal layer (117) is the second type of trench (211), as Figure 6 shown in Figure 6B. In some embodiments, the first type of trench (210) may also be set as a trench network to surround multiple segments of the second type of trench (211). The trench combination in which multiple second type of trenches (211) and first type of trenches (210) are adjacent to each other is beneficial to enhancing the effect of preventing charged ion invasion.

[0055] In the embodiments of the present utility model, the multiple first-type grooves (210) and second-type grooves (211) may adopt a closed ring-shaped groove structure or a non-closed groove structure, such as the combined structure of spiral grooves and ring-shaped grooves shown in 8A or 9A. In some embodiments, a more complex mesh groove structure may also be adopted.

[0056] Figure 7 It is a top view of the groove structure of a chip embodiment of the present utility model.

[0057] Compared with the above embodiments, the first-type grooves (210) and the second-type grooves (211) surround the device area (120) and have arc-shaped corners or 120-degree corners at the corners of the quadrilateral chip. The connecting grooves (212) extend from the inside to the outside at the corners of the quadrilateral chip and are connected to the peripheral cutoff grooves (112).

[0058] Since the distance from the first-type grooves (210) to the cutoff grooves (112) can be conveniently adjusted at the corners of the quadrilateral chip, the connecting grooves (212) can be provided without significantly affecting the area of the device area (120).

[0059] In the above embodiments, the external electrodes (205) in the first-type grooves (210) are all connected to the peripheral potential through the connecting grooves (212). In some embodiments, it may also be connected by a connecting metal located at the top of the groove, as shown in Figure 8 and Figure 9 the shown embodiments.

[0060] Figure 8 It is another embodiment of the present utility model. Among them, 8A is a top view of the structure of the first-type grooves (210) and the second-type grooves (211) in the quadrilateral chip, and 8B and 8C are schematic diagrams of the groove connection methods on different sides of the quadrilateral chip.

[0061] In this structure, two adjacent first-type grooves (210) surround the device area (120) and form a spiral structure, as shown in 8A. Among them, the electrodes in the first circle of the first-type grooves (214) and the second circle of the first-type grooves (215) are at different positions, and are connected to the connecting metal (121) through the contact holes (122), and then connected to the external potential through another contact hole (122).

[0062] In one embodiment, the external potential may be the semiconductor area between the second-type grooves (211) and the cutoff grooves (122), as shown in 8B and 8C.

[0063] Due to the minimum pitch limitation of the metal, after the connecting metal (121) is set, the adjacent top metal (117) needs to be indented. As shown in 8B, the connecting metal (121) is provided at the top of the first type of trench (214) in the first circle. Therefore, the adjacent top metal (117) needs to be indented into the inner region of the first type of trench (214) in the first circle. As a result, the first type of trench (214) in the first circle cannot achieve the function of preventing ions from invading the chip interior from the boundary of the top metal (117).

[0064] Therefore, in the above embodiment, a plurality of mutually surrounding first type of trenches (210) with a spiral structure are adopted. In this structure, the second circle of the first type of trenches (215) located inside the first circle of the first type of trenches (214) ensures that the boundary of the indented top metal (117) is located on its periphery and plays a role in preventing ion invasion. Correspondingly, a connecting metal (121) is provided above the second circle of the first type of trenches (215) in 8C to connect to the peripheral potential, and the top metal (117) above it is indented inward. At this time, the first circle of the first type of trenches (214) located inside the second circle of the first type of trenches (215) can ensure that the boundary of the indented top metal (117) is located on its periphery and plays a role in preventing ion invasion.

[0065] Figure 9 For another embodiment of the present invention, 9A is a top view of the structure of the first type of trenches (210) and the second type of trenches (211) in a quadrilateral chip, and 9B and 9C are schematic diagrams of the trench connection methods on different sides of the quadrilateral chip.

[0066] In this structure, a combination of adjacent multiple groups of the first type of trenches (210) and the second type of trenches (211) surrounds the device region (120) and forms a spiral structure, as shown in 9A.

[0067] Among them, the electrodes in the first circle of the first type of trenches (214) and the second circle of the first type of trenches (215) are at different positions, and are connected to the connecting metal (121) through the contact holes (122), and then connected to the external potential through another contact hole (122).

[0068] In one embodiment, this external potential may be the semiconductor region between the annular first additional trench (231) and the annular second additional trench (232) outside the ion invasion prevention region (220), as shown in 9B and 9C.

[0069] And Figure 8 Compared with the structure in

[0070] In addition, those skilled in the art should know that the structural features mentioned in each of the above-described embodiments of the present utility model can be combined with each other to form more device structures of embodiments.

Claims

1. A peripheral structure for improving the reliability of a power device chip, wherein the device comprises a device region inside the chip and an electric field cutoff region located at the outermost periphery of the device region, characterized in that: The peripheral structure also includes an anti-ion intrusion area arranged between the device area and the electric field cutoff area for preventing external pollutant ions from entering the interior of the chip. The anti-ion intrusion area and the adjacent device area are located below the same top metal layer. The anti-ion intrusion area is provided with more than one first-type groove surrounding the device area. The first-type groove is provided with an external electrode electrically isolated from the semiconductor groove. The external electrode is connected to other metal layers or semiconductor areas except the top metal layer. When the device is reverse biased, the potential of the external electrode is between the potential of the top metal and the potential of the bottom metal or is equal to the potential of the bottom metal.

2. The peripheral structure for high power device chip reliability as claimed in claim 1, characterized in that: The minimum distance d1 between the first type of trench and the terminal structure in the device region is greater than the depth of the drift region of the device in the device region.

3. The peripheral structure for high power device chip reliability as claimed in claim 1, characterized in that: The electric field cutoff region includes one or more cutoff grooves surrounding the chip and one or more guard ring grooves surrounding the cutoff grooves. The cutoff grooves and the guard ring grooves are located under the same section of the cutoff metal layer. The cutoff electrode in the cutoff groove is connected to the cutoff metal layer.

4. The peripheral structure for high power device chip reliability as claimed in claim 1, characterized in that: More than one second type of trench is provided around the first type of trench in the anti-ion invasion region, and the buried electrode in the second type of trench is connected to the top metal layer.

5. The peripheral structure for high power device chip reliability as claimed in claim 4, characterized in that: A plurality of the first type grooves and the second type grooves are arranged in a groove network manner; or, A plurality of the first type grooves and / or the second type grooves are arranged in a ring-shaped groove manner; or, A plurality of first-type grooves and second-type grooves are arranged alternately in a spiral groove manner.

6. The peripheral structure for high power device chip reliability as claimed in claim 5, characterized in that: The first type of grooves and the second type of grooves are arranged in a circular groove manner or a spiral groove manner, and the four corners of the quadrilateral chip are chamfered.

7. The peripheral structure for high power device chip reliability as claimed in claim 1, characterized in that: The first type of trench is connected to a peripheral trench disposed at the periphery of the top metal layer through a connecting trench, and the external electrode in the first type of trench is connected to the electrodes in the connecting trench and the peripheral trench; or The first type of trench is connected to an external potential through a connection metal disposed on the top of the trench.

8. The peripheral structure for high power device chip reliability as claimed in claim 7, characterized in that: The electrodes in the first type of trenches, the connecting trenches and the peripheral trenches are the same, wherein the heights of the electrodes in the first type of trenches and the peripheral trenches are higher than the height of the electrodes in the connecting trenches.

Images