Solar cell

Abstract

The utility model provides a solar cell comprising a silicon substrate having a first surface and a second surface opposite to each other; the intrinsic amorphous silicon layer and the doped semiconductor layer are sequentially stacked on the first surface and the side surface of the silicon substrate; the tunneling layer and the doped polycrystalline silicon layer are sequentially stacked on the second surface, and the doping type of the doped polycrystalline silicon layer is opposite to that of the doped semiconductor layer; the first transparent conductive layer is arranged on the doped semiconductor layer on the first surface, and the second transparent conductive layer is arranged on the doped polycrystalline silicon layer and extends to the side surface of the silicon substrate; the first transparent conductive layer is also arranged on a doped semiconductor on the side surface of the silicon substrate or a second transparent conductive layer on the side surface of the silicon substrate; the isolation groove is formed in the edge of the silicon substrate and penetrates through the first transparent conducting layer and / or the second transparent conducting layer, and / or the isolation groove is formed in the side face of the silicon substrate and penetrates through the first transparent conducting layer and the second transparent conducting layer. According to the solar cell, the transparent conductive layer is disconnected through the isolation groove, and short-circuit current can be reduced.

Description

Technical Field

[0001] This application mainly relates to the field of photovoltaic technology, and particularly to a solar cell. Background Art

[0002] The tunnel oxide passivated contact structure (TOPcon) and the hetero junction structure (HJT) in a solar cell can improve the conversion efficiency of the solar cell. However, there is a short - circuit current between the two. How to avoid the occurrence of short - circuit between the two is one of the important research directions in this field. Summary of the Utility Model

[0003] The technical problem to be solved by this application is to provide a solar cell that can avoid the occurrence of short - circuit current between the TOPcon passivation structure and the HJT passivation structure.

[0004] To solve the above - mentioned technical problem, this application provides a solar cell, including: a silicon substrate having opposite first and second surfaces; an intrinsic amorphous silicon layer and a doped semiconductor layer, which are sequentially stacked on the first surface and the side surface of the silicon substrate; a tunneling layer and a doped polysilicon layer, which are sequentially stacked on the second surface, and the doping type of the doped polysilicon layer is opposite to the doping type of the doped semiconductor layer; a first transparent conductive layer disposed on the doped semiconductor layer located on the first surface, a second transparent conductive layer disposed on the doped polysilicon layer and extending to the side surface of the silicon substrate, and the first transparent conductive layer is also disposed on the doped semiconductor on the side surface of the silicon substrate or on the second transparent conductive layer on the side surface of the silicon substrate; and an isolation groove located at the edge of the silicon substrate and penetrating the first transparent conductive layer and / or the second transparent conductive layer, and / or the isolation groove is located on the side surface of the silicon substrate and penetrates the first transparent conductive layer and the second transparent conductive layer.

[0005] In an embodiment of this application, the first surface is the light - facing surface and the second surface is the back - light surface, or the first surface is the back - light surface and the second surface is the light - facing surface.

[0006] In an embodiment of this application, the solar cell further includes an antireflection layer disposed on the transparent conductive layer located on the light - facing surface and the side surface of the silicon substrate, wherein the antireflection layer includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0007] In an embodiment of this application, the solar cell further includes a plurality of electrodes, and the plurality of electrodes are in contact with the corresponding transparent conductive layer.

[0008] On the other hand, the present application also provides a solar cell, comprising: a silicon substrate having opposite first and second surfaces; an intrinsic amorphous silicon layer and a doped semiconductor layer, which are sequentially stacked on the first surface and the side surface of the silicon substrate; a tunneling layer and a doped polysilicon layer, which are sequentially stacked on the second surface, and the doping type of the doped polysilicon layer is opposite to that of the doped semiconductor layer; an antireflection layer, which is disposed on the doped semiconductor layer or the doped polysilicon layer (150) and extends to the side surface of the silicon substrate, and the antireflection layer is located on the light-receiving surface of the silicon substrate; a third transparent conductive layer, which is disposed opposite to the antireflection layer on the silicon substrate and extends to the side surface of the silicon substrate; and an isolation groove, which is located at the edge of the silicon substrate and penetrates the third transparent conductive layer, and / or the isolation groove is located on the side surface of the silicon substrate and penetrates the third transparent conductive layer.

[0009] In an embodiment of the present application, the solar cell further comprises a plurality of electrodes, and the plurality of electrodes penetrate the antireflection layer and are in contact with the doped semiconductor layer or the doped polysilicon layer.

[0010] In an embodiment of the present application, the width of the isolation groove is greater than 5 μm and less than 5000 μm, and the distance between the isolation groove and the outermost side of the solar cell is less than 15 mm.

[0011] In an embodiment of the present application, the antireflection layer comprises any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0012] In an embodiment of the present application, the intrinsic amorphous silicon layer contains any one of oxygen element, carbon element, and nitrogen element.

[0013] In an embodiment of the present application, the doped semiconductor layer comprises amorphous silicon and / or microcrystalline silicon.

[0014] Compared with the prior art, the present application has the following advantages: the solar cell of the present application disconnects the transparent conductive layer through the isolation groove, which can reduce the short-circuit current. In addition, the isolation groove is located at the edge of the solar cell, so that the area of the transparent conductive layer can be maximized. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are provided to further understand the present application, and they are incorporated and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and, together with the description of the present application, serve to explain the principles of the present application. In the accompanying drawings:

[0016] Figures 1 to 7 is a cross-sectional schematic diagram of a solar cell in different embodiments of the present application.

[0017] REFERENCE NUMERALS

[0018] Silicon substrate 110, tunneling layer 140, opening 210

[0019] First side 111, doped polysilicon layer 150, diffusion layer 220

[0020] Second side 112, first transparent conductive layer 160, first electrode 230

[0021] Side surface 113, second transparent conductive layer 170, second electrode 240

[0022] Intrinsic amorphous silicon layer 120, isolation groove 180, third transparent conductive layer 250

[0023] Doped semiconductor layer 130, antireflection layer 190 Detailed implementation mode

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios according to these drawings. Unless it is obvious from the language context or otherwise stated, the same reference numerals in the drawings represent the same structure or operation.

[0025] As shown in the present application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0026] Unless otherwise specifically stated, the relative arrangements, numerical expressions and values of the components and steps described in these embodiments do not limit the scope of the present application. At the same time, it should be understood that for the sake of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. Technologies, methods and devices known to those of ordinary skill in the relevant fields may not be discussed in detail, but in appropriate cases, the said technologies, methods and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be interpreted as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in the subsequent drawings.

[0027] In the description of the present application, it should be understood that the orientation or positional relationship indicated by orientation terms such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom", etc. is usually based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. Without contrary instructions, these orientation terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the protection scope of the present application; the orientation terms "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0028] For the sake of convenience in description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above-mentioned", etc. can be used here to describe the spatial positional relationship between a device or feature shown in the drawings and other devices or features. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation described in the drawings for the device. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned as "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding explanations are made for the spatial relative descriptions used here.

[0029] In addition, it should be noted that the use of terms such as "first", "second", etc. to limit components is only for the convenience of distinguishing the corresponding components. Without additional statements, the above terms have no special meanings. Therefore, it should not be construed as a limitation on the protection scope of the present application. In addition, although the terms used in the present application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of the description herein. In addition, it is required to understand the present application not only through the actual terms used, but also through the meanings implied by each term.

[0030] Next, the solar cell of the present application will be described by way of examples.

[0031] Refer to Figure 1 As shown, the silicon substrate 110 has opposite first surface 111 and second surface 112. The first surface 111 can be the light-facing surface, and the corresponding second surface 112 is the backlight surface. The first surface 111 can also be the backlight surface, and the corresponding second surface 112 is the light-facing surface. The silicon substrate 110 can be an N-type or P-type doped single-crystalline silicon.

[0032] The intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are sequentially stacked on the first surface 111, and the intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are also sequentially stacked on the side surface 113 of the silicon substrate 110. The thickness of the intrinsic amorphous silicon layer 120 can be 3 nm to 15 nm. For example, the thickness is 3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm. The thickness of the intrinsic amorphous silicon layer 120 can be 3 nm to 60 nm. For example, the thickness is 3 nm, 13 nm, 23 nm, 33 nm, 43 nm, 53 nm, or 60 nm. The intrinsic amorphous silicon layer 120 can contain any of oxygen element (O), carbon element (C), and nitrogen element (N). The doped semiconductor layer 130 can include amorphous silicon and / or microcrystalline silicon. For example, the doped semiconductor layer 130 is N-type or P-type doped amorphous silicon. The doped semiconductor layer 130 can contain one or more of oxygen element, carbon element, or nitrogen element.

[0033] The tunneling layer 140 and the doped polysilicon layer 150 are sequentially stacked on the second surface 112. The tunneling layer 140 can be silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), or one or more of them. The thickness of the tunneling layer 140 is equal to or less than 3 nm. For example, the thickness is 1 nm, 2 nm, or 3 nm. The tunneling layer 140 can contain the doping elements in the doped polysilicon layer 150 and / or the silicon substrate 110. The doped polysilicon layer 150 can be an N-type or P-type doped polysilicon layer, and the doping type of the doped polysilicon layer 150 is opposite to the doping type of the doped semiconductor layer 130. For example, the doped polysilicon layer 150 is N-type doped and the doped semiconductor layer 130 is P-type doped. The doped polysilicon layer 150 can contain one or more of oxygen element, carbon element, and nitrogen element. The thickness of the doped polysilicon layer 150 can be 20 nm to 600 nm. For example, the thickness is 20 nm, 120 nm, 220 nm, 320 nm, 420 nm, 520 nm, or 600 nm.

[0034] In the Figure 1 embodiment, the tunneling layer 140 and the doped polysilicon layer 150 are not formed on the side surface 113, so as to avoid short circuit between the tunneling layer 140 and the doped polysilicon layer 150 (TOPcon passivation structure) on the side surface 113 and the intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 (HJT passivation structure).

[0035] In one embodiment, the solar cell has a diffusion layer 220. The diffusion layer 220 is located between the tunneling layer 140 and the silicon substrate 110, and the doping type of the diffusion layer 220 is the same as that of the doped polysilicon layer 150. The diffusion layer 220 can be an N-type or P-type doped single-crystalline silicon. The thickness of the diffusion layer 220 is equal to or greater than 20 nm and equal to or less than 1500 nm. For example, the thickness is 20 nm, 120 nm, 220 nm, 320 nm, 420 nm, 520 nm, 620 nm, 720 nm, 820 nm, 920 nm, 1020 nm, 1120 nm, 1220 nm, 1320 nm, 1420 nm, or 1500 nm.

[0036] The first transparent conductive layer 160 is disposed on the doped semiconductor layer 130 located on the first surface 111, and the first transparent conductive layer 160 is also disposed on the doped semiconductor layer 130 located on the side surface 113. The second transparent conductive layer 170 is disposed on the doped polysilicon layer 150 and extends to the side surface 113.

[0037] Reference Figure 4 As shown, in some other embodiments, the first transparent conductive layer 160 located on the side surface 113 is disposed on the second transparent conductive layer 170. Specifically, the second transparent conductive layer 170 located on the side surface 113 is disposed on the doped semiconductor layer 130 located on the side surface 113, and the first transparent conductive layer 160 located on the side surface 113 is disposed on the second transparent conductive layer 170 located on the side surface 113.

[0038] The first transparent conductive layer 160 can include one or more of zinc oxide (ZnO), indium oxide (InO), and tin oxide (SnO), and the first transparent conductive layer 160 can contain one or more of gallium (Ga), tin (Sn), cesium (Ce), molybdenum (Mo), fluorine (F), tungsten (W), and aluminum (Al). The thickness of the first transparent conductive layer 160 is equal to or greater than 10 nm and less than or equal to 200 nm. For example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm.

[0039] The second transparent conductive layer 170 can include one or more of zinc oxide, indium oxide, and tin oxide, and the first transparent conductive layer 160 can contain one or more of gallium, tin, cesium, molybdenum, fluorine, tungsten, and aluminum. The thickness of the first transparent conductive layer 160 is equal to or greater than 10 nm and less than or equal to 200 nm. For example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm. The thickness of the first transparent conductive layer 160 can be equal to or different from the thickness of the second transparent conductive layer 170.

[0040] The isolation groove 180 is located at the edge of the silicon substrate 110, and the isolation groove 180 penetrates through the first transparent conductive layer 160. The first transparent conductive layer 160 located on the side surface 113 is in contact with the second transparent conductive layer 170 located on the side surface. The isolation groove 180 penetrating through the first transparent conductive layer 160 can prevent the first transparent conductive layer 160 located on the side surface 113 from electrically connecting the first electrode 230 and the second transparent conductive layer 170, thereby avoiding the occurrence of short-circuit current between the TOPcon passivation structure and the HJT passivation structure in the battery.

[0041] The first electrode 230 is in contact with the first transparent conductive layer 160, and the second electrode 240 is in contact with the second transparent conductive layer 170.

[0042] Reference Figure 2 As shown, in Figure 2 the embodiment, the isolation groove 180 is still located at the edge of the silicon substrate 110. Different from Figure 1 that, Figure 1 the isolation groove 180 in Figure 2 is located on the first surface 111, and the transparent conductive layer penetrated is the first transparent conductive layer 160.

[0043] As Figure 2 shown, the isolation groove 180 can penetrate into the doped polysilicon layer 150 to a certain depth, and the isolation groove 180 can also penetrate through the doped polysilicon layer 150.

[0044] Reference Figure 3 As shown, in Figure 3 the embodiment, the isolation groove 180 is located on the side surface 113 and penetrates through the first transparent conductive layer 160 and the second transparent conductive layer 170, so that the first transparent conductive layer 160 and the second transparent conductive layer 170 located on the side surface 113 can be prevented from electrically connecting the first electrode 230 and the second electrode 240.

[0045] If Figure 1 the second surface 112 in Figure 1 is the light-facing surface, then compared with the embodiment in 2, since Figure 1 the isolation groove 180 in

[0046] In one embodiment, the width of the isolation groove 180 is greater than 5 μm and less than 5000 μm. For example, the width is 500 μm, 1000 μm, 1500 μm, 2000 μm, 2500 μm, 3000 μm, 3500 μm, 4000 μm, 4500 μm. The isolation groove 180 can be prepared by laser.

[0047] Reference Figure 1 and Figure 2 As described, in one embodiment, the distance d1 between the isolation groove 180 and the outermost side of the solar cell is less than 15 mm. For example, the distance d1 is 0 nm, 5 mm or 10 nm. When the distance d1 is 0 nm, it means that one side of the isolation groove 180 is located at the outermost side of the solar cell. The distance d1 being less than 15 mm can maximize the area of the transparent conductive layer on the first surface 111 and / or the second surface 112, so that photo-generated carriers can be effectively collected.

[0048] Reference Figure 5 As shown, in one embodiment, the second surface 112 is the light-receiving surface. The solar cell further includes an antireflection layer 190, and the antireflection layer 190 is disposed on the second transparent conductive layer 170 located on the second surface 112 and the side surface 113. The antireflection layer 190 can include any one of silicon nitride, silicon oxide, and silicon oxynitride. The thickness of the antireflection layer 190 is greater than or equal to 10 nm and less than or equal to 200 nm. For example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm or 200 nm. The second electrode 240 contacts the second transparent conductive layer 170 after passing through the antireflection layer 190. An opening 210 for the second electrode 240 to pass through can be formed in the antireflection layer 190 by a laser drilling process.

[0049] Reference Figure 6 As shown, Figure 6 Differences from Figure 5 include: at the side surface 113, the second transparent conductive layer 170 covers the doped semiconductor layer 130, the first transparent conductive layer 160 covers the second transparent conductive layer 170, and the antireflection layer 190 covers the first transparent conductive layer 160.

[0050] On the other hand, the present application further proposes a solar cell, and the following is an explanation of this solar cell.

[0051] Reference Figure 7 As shown, in Figure 7 the embodiment, the second surface 112 is the light-receiving surface. The intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are sequentially stacked on the first surface 111 and the side surface 113, and the tunneling layer 140 and the doped polysilicon layer 150 are sequentially stacked on the second surface 112. The antireflection layer 190 is disposed on the doped polysilicon layer 150 and extends to the side surface 113.

[0052] The third transparent conductive layer 250 is disposed opposite to the antireflection layer 190 on the silicon substrate 110 and extends to the side surface 113. Specifically, the third transparent conductive layer 250 is disposed on the doped semiconductor layer 130. The intrinsic amorphous silicon layer 120 and the doped semiconductor layer 130 are sequentially stacked on the side surface 113. The third transparent conductive layer 250 is in contact with the doped semiconductor layer 130 located on the side surface 113. The antireflection layer 190 is in contact with the third transparent conductive layer 250 located on the side surface 113.

[0053] The antireflection layer 190 may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0054] It should be noted that in some other embodiments, the first surface 111 is a light-receiving surface. The antireflection layer 190 is disposed on the doped semiconductor layer 130 and extends to the side surface 113. The third transparent conductive layer 250 is disposed on the other side opposite to the antireflection layer 190.

[0055] The third transparent conductive layer 250 may include one or more of zinc oxide, indium oxide, and tin oxide. The third transparent conductive layer 250 may contain one or more of gallium, tin, cesium, molybdenum, fluorine, tungsten, and aluminum. The thickness of the first transparent conductive layer 160 is equal to or greater than 10 nm and less than or equal to 200 nm. For example, the thickness is 10 nm, 50 nm, 90 nm, 130 nm, 170 nm, or 200 nm.

[0056] The isolation groove 180 is located at the edge of the silicon substrate 110 and penetrates through the third transparent conductive layer 250. In one embodiment, the isolation groove 180 is located on the side surface 113 and penetrates through the third transparent conductive layer 250 located on the side surface 113. In some other embodiments, the isolation groove 180 may be disposed at the edge of the silicon substrate 110 and on the side surface 113 at the same time, and the isolation groove 180 penetrates through the third transparent conductive layer 250.

[0057] Reference Figure 7 As shown, in one embodiment, the solar cell further includes a first electrode 230 and a second electrode 240. The first electrode 230 penetrates through the antireflection layer 190 and is in contact with the doped polysilicon layer 150. It can be understood that if the antireflection layer 190 is disposed on the doped semiconductor layer 130, the electrode penetrates through the antireflection layer 190 and is in contact with the doped semiconductor layer 130.

[0058] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation to this application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are proposed in this application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of this application.

[0059] Meanwhile, this application uses specific terms to describe the embodiments of this application. Such as "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application can be appropriately combined.

[0060] Similarly, it should be noted that, in order to simplify the expression of this application disclosure and thus help the understanding of one or more application embodiments, in the previous description of the embodiments of this application, sometimes multiple features are merged into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than those mentioned in the claims. In fact, the features of the embodiments are less than all the features of the individual embodiments disclosed above.

[0061] In some embodiments, numbers describing the components and attribute quantities are used. It should be understood that such numbers used for the description of embodiments are, in some examples, modified by the modifiers "about", "approximate", or "substantially". Unless otherwise stated, "about", "approximate", or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and such approximate values can change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used in some embodiments of this application to confirm the breadth of their scope are approximate values, in specific embodiments, the setting of such numerical values is as precise as possible within the feasible range.

[0062] Although this application has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, as long as the changes and variations of the above embodiments are within the scope of the spirit of this application, they will fall within the scope of the claims of this application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate (110) having a first surface (111) and a second surface (112) opposite to each other; An intrinsic amorphous silicon layer (120) and a doped semiconductor layer (130) are sequentially stacked on the first surface (111) and the side surface (113) of the silicon substrate (110); A tunneling layer (140) and a doped polysilicon layer (150) are sequentially stacked on the second surface (112), and the doping type of the doped polysilicon layer (150) is opposite to the doping type of the doped semiconductor layer (130); a first transparent conductive layer (160) disposed on the doped semiconductor layer (130) located on the first surface (111), a second transparent conductive layer (170) disposed on the doped polysilicon layer (150) and extending to the side surface (113) of the silicon substrate, wherein the first transparent conductive layer (160) is further disposed on the doped semiconductor located on the side surface (113) of the silicon substrate or on the second transparent conductive layer (170) located on the side surface of the silicon substrate; and An isolation groove (180) is located at the edge of the silicon substrate (110) and penetrates the first transparent conductive layer (160) and / or the second transparent conductive layer (170), and / or the isolation groove (180) is located on the side surface (113) of the silicon substrate and penetrates the first transparent conductive layer (160) and the second transparent conductive layer (170).

2. The solar cell according to claim 1, wherein: The first surface (111) is a light-facing surface, and the second surface (112) is a backlight surface, or the first surface (111) is a backlight surface, and the second surface (112) is a light-facing surface.

3. The solar cell according to claim 2, characterized in that It also includes an anti-reflection layer (190) which is arranged on the transparent conductive layer located on the light-facing surface and the side surface of the silicon substrate, wherein the anti-reflection layer includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

4. The solar cell according to claim 1, wherein: The invention also includes a plurality of electrodes, wherein the plurality of electrodes are in contact with corresponding transparent conductive layers.

5. A solar cell, characterized in that: include: A silicon substrate (110) having a first surface (111) and a second surface (112) opposite to each other; An intrinsic amorphous silicon layer (120) and a doped semiconductor layer (130) are sequentially stacked on the first surface (111) and the side surface (113) of the silicon substrate (110); A tunneling layer (140) and a doped polysilicon layer (150) are sequentially stacked on the second surface (112), and the doping type of the doped polysilicon layer (150) is opposite to the doping type of the doped semiconductor layer (130); an anti-reflection layer (190), arranged on the doped semiconductor layer (130) or the doped polysilicon layer (150) and extending to the side surface (113) of the silicon substrate, the anti-reflection layer (190) being located on the light-receiving surface of the silicon substrate; a third transparent conductive layer (250), disposed on the silicon substrate (110) opposite to the anti-reflection layer (190) and extending to a side surface (113) of the silicon substrate; and The isolation groove (180) is located at the edge of the silicon substrate (110) and penetrates the third transparent conductive layer (250), and / or the isolation groove (180) is located on the side surface (113) of the silicon substrate and penetrates the third transparent conductive layer (250).

6. The solar cell according to claim 5, characterized in that It also includes a plurality of electrodes, which penetrate the anti-reflection layer and contact the doped semiconductor layer (130) or the doped polysilicon layer (150).

7. The solar cell according to claim 5, characterized in that The width of the isolation groove (180) is greater than 5 μm and less than 5000 μm, and the distance between the isolation groove (180) and the outermost side of the solar cell is less than 15 mm.

8. The solar cell according to claim 5, characterized in that The anti-reflection layer includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

9. The solar cell according to claim 1 or 5, characterized in that: The intrinsic amorphous silicon layer (120) contains any one of oxygen, carbon and nitrogen.

10. The solar cell according to claim 1 or 5, characterized in that: The doped semiconductor layer (130) includes amorphous silicon and / or microcrystalline silicon.

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