Semiconductor device

Abstract

Semiconductor devices are provided herein. In one embodiment, a method is disclosed. A semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer on a first side of the first core substrate, a second redistribution layer on a second side of the first core substrate opposite the first side, a first resin film over the second redistribution layer, and a second resin film over the second redistribution layer. A second semiconductor component embedded in the second core substrate, a third redistribution layer on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer on a fourth side of the second core substrate opposite to the third side, and a via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to the packaging of semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layer materials over a semiconductor substrate and using lithography to pattern the multiple material layers to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. The integrated circuits are separated along scribe lines to isolate individual dies. The individual dies are then separately packaged in a multi-chip module or other types of packaging.

[0003] Due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, or the like), the semiconductor industry has experienced rapid growth. In most cases, such integration density improvements come from repeatedly reducing the minimum feature size, enabling more components to be integrated in a given area. With the increasing requirements for miniaturization, higher speed, greater bandwidth, lower power consumption, and lower latency, smaller and more innovative semiconductor die packaging technologies are needed.

[0004] As semiconductor technology advances further, stacked semiconductor devices such as three dimensional integrated circuits (3DICs) emerge as an effective alternative to further reduce the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be mounted or stacked on top of one another, thereby further reducing the form factor of the semiconductor device. A package-on-package (POP) device is a type of three dimensional integrated circuit in which dies are packaged and then packaged together with another packaged die (or multiple dies). A chip-on-package (COP) device is another type of three dimensional integrated circuit in which dies are packaged and then packaged together with another die (or multiple dies). Summary of the Utility Model

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer located on a first side of the first core substrate, a second redistribution layer located on a second side of the first core substrate opposite the first side, a first resin film located above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer located on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer located on a fourth side of the second core substrate opposite the third side, and a via hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer located on a first side of the first core substrate, a second redistribution layer located on a second side of the first core substrate opposite the first side, a first resin film located above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer located on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer located on a fourth side of the second core substrate opposite the third side, and a first via hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, wherein the first via hole is electrically coupled to the first semiconductor component. The semiconductor device further includes a second resin film located above the fourth redistribution layer, a third semiconductor component embedded in a third core substrate, a fifth redistribution layer located on a fifth side of the third core substrate and bonded to the fourth redistribution layer through the second resin film, a sixth redistribution layer located on a sixth side of the third core substrate opposite the fifth side, and a second via hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate, and the sixth redistribution layer, wherein the second via hole is electrically coupled to the second semiconductor component.

[0007] According to some embodiments of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer located on a first side of the first core substrate and including a plurality of first conductive features, a second redistribution layer located on a second side of the first core substrate opposite to the first side, a first resin film located above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer located on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side and including a plurality of second conductive features, and a plurality of through holes extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer, wherein the first conductive features electrically couple the first semiconductor component to one of the through holes, and the second conductive features electrically couple the second semiconductor component to one of the through holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that the various features are not drawn to scale according to standard methods in the industry. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figures 1 to 9 Cross-sectional views illustrating a plurality of steps of forming a first substrate layer according to some embodiments;

[0010] Figures 10 to 13 Cross-sectional views illustrating a plurality of steps of forming a multi-core substrate according to some embodiments;

[0011] Figures 14 to 16 Cross-sectional views illustrating a plurality of steps of forming a second through hole according to some embodiments;

[0012] Figures 17 to 19 Cross-sectional views illustrating a plurality of steps of forming a redistribution structure above a multi-core substrate according to some embodiments;

[0013] Figure 20 Cross-sectional views illustrating attaching a multi-core substrate to a package substrate and attaching a semiconductor device to the multi-core substrate according to some embodiments.

[0014] SYMBOL DESCRIPTION

[0015] 100: First core substrate

[0016] 101: First opening

[0017] 103: First central core

[0018] 105: First conductive layer

[0019] 150: Surface preparation process

[0020] 201: Film tape

[0021] 300: First semiconductor component

[0022] 401: First conductive trace

[0023] 403: First via hole

[0024] 501: First dielectric layer

[0025] 601: Second conductive trace

[0026] 701: Second dielectric layer

[0027] 801: Second opening

[0028] 803: Third opening

[0029] 900: First substrate layer

[0030] 901: First metallization pattern

[0031] 903: Second metallization pattern

[0032] 1001: First resin film

[0033] 1100: Second substrate layer

[0034] 1101: Second semiconductor component

[0035] 1103: Third semiconductor component

[0036] 1105: Second core substrate

[0037] 1150: Additional process

[0038] 1200: Third substrate layer

[0039] 1201: Second resin film

[0040] 1203: Third core substrate

[0041] 1205: Fourth semiconductor component

[0042] 1300: Multi-core substrate

[0043] 1301: Third dielectric layer

[0044] 1303: Fourth dielectric layer

[0045] 1401: Fourth opening

[0046] 1403: Second conductive layer

[0047] 1450: Surface preparation process

[0048] 1501: Filling material

[0049] 1600: Second via hole

[0050] 1601: Planarization process

[0051] 1701: Third metallization pattern

[0052] 1703: Fourth metallization pattern

[0053] 1801: First redistribution layer

[0054] 1803: Second redistribution layer

[0055] 1805: Fifth dielectric layer

[0056] 1807: Fifth metallization pattern

[0057] 1809: Sixth dielectric layer

[0058] 1811: Sixth metallization pattern

[0059] 1901: First redistribution structure

[0060] 1903: Second redistribution structure

[0061] 1905: Third redistribution layer

[0062] 1907: Seventh dielectric layer

[0063] 1909: Seventh metallization pattern

[0064] 1911: Fourth redistribution layer

[0065] 1913: Eighth dielectric layer

[0066] 1915: Eighth metallization pattern

[0067] 1917: Ninth dielectric layer

[0068] 1919: Tenth dielectric layer

[0069] 1925: First external connector

[0070] 1950: Second external connector

[0071] 1951: Bump underfill metal

[0072] 1953: First conductive connector

[0073] 2000: Package substrate

[0074] 2001: First bonding pad

[0075] 2003: Passivation layer

[0076] 2005: Underfill material

[0077] 2050: Semiconductor device

[0078] 2051: Second bonding pad

[0079] 2052: Substrate

[0080] 2054: Third bonding pad

[0081] 2058: Conductive via

[0082] 2060: Stacked die

[0083] 2060A: Die

[0084] 2060B: Die

[0085] 2062: Bonding wire

[0086] 2064: Encapsulant material

[0087] 2070: Die shadow

[0088] TH1: First thickness

[0089] TH2: Second thickness

[0090] TH3: Third thickness

[0091] TH4: Fourth thickness

[0092] W1: First width

[0093] W2: Second width

[0094] W3: Third width Detailed implementation manner

[0095] To implement different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. The following describes specific examples of components, configurations, etc. to simplify the present disclosure. Of course, these are merely examples and not restrictive. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features are formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0096] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0097] Embodiments discussed herein may be discussed in terms of a specific context, namely a packaged component having one or more integrated circuit dies. In some embodiments, the packaged component is a system-on-integrated-substrate (SoIS) package. The packaged component includes an integrated substrate having a plurality of core substrates, wherein the core substrates have embedded components. The core substrates are bonded to each other and may include redistribution structures. The integrated substrate having a plurality of core substrates can densely integrate semiconductor components within the integrated substrate. The embedded semiconductor components within the plurality of core substrates of the integrated substrate increase the communication bandwidth across the integrated substrate while maintaining low contact resistance and high reliability.

[0098] Figures 1 to 9 A cross-sectional view showing a plurality of steps of forming a first substrate layer 900 (see Figure 9 ). In one embodiment, the first substrate layer 900 includes embedding semiconductor components into the core substrate, forming vias through the core substrate, forming dielectric layers on opposite sides of the core substrate, and forming metallization patterns on opposite sides of the core substrate. In one embodiment, the plurality of steps of forming the first substrate layer 900 may be repeated to form a second substrate layer 1100 (see Figure 11 ), a third substrate layer 1200 (see Figure 12 ), and the like that can be subsequently bonded.

[0099] Figure 1 A cross-sectional view of a first core substrate 100 having a first opening 101 is illustrated according to some embodiments. In some embodiments, the first core substrate 100 includes a first central core 103 having first conductive layers 105 on both sides. In some embodiments, the first core substrate 100 is a double-sided copper-clad laminate (CCL). The first central core 103 may be an organic substrate, a ceramic substrate, a pre-impregnated composite fiber (prepreg), an Ajinomoto build-up film (ABF), paper, fiberglass, non-woven fiberglass, other insulating materials, or a combination of the above. The first conductive layer 105 may be one or more layers of copper, nickel, aluminum, other conductive materials, or a combination of the above laminated or formed on opposite sides of the first central core 103.

[0100] Figure 1 The formation of the first opening 101 on the first core substrate 100 is further illustrated. In some embodiments, the first opening 101 is formed by laser drilling. Other processes such as mechanical drilling, etching, or the like may also be used. The first opening 101 may have a rectangular, circular, or other shape in a top view.

[0101] Subsequent to the formation of the first opening 101, a surface preparation process 150 may be performed. The surface preparation process 150 may include cleaning the exposed surfaces of the first core substrate 100 (e.g., the surfaces of the first conductive layer 105 and the first central core 103 in the first opening 101) using one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralizing alkaline solution, rinse water, or the like) to remove or reduce dirt, oil, and / or native oxide films. A desmear process may be performed to clean the areas adjacent to the first opening 101, where these areas may be contaminated with the material of the first central core 103 removed during the formation of the first opening 101. The desmear may be mechanical desmear (e.g., using fine abrasive blasting in a wet slurry), chemical desmear (e.g., using a combination of organic solvents, permanganate, or the like for rinsing), or a combination of mechanical and chemical desmear. After cleaning, treatment with a chemical conditioner may be performed, where the chemical conditioner promotes the adsorption of an activator used during subsequent electroless plating. In some embodiments, the conditioning step may be followed by micro-etching the first conductive layer 105 to slightly roughen the conductive surface of the first conductive layer 105, thereby better bonding the first conductive layer 105 and the conductive material deposited later.

[0102] According to some embodiments, the first core substrate 100 is formed to a first thickness TH1, which facilitates embedding a semiconductor component into the first core substrate 100 (e.g., the first semiconductor component 300, see Figure 3 ). The first thickness TH1 can be in the range of 50 μm to 1400 μm. If the first core substrate 100 is formed with a thickness greater than the first thickness TH1, too large a gap may appear between the semiconductor component to be embedded in the first core substrate 100 and the subsequently formed conductive features (e.g., the first conductive trace 401, see Figure 4 ). If the first core substrate 100 is formed with a thickness less than the first thickness TH1, the first core substrate 100 may be too thin to accommodate the semiconductor component to be embedded in the first core substrate 100, and the semiconductor component may protrude too much outside the first core substrate 100 to interfere with the formation of the subsequently formed conductive features (e.g., the first conductive trace 401, see Figure 4 ). In addition, according to some embodiments, the first opening may be formed with various widths. One or more first openings 101 can be formed to a first width W1, which facilitates embedding a semiconductor component into the first core substrate 100 (e.g., the first semiconductor component 300, see Figure 3 ). The first width W1 can be greater than the width of the first semiconductor component 300 by 50 μm to 500 μm. If the first width W1 is greater than the width of the first semiconductor component 300 by too much more than 500 μm, the semiconductor component may be difficult to be sufficiently fixed in the first core substrate 100. If the width of the first opening 101 is formed less than the first width W1, the first opening 101 may be too small to accommodate the semiconductor component to be embedded in the first core substrate 100, and the semiconductor component may be too small to conform to the first opening 101. Additionally, one or more first openings 101 can be formed to a second width W2, which facilitates forming a conductive material (e.g., the first via 403, see Figure 4 ) in the first opening 101. The second width W2 can be in the range of 50 μm to 1400 μm. In one embodiment, the first opening 101 can be formed to the second width W2, so as to form a plating through hole via (PTH) (e.g., the first via 403) to connect the metallization pattern on the front side of the first core substrate 100 to the metallization pattern on the back side.

[0103] Figure 2 A cross-sectional view showing the attachment of the film tape 201 to the first side of the first core substrate 100 is shown. The film tape 201 can be used to facilitate the embedding of a semiconductor component (e.g., the first semiconductor component 300, see Figure 3)One of them is placed inside one of the first openings 101 having a first width W1. In one embodiment, the film tape 201 can be a polymer film, such as a polyimide film. The polyimide film can be used to provide structural support and provide a sufficient placement substrate for semiconductor components to be buried in the first openings 101 of the first core substrate 100. However, any suitable film tape 201 can be used, such as an ultraviolet tape that may lose adhesiveness when exposed to ultraviolet light, a pressure-sensitive tape, a radiation-curable tape, a combination of the above, or the like.

[0104] Figure 3 The cross-sectional view shows that the first semiconductor component 300 is buried in one of the first openings 101 having a first width W1 of the first core substrate 100. According to some embodiments, the first semiconductor component 300 can be an active component, such as a transistor or the like. In some embodiments, the semiconductor component can be a passive component, such as a capacitor, an inductor, a resistor, the like, or a combination of the above. The first semiconductor component 300 can be a semiconductor die, an integrated passive device (IPD), an active wafer, an integrated voltage regulator (IVR), a multilayer ceramic capacitor (MLCC), or the like. The first semiconductor component 300 can be placed on the surface of the film tape 201 exposed in the first opening 101, and the first semiconductor component 300 is buried in one of the first openings 101 having a first width W1. In some embodiments, a pick-and-place process can be used to place the first semiconductor component 300 on the exposed surface of the film tape 201 in the first opening 101. However, any suitable process can be used to place the first semiconductor component 300 on the exposed surface of the film tape 201 in the first opening 101. In some embodiments, once the first semiconductor component 300 is placed in the first core substrate 100, the first semiconductor component 300 can be fixed in the first opening 101 by a dielectric material.

[0105] Figure 4A cross-sectional view showing the formation of the first through-hole 403 in the first core substrate 100 and the first conductive trace 401 on one side of the first core substrate 100 relative to the film tape 201. In one embodiment, the first opening 101 not occupied by the first semiconductor component 300 may be filled to form the first through-hole 403, and the first conductive trace 401 is formed on one side of the first core substrate 100 relative to the film tape 201 and above the first through-hole 403, the first core substrate 100, and the first semiconductor component 300 buried in the first core substrate 100. In one embodiment, the formation of the first through-hole 403 and the first conductive trace 401 may be achieved by forming a seed layer (not specifically shown) above the first core substrate 100. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The formation of the seed layer may use, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. Then, a photoresist (not specifically shown) is formed and patterned on the seed layer. The formation of the photoresist may be by spin coating or the like, exposure to a patterned light source or other patterning energy source, and exposure to a developer to remove the exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the first conductive trace 401. The patterning step forms an opening through the photoresist to expose the seed layer. A conductive material (not specifically shown) is formed in the opening of the photoresist and on the exposed portion of the seed layer. The formation of the conductive material may be by electroplating, such as electroplating with electricity, electroless plating, or the like. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The removal of the photoresist may be by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer and the conductive material form the first through-hole 403 and the first conductive trace 401.

[0106] After the formation of the first conductive trace 401 and the first through-hole 403, the patterned mask layer (such as the photoresist) may be stripped. In some embodiments, a suitable etching process may be used to remove a portion of the first conductive layer 105 covered by the patterned mask layer. Removing the unwanted portion of the first conductive layer 105 can avoid an unwanted electrical short between the conductive features formed in the areas exposed by the patterned mask layer.

[0107] Figure 5A cross-sectional view showing the formation of a first dielectric layer 501 over an exposed surface of a first core substrate 100 and a first conductive trace 401. In some embodiments, the first dielectric layer 501 comprises a dielectric material such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. In some embodiments, the first dielectric layer 501 may be formed of a polymer, where the polymer may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, and may be patterned using a photomask. The formation of the first dielectric layer 501 may be by coating, lamination, chemical vapor deposition, the like, or a combination of the above. However, any suitable forming material or method may be used to form the first dielectric layer 501. Additionally, in some embodiments, a planarization process is performed to form a planar outer surface of the first dielectric layer 501.

[0108] Figure 6 A cross-sectional view showing the removal of the film tape 201 and the formation of a second conductive trace 601 over an exposed surface of the first core substrate 100 and a first semiconductor component 300 embedded in the first core substrate 100. In one embodiment, the first core substrate 100 is flipped, and the film tape 201 is removed. In one embodiment, the removal of the film tape 201 may be by a mechanical process such as a grinding process, a chemical process such as etching, or a combination of the above, such as chemical mechanical polish (CMP). However, any suitable method may be used to remove the film tape 201. Once the film tape 201 is removed, the second conductive trace 601 may be formed and patterned in a manner similar to that of forming the first conductive trace 401 described above. However, any suitable method or material may be used to form the second conductive trace 601. Additionally, Figure 6 A cross-sectional view showing that a first semiconductor component 300 has contact pads (e.g., a first conductive trace 401 and a second conductive trace 601) formed on both sides of the first semiconductor component 300, resulting in the first semiconductor component 300 having dual-sided pads, but this is only an illustrative example. In one embodiment, either the second conductive trace 601 or the first conductive trace 401 may serve as a contact pad for the first semiconductor component 300, such that the first semiconductor component 300 has a single-sided pad.

[0109] Figure 7A cross-sectional view showing the formation of a second dielectric layer 701 over the exposed surface of the first core substrate 100 and the second conductive trace 601. In some embodiments, the second dielectric layer 701 may be formed using a manner and materials similar to those for forming the first dielectric layer 501 described above. However, any suitable method or materials may be used to form the second dielectric layer 701.

[0110] Figure 8 A cross-sectional view showing the formation of a second opening 801 in the second dielectric layer 701 and a third opening 803 in the first dielectric layer 501. In some embodiments, the second opening 801 and the third opening 803 may be formed by a laser drilling process into the corresponding dielectric layer (the second dielectric layer 701 or the first dielectric layer 501). In some embodiments, the second opening 801 and the third opening 803 may be formed by etching the first dielectric layer 501 and the second dielectric layer 701 using a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask. In some embodiments where either the first dielectric layer 501 or the second dielectric layer 701 is formed of a photosensitive material, the first dielectric layer 501 or the second dielectric layer 701 may be exposed to form the second opening 801 and the third opening 803 in the corresponding dielectric layer. Forming the second opening 801 may expose a portion of the first conductive trace 401, and forming the third opening 803 may expose a portion of the second conductive trace 601. However, any suitable process may be used to form the second opening 801 and the third opening 803 in the corresponding dielectric layer (the second dielectric layer 701, the first dielectric layer 501). Although not shown, forming the second opening 801 and the third opening 803 may include multiple flipping steps and steps of placing the structure on a tape or a carrier.

[0111] Figure 9 A cross-sectional view showing the formation of a first metallization pattern 901 in the second opening 801 and over the second dielectric layer 701, and a second metallization pattern 903 in the third opening 803 and over the first dielectric layer 501. In one embodiment, the first metallization pattern 901 may be formed in a manner and materials similar to those of the first conductive trace 401 described above. The first metallization pattern 901 includes a conductive trace formed along the top surface of the second dielectric layer 701 and a conductive via passing through the second dielectric layer 701 in the second opening 801. The via electrically and physically connects the conductive trace of the first metallization pattern 901 to a metal pattern (e.g., the second conductive trace 601) directly below the second dielectric layer 701. In some embodiments, the conductive via of the first metallization pattern 901 may be a blind via electrically connected to the first semiconductor component 300. However, any suitable process and materials may be used to form the first metallization pattern 901.

[0112] In addition, the formation of the second metallization pattern 903 can be in a manner and with materials similar to those of the first metallization pattern 901 described above, where the second metallization pattern 903 is formed in the third opening 803 and above the first dielectric layer 501. However, any suitable process and materials can be used to form the second metallization pattern 903. It should be noted that the structures discussed are formed on both sides of the first core substrate 100, which can be by using a support substrate, an adhesion film, or the like (not shown), and subsequent structures herein can be formed in a similar manner.

[0113] The method of forming the first dielectric layer 501, the second dielectric layer 701, the conductive traces and vias of the first metallization pattern 901, and the conductive traces and vias of the second metallization pattern 903 is an example. It should be understood that the processes for forming these dielectric layers and metallization patterns can vary based on the specific design (e.g., the desired pattern minimum size). For example, in some embodiments, damascene processes (e.g., single damascene process or dual damascene process) can be used. In addition, the first core substrate 100 in which the first semiconductor component 300 is buried, and the first dielectric layer 501, the second dielectric layer 701, the first metallization pattern 901, and the second metallization pattern 903 can be collectively referred to as the first substrate layer 900.

[0114] Figures 10 to 13 Illustrated are cross-sectional views of multiple steps for forming the multi-core substrate 1300 (see Figure 11 ) by attaching the first substrate layer 900 to the second substrate layer 1100 (see Figure 12 ) and attaching the second substrate layer 1100 to the third substrate layer 1200 (see Figure 13 ). In one embodiment, a material layer contacts a resin film (e.g., the first resin film 1001, see Figure 10 ), and then the resin film is cured such that the resin film cures to attach the substrate layers to one another, thereby enabling the multiple substrate layers for forming the multi-core substrate 1300 to be attached to each other.

[0115] Figure 10A cross-sectional view showing the formation of a first resin film 1001 over an exposed surface of a second dielectric layer 701 and a first metallization pattern 901. In one embodiment, the first resin film 1001 can be a polymer resin film, an epoxy resin film, a dielectric material, or the like. In one embodiment, the first resin film 1001 can be applied using a process, such as a spin coating process, a dip coating method, an air-knife coating method, a curtain coating method, a wire-bar coating method, a gravure coating method, a lamination method, an extrusion coating method, a combination of the above, or the like. In one embodiment, the first resin film 1001 can be applied in a liquid or semi-liquid form and then cured. However, any suitable material and method can be used to form the first resin film 1001. The first resin film 1001 can be formed to a second thickness TH2. In one embodiment, the second thickness TH2 can be in the range of 50 μm to 1400 μm. If the thickness of the first resin film 1001 formed is less than the second thickness TH2, subsequent bonding of a structure (such as a second substrate layer 1100, see Figure 11 ) to the first resin film 1001 may be insufficient. If the thickness of the first resin film 1001 formed is greater than the second thickness TH2, the first resin film 1001 may be difficult to fully cure during subsequent bonding processes.

[0116] Figure 11 A cross-sectional view showing the attachment of a first substrate layer 900 and a second substrate layer 1100. In one embodiment, the second substrate layer 1100 can be formed in a manner similar to that of the first substrate layer 900 described above. Additionally, the second substrate layer 1100 is shown having two semiconductor components (a second semiconductor component 1101 and a third semiconductor component 1103) embedded in a second core substrate 1105, however this is merely an illustrative example and any number of semiconductor components can be embedded in the respective core substrates of multiple substrate layers (e.g., the first substrate layer 900 and the second substrate layer 1100). Further, the second core substrate 1105 can be formed to a third thickness TH3 to facilitate the embedding of the second semiconductor component 1101 and the third semiconductor component 1103. The third thickness TH3 has the same range as the first thickness TH1. In one embodiment, the third thickness TH3 can be less than the first thickness TH1. In one embodiment, the third thickness TH3 can be greater than the first thickness TH1.

[0117] In addition, in one embodiment, the second substrate layer 1100 is attached to the first substrate layer 900 by an additional process 1150. In one embodiment, the additional process 1150 uses a first resin film 1001 to bring the bottom surface of the second substrate layer into contact with the top surface of the first resin film 1001 to attach the second substrate layer 1100 to the first substrate layer 900. The first resin film 1001 can then be cured so that the material of the first resin film 1001 hardens to attach the first substrate layer 900 to the second substrate layer 1100. In one embodiment, the additional process 1150 can be a furnace curing process, in which a structure having the second substrate layer 1100 above the first resin film 1001 is placed in a furnace and surrounded by an inert environment. In one embodiment, the inert environment can be, for example, argon, neon, or a similar inert gas, or it can be an environment that is non-reactive to the exposed surfaces. Once the structure is placed in the furnace, the furnace uses heating elements to heat the inert environment, thereby raising the temperature of the first resin film 1001 and other structures.

[0118] In one embodiment, the additional process 1150 can raise the temperature to a curing temperature range of 40°C to 350°C. If the temperature rises above the first temperature range, the first resin film 1001 and other structures may be damaged. If the temperature is below the first temperature range, the first resin film 1001 may be difficult to cure sufficiently to attach the first substrate layer 900 to the second substrate layer 1100. Additionally, the additional process 1150 can be performed for a sufficient duration to ensure that the first resin film 1001 is cured sufficiently to attach the first core substrate 100 to the second substrate layer 1100 without damaging the first resin film 1001, the first core substrate 100, or the second substrate layer 1100.

[0119] Furthermore, the furnace curing process is one example of the above-described additional process 1150, but this is merely an example and is not intended to be limiting in any way. Rather, any suitable additional process can be used, such as rapid thermal cure, flash annealing, laser annealing, a combination of the above, or the like. Any suitable curing method can be used, and all such methods are encompassed within the scope of the embodiments.

[0120] Figure 12 A cross-sectional view is shown of attaching a third substrate layer 1200 to the second substrate layer 1100 after forming a second resin film 1201 above the second substrate layer 1100. In one embodiment, the second resin film 1201 can be formed of a material similar to the above-described first resin film 1001 and can be formed above the second substrate layer 1100 in a manner similar to the first resin film 1001 that forms the first substrate layer 900. However, any suitable material and method can be used to form the second resin film 1201.

[0121] In addition, forming the third substrate layer 1200 can be similar to the manner of forming the first substrate layer 900 and the second substrate layer 1100 described above. Moreover, the third substrate layer 1200 can have any number of semiconductor components embedded in the corresponding core substrate. Additionally, the third core substrate 1203 of the third substrate layer 1200 can be formed to a fourth thickness TH4, which is conducive to embedding the fourth semiconductor component 1205. The fourth thickness TH4 has the same thickness range as the first thickness TH1. In one embodiment, the fourth thickness TH4 can be the same as or different from the first thickness TH1 or the third thickness TH3.

[0122] Furthermore, in one embodiment, attaching the third substrate layer 1200 to the second substrate layer 1100 can be similar to the manner of attaching the first substrate layer 900 to the second substrate layer 1100 described above. For example, after placing the third substrate layer on the second resin film 1201, the second resin film 1201 can be cured in a manner similar to curing the first resin film 1001. After attaching the third substrate layer 1200 to the second substrate layer 1100, the formed structure can be referred to as a multi-core substrate 1300 (shown in Figure 13 ). It is worth mentioning that Figures 10 to 12 illustrates the formation of a multi-core substrate 1300 including three independent substrate layers, where the substrate layers have core substrates with embedded semiconductor components, but this is only an example and any number of substrate layers with core substrates having embedded semiconductor components can be adhered to form the multi-core substrate 1300.

[0123] Figure 13 illustrates a cross-sectional view of forming a third dielectric layer 1301 and a fourth dielectric layer 1303 on opposite sides of the multi-core substrate 1300. In one embodiment, forming both the third dielectric layer 1301 and the fourth dielectric layer 1303 can be similar to the manner and materials of forming the first dielectric layer 501 described above, where the third dielectric layer 1301 is formed above the exposed side of the first substrate layer 900, and the fourth dielectric layer 1303 is formed above the exposed side of the third substrate layer 1200. However, any suitable materials and processes can be used to form the third dielectric layer 1301 and the fourth dielectric layer 1303.

[0124] Figures 14 to 16 illustrates a cross-sectional view of multiple steps of forming a second via 1600 (see Figure 16 ) through the multi-core substrate 1300. In one embodiment, the second via 1600 is an electroplated via. Additionally, in one embodiment, the second via 1600 is formed at the periphery of a region (such as the die shadow 2070, see Figure 20 ), where multiple semiconductor components are embedded in the regions of the multiple core substrates of the multi-core substrate 1300.

[0125] Figure 14 A cross-sectional view showing an intermediate step of forming a second through hole 1600 (see Figure 16 ). In one embodiment, forming a fourth opening 1401 for the second through hole 1600 may use a drilling process, photolithography, a laser process, or other methods. In one embodiment, the fourth opening 1401 is formed outside the region of the embedded semiconductor component in the multi-core substrate 1300. In one embodiment, the fourth opening 1401 may have a rectangular, circular, or other shape in a top view. In one embodiment, the fourth opening 1401 may be formed to a third width W3 to facilitate forming a conductive material (such as a second conductive layer 1403) in the fourth opening 1401. The third width W3 may be in the range of the second width W2. In some embodiments, the third width W3 may be greater than the second width W2 to form a larger through hole through the multi-core substrate 1300.

[0126] After forming the fourth opening 1401, a second surface preparation process 1450 may be performed. The second surface preparation process 1450 may include cleaning the exposed surface of the multi-core substrate 1300 using one or more cleaning solutions (such as sulfuric acid, chromic acid, a neutralizing alkaline solution, rinsing water, or the like) to remove or reduce dirt, oil, and / or a self-generated oxide film. A degumming process may be performed to clean the area near the fourth opening 1401, where these areas may be contaminated with various materials of the multi-core substrate 1300 removed when forming the fourth opening 1401. Degumming may be mechanical degumming (such as using fine abrasive blasting in a wet slurry), chemical degumming (such as rinsing using a combination of an organic solvent, permanganic acid, or the like), or a combination of mechanical and chemical degumming. After cleaning, treatment may be performed using a chemical conditioner, where the chemical conditioner promotes the adsorption of an activator used during subsequent electroless plating.

[0127] After forming the fourth opening 1401 through the multi-core substrate 1300, the exposed surface of the multi-core substrate 1300 including the sidewalls of the fourth opening 1401 is lined with a second conductive layer 1403. In one embodiment, the second conductive layer 1403 may include a conductive material such as copper, a copper alloy, or other conductors, and may include a barrier layer (not particularly shown), a liner layer (not particularly shown), and a seed layer (not particularly shown). In one embodiment, the second conductive layer 1403 may be partially formed using a metal electroless plating technique. However, any suitable materials and methods may be used to form the second conductive layer 1403. It is worth mentioning that the second conductive layer 1403 is shown as completely covering the top and bottom surfaces of the multi-core substrate 1300, but this is only an example and forming the second conductive layer 1403 may include forming a patterned mask layer (not particularly shown) and selectively depositing a conductive material.

[0128] Figure 15A cross-sectional view showing the formation of the filling material 1501 for the second through-hole 1600 is presented. In some embodiments, the second through-hole 1600 is a hollow conductive through-hole, where the center of the hollow conductive through-hole is filled with the filling material 1501 of insulating material. In other embodiments, the filling material 1501 can be a conductive material, such as copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, or other conductors. The filling material 1501 can be electroplated or deposited above the second conductive layer 1403. In one embodiment, the filling material 1501 can be overfilled on either or both sides of the multi-core substrate 1300. However, any suitable material and formation method can be used to form the filling material 1501 above the second conductive layer 1403 in the fourth opening 1401.

[0129] Figure 16 A cross-sectional view showing the formation of the second through-hole 1600 after the planarization process 1601 is presented. In one embodiment, the overfilled portion of the filling material 1501 (and if present, a portion of the second conductive layer 1403 along the outer surface of the outer dielectric layer of the multi-core substrate 1300) can be removed by the planarization process. In one embodiment, the planarization process 1601 causes the opposite surfaces of the second through-hole 1600 to be coplanar with the dielectric layers (the third dielectric layer 1301 and the fourth dielectric layer 1303) of the multi-core substrate 1300. The planarization process 1601 can be, for example, a chemical mechanical polishing process, a grinding process, an etching process, the like, or a combination of the above. However, any suitable planarization process can be used to form the second through-hole 1600.

[0130] The second through-hole 1600 provides a vertical electrical connection from one side of the multi-core substrate 1300 to the other side of the multi-core substrate 1300 and a vertical electrical connection between multiple substrate layers (e.g., the first substrate layer 900, the second substrate layer 1100, the third substrate layer 1200, or the like), where semiconductor components (e.g., the first semiconductor component 300, the second semiconductor component 1101, the third semiconductor component 1103, the fourth semiconductor component 1205, or the like) are buried in multiple core substrates of the substrate layers (e.g., the first core substrate 100, the second core substrate 1105, the third core substrate 1203, or the like). For example, some second through-holes 1600 are coupled between conductive features (e.g., the first redistribution structure 1901, see Figure 19 ) on one side of the multi-core substrate 1300 and conductive features (e.g., the second redistribution structure 1903, see Figure 19 ) on the opposite side of the multi-core substrate 1300. It is worth mentioning that two second through-holes 1600 are shown on either side of the region of the multi-core substrate 1300 containing the buried semiconductor components, but this is only an example and any number of second through-holes 1600 can be formed to provide sufficient connections through and across the multi-core substrate 1300.

[0131] Figure 17 A cross-sectional view showing the formation of a third metallization pattern 1701 and a fourth metallization pattern 1703 on opposite sides of a multi-core substrate 1300. In one embodiment, the formation of the third metallization pattern 1701 and the fourth metallization pattern 1703 may be in a manner and material similar to the second metallization pattern 903. Forming the third metallization pattern 1701 may include forming vias in openings within a third dielectric layer 1301 for forming an electrical connection to the conductive features of the metallization pattern in the first substrate layer 900, and the wires of the third metallization pattern 1701 may be formed over the exposed surfaces of the vias and a second via 1600 for forming an electrical connection to the second via 1600 (e.g., forming an electrical connection through the second conductive layer 1403). Forming the fourth metallization pattern 1703 may include forming vias in openings within a fourth dielectric layer 1303 for forming an electrical connection to the conductive features of the metallization pattern in the third substrate layer 1200, and the wires of the fourth metallization pattern 1703 may be formed over the exposed surfaces of the vias and a second via 1600 for forming an electrical connection to the second via 1600 (e.g., forming an electrical connection through the second conductive layer 1403).

[0132] In some embodiments, Figure 18 the structure of may be used as a probe card in semiconductor device testing, such as a probe card for testing known good die. For example, probe pins or probe needles (not shown) may be formed on Figure 18 one or both sides of the structure of to facilitate device testing. Since multiple components can be embedded in the integrated substrate, the electronic design requirements of the probe card can be met (e.g., different capacitors and inductors in the same integrated substrate). In addition, multiple embedded components (e.g., capacitors) improve the power integrity and signal integrity of the probe card, enabling the probe card to meet the testing requirements of high-end devices.

[0133] Figure 18A cross-sectional view showing the first redistribution layer 1801 above the third metallization pattern 1701 and the second redistribution layer 1803 above the fourth metallization pattern 1703 is shown. In one embodiment, the first redistribution layer 1801 includes a fifth dielectric layer 1805 and a fifth metallization pattern 1807. In some embodiments, the fifth dielectric layer 1805 is formed of a photosensitive material such as polybenzoxazole, polyimide, benzocyclobutene, or the like, and the photosensitive material can be patterned using a photomask. The fifth dielectric layer 1805 can be formed by spin coating, lamination, chemical vapor deposition, the like, or a combination of the above. Then, the fifth dielectric layer 1805 is patterned. Openings are patterned to expose portions of the third metallization pattern 1701. The patterning can be performed by an acceptable process, such as exposing and developing the fifth dielectric layer 1805 when the fifth dielectric layer 1805 is a photosensitive material, or an etching process such as anisotropic etching.

[0134] Then, the fifth metallization pattern 1807 can be used. The fifth metallization pattern 1807 can include conductive elements that extend along the main surface of the fifth dielectric layer 1805 and extend through the fifth dielectric layer 1805 to physically and electrically couple to the third metallization pattern 1701. As an example of forming the fifth metallization pattern 1807, a seed layer (not specifically shown) is formed above the fifth dielectric layer 1805 and in the openings that extend through the fifth dielectric layer 1805. In some embodiments, the seed layer is a metal layer, and the metal layer can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition or the like. Then, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and can be exposed for patterning. The photoresist pattern corresponds to the fifth metallization pattern 1807. Openings are patterned through the photoresist to expose the seed layer. Then, a conductive material is formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material can be formed by electroplating, such as electroplating with or without electricity, or the like. The conductive material can include metals such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying seed layer portions forms the fifth metallization pattern 1807. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as using an acceptable etching process, such as wet or dry etching.

[0135] In one embodiment, the second redistribution layer 1803 may include a sixth dielectric layer 1809 and a sixth metallization pattern 1811. Forming the sixth dielectric layer 1809 may be similar to the material and manner of the above-mentioned fifth dielectric layer 1805, and forming the sixth metallization pattern 1811 may be similar to the manner of the above-mentioned fifth metallization pattern 1807. However, any suitable materials or methods may be used to form both the first redistribution layer 1801 and the second redistribution layer 1803.

[0136] Figure 19 A cross-sectional view showing the formation of the first redistribution structure 1901 and the second redistribution structure 1903. In one embodiment, the first redistribution structure 1901 may include a first redistribution layer 1801 and a third redistribution layer 1905, wherein the third redistribution layer 1905 has a seventh dielectric layer 1907 and a seventh metallization pattern 1909. In one embodiment, the second redistribution structure 1903 may include a second redistribution layer 1803 and a fourth redistribution layer 1911, wherein the fourth redistribution layer 1911 has an eighth dielectric layer 1913 and an eighth metallization pattern 1915. In one embodiment, forming the third redistribution layer 1905 and the fourth redistribution layer 1911 may be similar to the manner and material of the first redistribution layer 1801. Further, it is worth mentioning that each redistribution structure (e.g., the first redistribution structure 1901 and the second redistribution structure 1903) is shown as having two redistribution layers each, but this is merely an example, and any number of redistribution layers may be formed in the redistribution structure.

[0137] In addition, subsequent to forming the first redistribution structure 1901 and the second redistribution structure 1903, a first external connector 1925 electrically connected to the second redistribution structure 1903 is formed, and a second external connector 1950 electrically connected to the first redistribution structure 1901 is formed. In some embodiments, the first external connector 1925 extending through the ninth dielectric layer 1917 is formed to contact the eighth metallization pattern 1915. An opening is formed through the ninth dielectric layer 1917 to expose a portion of the eighth metallization pattern 1915. Forming the opening can be, for example, by using laser drilling, etching, or the like. The first external connector 1925 is formed in the opening. In some embodiments, the first external connector 1925 includes flux and is formed in a flux dipping process. In some embodiments, the first external connector 1925 includes a conductive adhesive, such as solder paste, silver paste, or the like, and the conductive adhesive can be dispensed in a printing process. In some embodiments, the second external connector 1950 includes a formed under bump metallization (UBM) 1951 and a first conductive connector 1953. The under bump metallization 1951 has a bump portion located in the tenth dielectric layer 1919 and extending along the main surface of the tenth dielectric layer 1919, and the under bump metallization 1951 has a via portion extending through the tenth dielectric layer 1919 to physically and electrically couple to the seventh metallization pattern 1909. The under bump metallization 1951 can be formed of the same material as the seventh metallization pattern 1909. In some embodiments, the under bump metallization 1951 has a different size from the metallization pattern (e.g., the seventh metallization pattern 1909). In some embodiments, the first conductive connector 1953 is formed on the under bump metallization 1951. The first conductive connector 1953 can be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, micro bump, bump formed by electroless nickel - electroless palladium - immersion gold technique (ENEPIG), or the like. The first conductive connector 1953 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination of the above. In some embodiments, forming the first conductive connector 1953 can first form a layer of solder by evaporation plating, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder is formed on the structure, reflow can be performed to shape the material into a desired bump shape.In another embodiment, the first conductive connector 1953 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal coating is formed on top of the metal pillars. The metal coating may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination of the foregoing, and may be formed by an electroplating process.

[0138] Figure 20 FIG. shows a cross-sectional view of attaching the multi-core substrate 1300 to the package substrate 2000 and attaching the semiconductor device 2050 to the multi-core substrate 1300. In one embodiment, attaching the multi-core substrate 1300 to the package substrate 2000 may be by bonding the second external connector 1950 to the first bonding pad 2001 of the package substrate. In one embodiment, attaching the semiconductor device 2050 to the multi-core substrate 1300 may be by bonding the first external connector 1925 to the second bonding pad 2051 of the semiconductor device 2050.

[0139] In one embodiment, the package substrate 2000 may be a printed circuit board (PCB) or the like. The package substrate 2000 may include one or more dielectric layers and electrically conductive features, such as traces and vias (not specifically shown). In some embodiments, the package substrate 2000 may include through vias, active devices, passive devices, and the like (not specifically shown). The package substrate 2000 may further include conductive pads (e.g., the first bonding pad 2001) formed on the upper and lower surfaces of the package substrate 2000. In one embodiment, a passivation layer 2003 is formed above the first bonding pad 2001, and an opening may be formed in the passivation layer 2003 to expose the first bonding pad 2001 so that the first conductive connector 1953 can contact the first bonding pad 2001 and perform reflow. Further, in one embodiment, an underfill material 2005 may be formed between the multi-core substrate 1300 and the package substrate 2000. The underfill material 2005 can reduce stress and protect the joints formed by the reflow of the first conductive connector 1953 to the first bonding pad 2001. After attaching the multi-core substrate 1300 and the package substrate 2000, the underfill material 2005 can be formed by a capillary flow process.

[0140] In one embodiment, the semiconductor device 2050 is coupled to the multi-core substrate 1300. The semiconductor device 2050 includes, for example, a substrate 2052 and one or more stacked dies 2060 coupled to the substrate 2052. Although a set of stacked dies 2060 is illustrated, in other embodiments, multiple stacked dies 2060 (each having one or more stacked dies) may be provided side-by-side and coupled to the same surface of the substrate 2052. The substrate 2052 may be formed of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of the foregoing, and the like may also be used. Additionally, the substrate 2052 may be a silicon-on-insulator (SOI) substrate. Generally, a silicon-on-insulator substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, silicon-on-insulator, silicon germanium on insulator (SGOI), or combinations of the foregoing. In an alternative embodiment, the substrate 2052 is based on an insulating core such as a fiberglass-reinforced resin core. One example core material is fiberglass resin such as FR4. Alternative options for the core material include bismaleimide-triazine (BT) resin, or other printed circuit board materials or films. The substrate 2052 may use, for example, Ajinomoto build-up film or other laminated build-up films.

[0141] The substrate 2052 may include active and passive devices (not shown). Many types of devices may be used to generate the design structure and functional requirements of the semiconductor device 2050, such as transistors, capacitors, resistors, combinations of the foregoing, and the like. Any suitable method may be used to form the devices.

[0142] The substrate 2052 may also include a metallization layer (not shown) and conductive vias 2058. The metallization layer may be formed over the active and passive devices and may be designed to connect multiple devices to form a functional circuit. The metallization layer may be formed of alternating layers of a dielectric (such as a low dielectric constant dielectric material) and a conductive material (such as copper) and vias interconnecting the conductive material layers, and the metallization layer may be formed by any suitable process such as deposition, damascene, dual damascene, or the like. In some embodiments, the substrate 2052 substantially does not have active and passive devices.

[0143] The substrate 2052 may have a third bonding pad 2054 on a first side of the substrate 2052 to couple to the stacked die 2060, and a second bonding pad 2051 on a second side of the substrate 2052 to couple to the first external connector 1925, wherein the second side of the substrate 2052 is opposite to the first side of the substrate 2052. In some embodiments, the third bonding pad 2054 and the second bonding pad 2051 are formed by forming grooves (not shown) into a dielectric layer (not shown) on the first side and the second side of the substrate 2052. Forming the grooves may bury the third bonding pad 2054 and the second bonding pad 2051 into the dielectric layer. In other embodiments, the grooves are omitted and the third bonding pad 2054 and the second bonding pad 2051 may be formed on the dielectric layer. In some embodiments, the third bonding pad 2054 and the second bonding pad 2051 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination of the foregoing. The conductive material of the third bonding pad 2054 and the second bonding pad 2051 may be deposited over the thin seed layer. Forming the conductive material may be by an electroplating process, an electroless plating process, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, the like, or a combination of the foregoing. In one embodiment, the conductive material of the third bonding pad 2054 and the second bonding pad 2051 is copper, tungsten, aluminum, silver, gold, the like, or a combination of the foregoing.

[0144] In some embodiments, the third bonding pad 2054 and the second bonding pad 2051 are under bump metals including three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. Other configurations of materials and material layers may be used to form the third bonding pad 2054 and the second bonding pad 2051, such as a chromium / chromium copper alloy / copper / gold configuration, a titanium / titanium tungsten / copper configuration, or a copper / nickel / gold configuration. Any suitable materials or material layers that may be used for the third bonding pad 2054 and the second bonding pad 2051 are within the scope of the present application. In some embodiments, the conductive vias 2058 extend through the substrate 2052 and couple at least one of the third bonding pads 2054 to at least one of the second bonding pads 2051.

[0145] In the illustrated embodiment, the stacked die 2060 is coupled to the substrate 2052 by bonding wires 2062, but other connections such as conductive bumps may be used. In one embodiment, the stacked die 2060 is a stacked memory die. For example, the stacked die 2060 may be a memory die such as a low-power double data rate (LPDDR) memory module, such as an LPDDR1, LPDDR2, LPDDR3, LPDDR4, or a similar memory module.

[0146] The stacked die 2060 and the bonding wires 2062 can be encapsulated by a molding compound 2064. The molding compound 2064 can be molded over the stacked die 2060 and the bonding wires 2062, for example, using compression molding. In some embodiments, the molding compound 2064 is a molding compound, a polymer, an epoxy resin, a silica-filled material, the like, or a combination of the foregoing. A curing process can be performed to cure the molding compound 2064, and the curing process can be heat curing, ultraviolet curing, the like, or a combination of the foregoing.

[0147] In some embodiments, the stacked die 2060 and the bonding wires 2062 are embedded in the molding compound 2064, and after curing the molding compound 2064, a planarization step, such as grinding, is performed to remove the excess portion of the molding compound 2064 and provide a substantially planar surface of the semiconductor device 2050.

[0148] After forming the semiconductor device 2050, the semiconductor device 2050 is mechanically and electrically coupled to the multi-core substrate 1300 via the first external connector 1925 and the second bonding pad 2051. In some embodiments, a solder mask layer (not shown) is formed on a side of the substrate 2052 opposite to the stacked die 2060. The first external connector 1925 can be disposed in an opening of the solder mask layer to be electrically and mechanically coupled to a conductive feature (e.g., the second bonding pad 2051) in the substrate 2052. The solder mask layer can be used to protect areas of the substrate 2052 from external damage.

[0149] In some embodiments, the first external connector 1925 has an epoxy flux (not shown) formed thereon before reflow, and at least some epoxy portions of the epoxy flux remain after the semiconductor device 2050 is attached to the multi-core substrate 1300.

[0150] In some embodiments, an underfill material (not shown) is formed between the multi-core substrate 1300 and the semiconductor device 2050 and surrounds the first external connector 1925. The underfill material can reduce stress and protect the joints generated by reflowing the first external connector 1925. The underfill material can be formed by a capillary flow process after attaching the semiconductor device 2050, or can be formed by a suitable deposition method before attaching the semiconductor device 2050. In embodiments where an epoxy flux is formed, the epoxy flux can serve as the underfill material.

[0151] In one embodiment, the semiconductor device 2050 may include one or more dies, such as logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, or the like), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, or the like), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination of the foregoing. In some embodiments, the semiconductor device 2050 may be an integrated circuit die.

[0152] Figure 20 A cross-sectional view further illustrates the die shadow 2070 projected by the semiconductor device 2050 over the multi-core substrate 1300. In one embodiment, the die shadow represents a power region associated with the semiconductor device 2050. In one embodiment, the multi-core substrate 1300 has a component density within the die shadow 2070 of 4 or more semiconductor components per square millimeter.

[0153] The present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of three dimensional (3D) packaging or 3D integrated circuit devices. The test structures may include, for example, test pads formed in redistribution layers or on substrates, so that 3D packaging or 3D integrated circuits can be tested using probes and / or probe cards and the like. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods that include verifying known good dies mid-stream, thereby increasing yield and reducing cost.

[0154] Embodiments of the present disclosure may achieve several advantages. By embedding multiple semiconductor components (e.g., the first semiconductor component 300) in multiple core substrates (e.g., the first core substrate 100) and bonding these core substrates together (e.g., through an additional process 1150), a high component density can be achieved, providing multiple advantages of the multi-core substrate 1300. The high component density of the multi-core substrate enables the signal integrity to be maintained above 112 Gigabit per second (Gigabit / s, Gbps). In addition, the power integrity across the multi-core substrate 1300 with such a component density can be less than 1 milliohm (mOhm) at 100 megahertz (MHz). Further, by forming vias (e.g., the second via 1600) and metallization patterns (e.g., the first metallization pattern 901), the high component density can provide both internal electrical coupling between the multiple semiconductor components embedded in the multi-core substrate and external electrical coupling across the multi-core substrate 1300 to other devices (e.g., the package substrate 2000 and the semiconductor device 2050), while maintaining sufficient signal integrity and power integrity.

[0155] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes embedding a first semiconductor component in a first core substrate, embedding a second semiconductor component in a second core substrate, attaching the second core substrate to the first core substrate and attaching the second core substrate to the first core substrate to form a multi-layer core substrate, and forming a plurality of first vias extending through the multi-layer core substrate, wherein the plurality of first vias are electrically coupled to the first semiconductor component and the second semiconductor component. In one embodiment, the step of attaching the second core substrate to the first core substrate includes depositing a first resin film over the first core substrate, placing the second core substrate over the first resin film, and curing the first resin film. In one embodiment, the method further includes forming a first redistribution layer on a first side of the first core substrate, wherein the first redistribution layer includes a first conductive feature that electrically couples the first semiconductor component to one of the plurality of first vias. In one embodiment, the step of forming the plurality of first vias includes forming a plurality of perforations through the multi-layer core substrate and electroplating a conductive material along sidewalls of the plurality of perforations. In one embodiment, the method further includes bonding a semiconductor wafer over a top surface of the multi-layer core substrate, wherein the semiconductor wafer forms a die shadow power region projection on the multi-layer core substrate, and wherein the multi-layer core substrate has a component density of 4 or more components per square millimeter within the die shadow power region projection. In one embodiment, the method further includes embedding a third semiconductor component in a third core substrate and attaching the third core substrate to an opposite side of the second core substrate relative to the first core substrate, wherein the third core substrate is part of the multi-layer core substrate. In one embodiment, the first core substrate has a first thickness and the second core substrate has a second thickness different from the first thickness.

[0156] According to an embodiment of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer on a first side of the first core substrate, a second redistribution layer on a second side of the first core substrate opposite the first side, a first resin film above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer on a fourth side of the second core substrate opposite the third side, and a through hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer. In one embodiment, the device further includes a second resin film above the fourth redistribution layer, a third semiconductor component embedded in a third core substrate, a fifth redistribution layer on a fifth side of the third core substrate and bonded to the fourth redistribution layer through the second resin film, and a sixth redistribution layer on a sixth side of the third core substrate opposite the fifth side. In one embodiment, the device further includes a first redistribution build-up structure above the sixth redistribution layer, a semiconductor wafer bonded to the first redistribution build-up structure relative to the sixth redistribution layer, a second redistribution build-up structure below the first redistribution layer, and a substrate bonded to the second redistribution build-up structure through an external connector. In one embodiment, the semiconductor wafer has a die shadow projection passing through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate, and the sixth redistribution layer, wherein the component density within the die shadow projection is 4 or more components per square millimeter. In one embodiment, the first core substrate has a first thickness, and the second core substrate has a second thickness different from the first thickness. In one embodiment, the device further includes a fourth semiconductor component embedded in the second core substrate. In one embodiment, the first semiconductor component is an integrated passive device, a dynamic die, an integrated voltage regulator, or a multilayer ceramic capacitor.

[0157] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes forming a first substrate layer, where the first substrate layer includes a first semiconductor component embedded in a first core substrate, a first redistribution layer of the first substrate layer formed above the first core substrate, and a second redistribution layer of the first substrate layer formed on a side of the first core substrate opposite to the first redistribution layer of the first substrate layer. The method further includes forming a second substrate layer, where the second substrate layer includes a second semiconductor component embedded in a second core substrate, a first redistribution layer of the second substrate layer formed above the second core substrate, and a second redistribution layer of the second substrate layer formed on a side of the second core substrate opposite to the first redistribution layer of the second substrate layer. The method further includes bonding the second substrate layer to the first substrate layer, and forming a first through hole extending through the first substrate layer and the second substrate layer, where the first through hole is electrically coupled to the first semiconductor component. In an embodiment, the method further includes forming a third substrate layer, where the third substrate layer includes a third semiconductor component embedded in a third core substrate, a first redistribution layer of the third substrate layer formed above the third core substrate, and a second redistribution layer of the third substrate layer formed on a side of the third core substrate opposite to the first redistribution layer of the third substrate layer, and the method includes bonding the third substrate layer to a side of the second substrate layer opposite to the first substrate layer. In an embodiment, the method further includes forming a second through hole extending through the first substrate layer, the second substrate layer, and the third substrate layer, where the second through hole is electrically coupled to the second semiconductor component. In an embodiment, the step of embedding the first semiconductor component in the first core substrate includes drilling a first hole through the first core substrate, attaching a polyimide film tape to one side of the first core substrate, performing a pick-and-place step to place the first semiconductor component on the polyimide film tape in the first hole, and removing the polyimide film tape. In an embodiment, the method further includes forming a local through-core substrate via through the first core substrate. In an embodiment, the step of forming the first redistribution layer of the first substrate layer includes depositing a first dielectric material above the first core substrate by a film lamination process, curing the first dielectric material to form a first dielectric layer, forming a blind via opening by a laser process, and electroplating a conductive material in the blind via opening to form a blind via.

[0158] According to an embodiment of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer located on a first side of the first core substrate, a second redistribution layer located on a second side of the first core substrate opposite to the first side, a first resin film located above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer located on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side, and a first through hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer, wherein the first through hole is electrically coupled to the first semiconductor component. The semiconductor device further includes a second resin film located above the fourth redistribution layer, a third semiconductor component embedded in a third core substrate, a fifth redistribution layer located on a fifth side of the third core substrate and bonded to the fourth redistribution layer through the second resin film, a sixth redistribution layer located on a sixth side of the third core substrate opposite to the fifth side, and a second through hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate, and the sixth redistribution layer, wherein the second through hole is electrically coupled to the second semiconductor component. In one embodiment, the semiconductor device further includes a local through-core-substrate via passing through the first core substrate.

[0159] According to an embodiment of the present disclosure, a semiconductor device includes a first semiconductor component embedded in a first core substrate, a first redistribution layer located on a first side of the first core substrate and including a plurality of first conductive features, a second redistribution layer located on a second side of the first core substrate opposite to the first side, a first resin film located above the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer located on a third side of the second core substrate and bonded to the second redistribution layer through the first resin film, a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side and including a plurality of second conductive features, and a plurality of through holes extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer, wherein the first conductive features electrically couple the first semiconductor component to one of the through holes, and the second conductive features electrically couple the second semiconductor component to one of the through holes.

[0160] The foregoing outlines the features of some embodiments, enabling those skilled in the art to better understand the perspective of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor component is embedded in a first core substrate; a first redistribution layer located on a first side of the first core substrate; a second redistribution layer located on a second side of the first core substrate opposite to the first side; a first resin film, located above the second redistribution layer; a second semiconductor component embedded in a second core substrate; a third redistribution layer located on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer through the first resin film; a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side; as well as A through hole extends through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate and the fourth redistribution layer.

2. The semiconductor device according to claim 1, wherein Further including: a second resin film, located above the fourth redistribution layer; a third semiconductor component embedded in a third core substrate; a fifth redistribution layer located on a fifth side of the third core substrate, wherein the fifth redistribution layer is bonded to the fourth redistribution layer through the second resin film; and A sixth redistribution layer is located on a sixth side of the third core substrate opposite to the fifth side.

3. The semiconductor device according to claim 2, wherein: Further including: a first redistribution build-up layer structure, located above the sixth redistribution layer; a semiconductor wafer bonded to the first redistribution build-up layer structure relative to the sixth redistribution layer; a second redistribution build-up layer structure, located below the first redistribution layer; and A substrate is connected to the second redistribution build-up layer structure through a plurality of external connectors.

4. The semiconductor device according to claim 3, wherein: The semiconductor chip has a die shadow projection passing through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate and the sixth redistribution layer, wherein the die shadow projection has a component density of 4 or more components per square millimeter.

5. The semiconductor device according to claim 1, wherein: The first core substrate has a first thickness, and the second core substrate has a second thickness different from the first thickness.

6. The semiconductor device according to claim 1, wherein: The method further includes a fourth semiconductor component buried in the second core substrate.

7. The semiconductor device according to claim 1, wherein The first semiconductor component is an integrated passive device, an active chip, an integrated voltage regulator or a multilayer ceramic capacitor.

8. A semiconductor device, characterized in that: include: A first semiconductor component is embedded in a first core substrate; a first redistribution layer located on a first side of the first core substrate; a second redistribution layer located on a second side of the first core substrate opposite to the first side; a first resin film, located above the second redistribution layer; a second semiconductor component embedded in a second core substrate; a third redistribution layer located on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer through the first resin film; a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side; a first through-hole extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate and the fourth redistribution layer, wherein the first through-hole is electrically coupled to the first semiconductor component; a second resin film, located above the fourth redistribution layer; a third semiconductor component embedded in a third core substrate; a fifth redistribution layer located on a fifth side of the third core substrate, wherein the fifth redistribution layer is bonded to the fourth redistribution layer through the second resin film; a sixth redistribution layer located on a sixth side of the third core substrate opposite to the fifth side; and A second through hole extends through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate and the sixth redistribution layer, wherein the second through hole is electrically coupled to the second semiconductor component.

9. The semiconductor device according to claim 8, wherein: Further comprising a partial through-core substrate through hole passing through the first core substrate.

10. A semiconductor device, characterized in that: include: A first semiconductor component is embedded in a first core substrate; a first redistribution layer on a first side of the first core substrate, wherein the first redistribution layer includes a plurality of first conductive features; a second redistribution layer located on a second side of the first core substrate opposite to the first side; a first resin film, located above the second redistribution layer; a second semiconductor component embedded in a second core substrate; a third redistribution layer located on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer through the first resin film; a fourth redistribution layer located on a fourth side of the second core substrate opposite to the third side, wherein the fourth redistribution layer includes a plurality of second conductive features; as well as A plurality of through holes extend through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate and the fourth redistribution layer, wherein the plurality of first conductive features electrically couple the first semiconductor component to one of the plurality of through holes, and the plurality of second conductive features electrically couple the second semiconductor component to one of the plurality of through holes.

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