Trench oxide layer structure and semiconductor device
By designing an oxide layer with a multi-layer stacked structure in the shielded gate trench device, the leakage problem between the gate and the source is solved, the performance and reliability of the device are improved, and the static power consumption is reduced.
Patent Information
- Application Number
- CN202421842640.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-07-31
AI Technical Summary
In the prior art, the leakage between the gate and source of the shielded gate trench device is large, resulting in an increase in static power consumption, a decrease in switching speed, and a decrease in reliability.
By designing a new trench oxide layer structure in the shielded gate trench device, including a first polysilicon layer, a second polysilicon layer and a third oxide layer, the third oxide layer consists of a multi-layer stacked structure with different materials and increased thickness to isolate the first polysilicon layer from the second polysilicon layer.
Effectively control and minimize gate source and drain, improving the performance, reliability and energy efficiency of shielded gate trench devices.
Smart Images
Figure CN223053360U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and more particularly, to a trench oxide layer structure and a semiconductor device. Background Art
[0002] In semiconductor processes, taking a Shielded Gate Trench (SGT) device as an example, a one-step forming process is usually adopted to construct an oxide layer between the gate polysilicon and the source polysilicon, that is, the above-mentioned oxide layer is directly obtained by oxidizing the source polysilicon. However, when preparing this oxide layer, due to the limitations of the gate oxide layer thickness and polysilicon concentration, the thickness of the above-mentioned oxide layer is relatively thin, resulting in a large leakage current between the gate and the source in the shielded gate trench device, thereby increasing the static power consumption of the device product, reducing the switching speed, and decreasing the reliability.
[0003] Therefore, there is an urgent need for a semiconductor structure that can control and minimize gate-source leakage to ensure the performance, reliability, and energy efficiency of shielded gate trench devices. Summary of the Utility Model
[0004] The purpose of the utility model is to provide a trench oxide layer structure and a semiconductor device that can control and minimize gate-source leakage to ensure the performance, reliability, and energy efficiency of shielded gate trench devices.
[0005] The utility model provides a technical solution:
[0006] In a first aspect, the utility model provides a trench oxide layer structure, which includes:
[0007] An epitaxial wafer;
[0008] A trench located outside the epitaxial layer;
[0009] A first polysilicon layer, a second polysilicon layer, and an oxide layer filled in the trench, where the oxide layer includes a first oxide layer, a second oxide layer, and a third oxide layer; the first polysilicon layer is located below the second polysilicon layer; the first oxide layer is disposed around the first polysilicon layer; the second oxide layer is disposed around the second polysilicon layer; the third oxide layer is disposed between the first polysilicon layer and the second polysilicon layer to isolate the first polysilicon layer and the second polysilicon layer through the third oxide layer;
[0010] Wherein, the third oxide layer includes at least one stacked structure; each stacked structure is sequentially overlapped from top to bottom to increase the thickness of the third oxide layer; and the materials of adjacent two layers in the stacked structure are different.
[0011] In a possible implementation manner, the stacked structure includes at least three layers, which sequentially include a top oxide layer, an interlayer compound layer, and a bottom oxide layer from top to bottom;
[0012] Among them, the thickness of the bottom oxide layer is less than the thickness of the top oxide layer.
[0013] In a possible implementation manner, the dielectric constant of the interlayer compound layer is greater than or equal to 10.
[0014] In a possible implementation manner, the material for making the interlayer compound layer is any one of hafnium oxide, silicon nitride, aluminum oxide, hafnium oxide, and titanium oxide.
[0015] In a possible implementation manner, the material for making the bottom oxide layer and / or the top oxide layer is tetraethoxysilane.
[0016] In a possible implementation manner, the material for preparing the bottom oxide layer is tetraethoxysilane; the material for preparing the interlayer compound layer is hafnium oxide; the material for preparing the top oxide layer is tetraethoxysilane.
[0017] In a possible implementation manner, the thickness of the third oxide layer is greater than or equal to 2000 angstroms.
[0018] In a possible implementation manner, the thickness of the bottom oxide layer is greater than or equal to 500 angstroms; the thickness of the interlayer compound layer is greater than or equal to 500 angstroms; the thickness of the top oxide layer is greater than or equal to 1000 angstroms; and the thickness of the top oxide layer is greater than the thickness of the bottom oxide layer.
[0019] In a possible implementation manner, the width of the first polysilicon layer is greater than the width of the second polysilicon layer.
[0020] In a second aspect, the present invention further provides a semiconductor device, including the trench oxide layer structure described in any item of the first aspect above.
[0021] The beneficial effects of a trench oxide layer structure and a semiconductor device provided by the present invention are:
[0022] The trench oxide layer structure in the present utility model includes: an epitaxial wafer; trenches located outside the epitaxial layer; a first polysilicon layer, a second polysilicon layer, and an oxide layer filled in the trenches, the oxide layer including a first oxide layer, a second oxide layer, and a third oxide layer; the first polysilicon layer is located below the second polysilicon layer; the first oxide layer is disposed around the first polysilicon layer; the second oxide layer is disposed around the second polysilicon layer; the third oxide layer is disposed between the first polysilicon layer and the second polysilicon layer to isolate the first polysilicon layer and the second polysilicon layer through the third oxide layer. Among them, the third oxide layer includes at least one stacked structure; each stacked structure is sequentially overlapped from top to bottom to increase the thickness of the third oxide layer; and the materials between adjacent two layers in the stacked structure are different. The present utility model controls and minimizes gate-source leakage by adjusting the structure and / or thickness of the third oxide layer, thereby ensuring the performance, reliability, and energy efficiency of the shield-gate trench device. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.
[0024] Figure 1 FIG. 1 is one of the schematic diagrams of a trench oxide layer structure provided by the present utility model;
[0025] Figure 2 FIG. 2 is one of the schematic diagrams of the structure of the third oxide layer in the present utility model;
[0026] Figure 3 FIG. 3 is the schematic diagram of the stacked structure in the present utility model;
[0027] Figure 4 FIG. 4 is another schematic diagram of the structure of the third oxide layer in the present utility model;
[0028] Figure 5 FIG. 5 is yet another schematic diagram of the structure of the third oxide layer in the present utility model;
[0029] Figure 6 FIG. 6 is one of the exemplary preparation schematic diagrams provided by the embodiments of the present utility model;
[0030] Figure 7 FIG. 7 is another exemplary preparation schematic diagram provided by the embodiments of the present utility model;
[0031] Figure 8 FIG. 8 is yet another exemplary preparation schematic diagram provided by the embodiments of the present utility model.
[0032] Icons: 100 - trench oxide layer structure; 101 - epitaxial wafer; 102 - trench; 103 - first polysilicon layer; 104 - second polysilicon layer; 105 - oxide layer; 201 - first oxide layer; 202 - second oxide layer; 203 - third oxide layer; 301 - stacked structure; 302 - top oxide layer; 303 - interlayer compound layer; 304 - bottom oxide layer; 401 - first stacked structure; 402 - second stacked structure; 501 - first top oxide layer; 502 - first interlayer compound layer; 503 - first bottom oxide layer; 504 - second top oxide layer; 505 - second interlayer compound layer; 506 - second bottom oxide layer. Detailed implementation manners
[0033] To make the objectives, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Apparently, the described embodiments are some but not all of the embodiments of the present utility model. Usually, the components of the embodiments of the present utility model described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0034] Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the present utility model to be protected, but merely represents the selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the scope of protection of the present utility model.
[0035] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0036] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship when the product of this utility model is in normal use, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model.
[0037] In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.
[0038] In the description of the present utility model, it should also be noted that unless otherwise clearly specified and defined, the terms "arrangement", "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0039] SGT devices typically use a one-step process to form the InterPoly Oxide (IPO) between the gate polysilicon and the source polysilicon. However, when preparing this oxide layer, due to the limitations of the gate oxide layer thickness and polysilicon concentration, the thickness of the above-mentioned IPO oxide layer is relatively thin, resulting in a large leakage current between the gate and the source in the SGT device, increasing the static power consumption of the SGT device, reducing the switching speed, and decreasing the reliability.
[0040] Based on this, the present utility model provides a semiconductor solution that can control and minimize the gate-source leakage to ensure the performance, reliability, and energy efficiency of the shield-gate trench device.
[0041] The following will introduce this semiconductor solution in detail.
[0042] Embodiment
[0043] In a first aspect, please refer to Figure 1 , the present utility model provides a trench oxide layer structure 100, and the trench oxide layer structure 100 includes:
[0044] An epitaxial wafer 101. In a possible implementation manner, the epitaxial wafer includes an epitaxial layer and a substrate. It should be noted that the material of the substrate is not limited in this application. For example, the epitaxial layer can be a homoepitaxy, in which case the materials of the epitaxial layer and the substrate are the same, both being silicon carbide materials; of course, the epitaxial layer can be a heteroepitaxy, in which case the materials of the epitaxial layer and the substrate are different, such as the substrate can be a sapphire substrate, a silicon substrate, etc.
[0045] A trench 102 located outside the epitaxial layer.
[0046] A first polysilicon layer 103, a second polysilicon layer 104, and an oxide layer 105 filled in the trench 102, and the oxide layer 105 includes a first oxide layer 201, a second oxide layer 202, and a third oxide layer 203.
[0047] Please continue to refer to Figure 1, the first polysilicon layer 103 is located below the second polysilicon layer 104; the first oxide layer 201 is disposed around the first polysilicon layer 103; the second oxide layer 202 is disposed around the second polysilicon layer 104; the third oxide layer 203 is disposed between the first polysilicon layer 103 and the second polysilicon layer 104 to isolate the first polysilicon layer 103 from the second polysilicon layer 104 through the third oxide layer 203.
[0048] In this embodiment, a new structure of the third oxide layer is provided to change the structure and / or thickness of the third oxide layer, thereby improving the performance of the semiconductor device.
[0049] Please refer to Figure 2 , in this embodiment, the third oxide layer 203 includes at least one stacked structure 301; the stacked structures 301 are sequentially stacked from top to bottom to increase the thickness of the third oxide layer 203; and the materials between adjacent two layers in the stacked structure 301 are different.
[0050] In a possible implementation manner, the stacked structure in the third oxide layer may be an ONO structure to increase the thickness of the IPO oxide layer through the ONO structure. Please refer to Figure 3 , the stacked structure 301 includes at least three layers, sequentially including a top oxide layer 302, an interlayer compound layer 303, and a bottom oxide layer 304 from top to bottom.
[0051] Among them, the thickness of the bottom oxide layer 304 is less than the thickness of the top oxide layer 302. That is, L1 is greater than L2.
[0052] In this embodiment, to overcome the problem of large gate-source leakage, the thickness of the third oxide layer needs to be greater than or equal to 2000 angstroms.
[0053] In a possible implementation manner, when the third oxide layer includes only one stacked structure, the thickness of the bottom oxide layer needs to be greater than or equal to 500 angstroms; the thickness of the interlayer compound layer needs to be greater than or equal to 500 angstroms; the thickness of the top oxide layer needs to be greater than or equal to 1000 angstroms; and the thickness of the top oxide layer also needs to be greater than the thickness of the bottom oxide layer.
[0054] To better improve the problem of large gate-source leakage, materials with a larger dielectric constant can be used to adjust the performance of the ONO structure. In a possible implementation manner, the dielectric constant of the interlayer compound layer is greater than or equal to 10.
[0055] In this embodiment, the material for making the interlayer compound layer is any one of hafnium oxide, silicon nitride, aluminum oxide, hafnium oxide, and titanium oxide.
[0056] The materials of the bottom oxide layer and the top oxide layer can be the same or different. In a possible implementation, the material for making the bottom oxide layer and / or the top oxide layer is tetraethyl orthosilicate.
[0057] This embodiment provides a preferred structural composition: the material for preparing the bottom oxide layer is tetraethyl orthosilicate; the material for preparing the interlayer compound layer is hafnium oxide; the material for preparing the top oxide layer is tetraethyl orthosilicate.
[0058] In this embodiment, when the third oxide layer includes a plurality of stacked structures; the stacked structures are sequentially overlapped from top to bottom, where the stacked structure includes at least three layers, and sequentially includes a top oxide layer, an interlayer compound layer, and a bottom oxide layer from top to bottom. Between adjacent stacked structures, an oxide layer can be shared. Specifically, assume that the third oxide layer includes a first stacked structure and a second stacked structure from top to bottom in sequence. Among them, the first stacked structure includes a first top oxide layer, a first interlayer compound layer, and a first bottom oxide layer; the second stacked structure includes a second top oxide layer, a second interlayer compound layer, and a second bottom oxide layer.
[0059] In a possible implementation, please refer to Figure 4 , the current third oxide layer 203 sequentially includes from top to bottom: a first top oxide layer 501, a first interlayer compound layer 502, a first bottom oxide layer 503, a second top oxide layer 504, a second interlayer compound layer 505, and a second bottom oxide layer 506.
[0060] In another possible implementation, please refer to Figure 5 , the current third oxide layer 203 sequentially includes from top to bottom: a first top oxide layer 501, a first interlayer compound layer 502, a first bottom oxide layer 503 or a second top oxide layer 504, a second interlayer compound layer 505, and a second bottom oxide layer 506. Specifically, when the first bottom oxide layer 503 and the second top oxide layer 504 are made of the same material, the corresponding oxide layer can be prepared only once, serving as the first bottom oxide layer 503 in the first stacked structure 401, or serving as the second top oxide layer 504 in the second stacked structure 402, thereby omitting the oxide layer preparation process.
[0061] The present utility model provides a trench oxide layer structure, which controls and minimizes gate-source leakage by adjusting the structure and / or thickness of the third oxide layer, thereby ensuring the performance, reliability, and energy efficiency of the shield gate trench device.
[0062] The following is an exemplary description of the manufacturing method of the trench oxide layer structure 100 provided by this application:
[0063] A substrate is provided, and an epitaxial layer is grown on the substrate. The epitaxial layer can be etched using a photoresist to form trenches on the epitaxial layer. For example, a photoresist can be spin-coated on the surface of the epitaxial layer, and the photoresist can be used as a masking layer. Then, the photoresist is patterned. For example, the photoresist can be patterned by the cooperation of a mask plate and ultraviolet light, and then a masking layer provided with a plurality of through holes is formed. Then, the epitaxial layer is etched through an etching process. Due to the masking of the photoresist, the area coated with the photoresist will not be etched, while the area not coated with the photoresist will be etched, and thus trenches are formed on the epitaxial layer.
[0064] After that, the photoresist layer can be directly stripped. For example, a wet etching process or a dry photoresist removal process is used to remove the photoresist on the surface of the epitaxial layer, and a trench structure is formed on the epitaxial layer.
[0065] Please refer to Figure 6 , after obtaining the trench structure, an oxide layer can be fabricated on the surface of the trench through a thermal oxidation process, that is, a shielding gate oxide layer is formed on the surface of the trench (the sidewall and the bottom wall of the trench), which is the first oxide layer 201 described above. Generally, the thickness of the shielding gate oxide layer can meet 300 - 600 nm. Among them, the thickness of each hierarchical structure and the thickness of the shielding gate oxide layer are only examples. They are not limited in this application.
[0066] Next, polysilicon is deposited in the trench oxide layer, that is, the trench is filled with polysilicon to obtain polysilicon inside the trench, such as source polysilicon, which is the first polysilicon layer described above. Please refer to Figure 7 , Figure 7 shows that after the first polysilicon layer is deposited in the trench oxide layer, the first oxide layer is wet-etched to make the height of the first oxide layer lower than the height of the first polysilicon layer, so that the prepared third oxide layer can wrap the surface of the first polysilicon layer to completely isolate the first polysilicon layer from the second polysilicon layer.
[0067] Please refer to Figure 8 , Figure 8 shows a schematic diagram of the trench after the third oxide layer is prepared. In this embodiment, the third oxide layer can be prepared by using CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition) methods. When the third oxide layer includes a stacked structure, for the top oxide layer, the interlayer compound layer, and the bottom oxide from top to bottom, the materials are tetraethoxysilane, hafnium oxide, and tetraethoxysilane in sequence. Among them, the top oxide layer and the bottom oxide layer can be formed by tetraethoxysilane deposition and dry etching; the interlayer compound layer can be formed by hafnium oxide chemical vapor deposition and dry etching.
[0068] After the third oxide layer is prepared, the normal polysilicon deposition and etching processes can be resumed; similarly, a second oxide layer can be formed in the trench through a thermal oxidation process; subsequently, polysilicon is deposited on the basis of the second oxide layer to obtain a second polysilicon, namely the gate polysilicon. Among them, the width of the first polysilicon layer is greater than that of the second polysilicon layer.
[0069] Please continue to refer to Figure 1 , Figure 1 which shows the trench oxide layer structure obtained by the present application according to the above preparation method. It should be noted that the present invention does not limit the preparation method of a trench oxide layer structure provided in this embodiment, and the above preparation scheme is only an example.
[0070] In summary, this embodiment provides a trench oxide layer structure, which includes: an epitaxial wafer; a trench located outside the epitaxial layer; a first polysilicon layer, a second polysilicon layer, and an oxide layer filled in the trench, and the oxide layer includes a first oxide layer, a second oxide layer, and a third oxide layer; the first polysilicon layer is located below the second polysilicon layer; the first oxide layer is disposed around the first polysilicon layer; the second oxide layer is disposed around the second polysilicon layer; the third oxide layer is disposed between the first polysilicon layer and the second polysilicon layer to isolate the first polysilicon layer and the second polysilicon layer through the third oxide layer. Among them, the third oxide layer includes at least one stacked structure; each stacked structure is sequentially overlapped from top to bottom to increase the thickness of the third oxide layer; and the materials between adjacent two layers in the stacked structure are different.
[0071] The present invention controls and minimizes gate-source leakage by adjusting the structure and / or thickness of the third oxide layer, thereby ensuring the performance, reliability, and energy efficiency of the shielded-gate trench device.
[0072] In a second aspect, the present invention also provides a semiconductor device, including the trench oxide layer structure according to any one of the above first aspects.
[0073] A semiconductor device provided in this embodiment includes the trench oxide layer structure according to any one of the above first aspects, and has all the technical features and technical effects of the above first aspect.
[0074] In summary, the present invention controls and minimizes gate-source leakage by adjusting the structure and / or thickness of the third oxide layer, thereby ensuring the performance, reliability, and energy efficiency of the shielded-gate trench device.
[0075] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
[0076] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present application. Any reference signs in the claims should not be construed as limiting the claims involved.
Claims
1. A trench oxide layer structure, characterized in that: The trench oxide layer structure comprises: Epitaxial wafer; a trench located outside the epitaxial layer; A first polysilicon layer, a second polysilicon layer and an oxide layer filled in the trench, wherein the oxide layer includes a first oxide layer, a second oxide layer and a third oxide layer; the first polysilicon layer is located below the second polysilicon layer; the first oxide layer is disposed around the outside of the first polysilicon layer; the second oxide layer is disposed around the outside of the second polysilicon layer; the third oxide layer is disposed between the first polysilicon layer and the second polysilicon layer, so as to isolate the first polysilicon layer from the second polysilicon layer through the third oxide layer; The third oxide layer includes at least one stacked structure; the stacked structures are overlapped in sequence from top to bottom to increase the thickness of the third oxide layer; and the materials between two adjacent layers in the stacked structure are different.
2. The trench oxide layer structure according to claim 1, characterized in that: The stacked structure comprises at least three layers, which include, from top to bottom, a top oxide layer, an interlayer compound layer and a bottom oxide layer; Wherein, the thickness of the bottom oxide layer is smaller than the thickness of the top oxide layer.
3. The trench oxide layer structure according to claim 2, characterized in that: The dielectric constant of the interlayer compound layer is greater than or equal to 10.
4. The trench oxide layer structure according to claim 3, characterized in that: The material for making the interlayer compound layer is any one of hafnium oxide, silicon nitride, aluminum oxide, hafnium oxide and titanium oxide.
5. The trench oxide layer structure according to claim 2, characterized in that: The material used to make the bottom oxide layer and / or the top oxide layer is tetraethoxysilane.
6. The trench oxide layer structure according to claim 2, characterized in that: The material for preparing the bottom oxide layer is tetraethoxysilane; the material for preparing the interlayer compound layer is hafnium oxide; and the material for preparing the top oxide layer is tetraethoxysilane.
7. The trench oxide layer structure according to claim 2, characterized in that: The thickness of the third oxide layer is greater than or equal to 2000 angstroms.
8. The trench oxide layer structure according to claim 7, characterized in that: The thickness of the bottom oxide layer is greater than or equal to 500 angstroms; the thickness of the interlayer compound layer is greater than or equal to 500 angstroms; the thickness of the top oxide layer is greater than or equal to 1000 angstroms; and the thickness of the top oxide layer is greater than the thickness of the bottom oxide layer.
9. The trench oxide layer structure according to claim 1, characterized in that: The width of the first polysilicon layer is greater than the width of the second polysilicon layer.
10. A semiconductor device, characterized in that: The invention comprises the trench oxide layer structure as claimed in any one of claims 1 to 9.