Wafer test packaging module

Abstract

The utility model provides a wafer testing and packaging module, which relates to the technical field of wafer testing devices, and comprises a testing bottom plate, at least a first mounting area and a second mounting area are arranged on the testing bottom plate and are respectively used for mounting different wafers to be tested, and the testing bottom plate is provided with a plurality of first mounting holes and a plurality of second mounting holes. The first mounting area and the second mounting area are respectively provided with a plurality of test pins, the test pins are electrically connected with a wafer to be tested to form test circuits, the test circuits of the first mounting area and the second mounting area are connected in series, and the test circuits of the first mounting area and the second mounting area are symmetrically arranged. A plurality of wafers to be tested are connected in series to form a symmetrical test circuit structure, and the performance of the wafers can be accurately known only by verifying the half-bridge in the test, so that the test efficiency is improved. During testing, the performance of a single wafer can be tested independently, the actual chip performance can be better reflected, and collected data are more accurate.

Description

Technical Field

[0001] The utility model relates to the technical field of wafer testing devices, and particularly relates to a wafer testing and packaging module. Background Art

[0002] A power semiconductor module is a single power semiconductor device formed by packaging multiple power semiconductor wafers through a certain technological process; generally, a power semiconductor module can achieve high integration and a significant increase in power level through the interconnection of its internal wafers; among them, the manufacturing process of a semiconductor power module is as follows: after the wafer is completed in wafer processing, it is diced to obtain individual wafers; the wafers are subjected to reliability and consistency tests to screen out qualified products, and the qualified products with consistent parameters are divided into multiple categories according to certain standards; a certain number of wafers are selected from the same category and placed in the same power module for packaging to obtain a semiconductor power module. After packaging, the wafers need to be further tested to obtain information such as the working performance and actual use parameters of the chips. The existing testing method is mainly probe station bare wafer testing (probe station bare wafer testing), but before testing, the wafers need to be placed in a special simulation package, the operation process is complex, the equipment price is high, the stray inductance of the wafers during testing is high, and the collected data has large errors. Content of the Utility Model

[0003] The purpose of the utility model is to provide a wafer testing and packaging module to solve the above technical problems.

[0004] In a first aspect, the utility model provides a wafer testing and packaging module, including: a test bottom plate, on which at least a first installation area and a second installation area are provided. The first installation area and the second installation area are respectively used for installing different wafers to be tested. A plurality of test pins are respectively provided in the first installation area and the second installation area. The test pins are electrically connected to the wafers to be tested to form a test circuit. The test circuits in the first installation area and the second installation area are connected in series with each other, and the test circuits in the first installation area and the second installation area are symmetrically arranged.

[0005] In an optional embodiment, the wafer to be tested has at least a power input terminal, a signal input terminal, and a power output terminal. The test pins include a power input pin, a signal pin, and a power output pin respectively provided in the first installation area and the second installation area. The power input terminal is connected to the power input pin, the signal input terminal is connected to the signal pin, and the power output terminal is connected to the power output pin. The power output terminal of the wafer to be tested in the first installation area is connected in series with the power input terminal of the wafer to be tested in the second installation area.

[0006] In an alternative embodiment, the test pins further include a total input pin, a total output pin, and an intermediate input pin. The total input pin is electrically connected to the power input terminal of the wafer to be tested in the first mounting area. The total output pin is electrically connected to the power output terminal of the wafer to be tested in the second mounting area. The intermediate input pin is simultaneously connected to the power output terminal of the wafer to be tested in the first mounting area and the power input terminal of the wafer to be tested in the second mounting area.

[0007] In an alternative embodiment, the total input pin and the total output pin are arranged on the same side of the test base plate. The power input pins, signal pins, and power output pins in the first mounting area and the second mounting area are all arranged and symmetrically distributed at both ends of the test base plate.

[0008] In an alternative embodiment, the test pins are bent at 90 degrees and extend in a direction away from the test base plate.

[0009] In an alternative embodiment, the test pins are all arranged at the edge of the test base plate.

[0010] In an alternative embodiment, the wafer to be tested is an IGBT wafer.

[0011] In an alternative embodiment, an annular protective sealing ring is provided on the test base plate. The wafer to be tested and the test pins are both arranged inside the sealing ring.

[0012] In an alternative embodiment, the inside of the protective sealing ring is filled with an insulating encapsulation layer.

[0013] In an alternative embodiment, the test base plate is a ceramic copper clad board, and the insulating encapsulation layer is a silicone filling layer.

[0014] A wafer test packaging module provided by the present utility model includes: a test base plate, on which at least a first mounting area and a second mounting area are provided. The first mounting area and the second mounting area are respectively used for mounting different wafers to be tested. A plurality of test pins are respectively provided in the first mounting area and the second mounting area. The test pins are electrically connected to the wafers to be tested to form a test circuit. The test circuits in the first mounting area and the second mounting area are connected in series with each other, and the test circuits in the first mounting area and the second mounting area are symmetrically arranged. By connecting multiple wafers to be tested in series to form a symmetric test circuit structure, only half of the bridge needs to be verified during the test to accurately know the wafer performance, thereby improving the test efficiency. When testing, the performance of a single wafer can be tested separately, which can better reflect the actual chip performance, and the collected data is also more accurate. Description of the Drawings

[0015] To more clearly illustrate the specific embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 3D view of the wafer test packaging module provided by the embodiment of the present utility model;

[0017] Figure 2 Circuit structure diagram of the wafer test packaging module provided by the embodiment of the present utility model;

[0018] Figure 3 Dynamic test circuit structure diagram of the wafer test packaging module provided by the embodiment of the present utility model;

[0019] Figure 4 One of the static test circuit structure diagrams of the wafer test packaging module provided by the embodiment of the present utility model;

[0020] Figure 5 Another static test circuit structure diagram of the wafer test packaging module provided by the embodiment of the present utility model.

[0021] Icon: 100 - test base plate; 101 - first installation area; 102 - second installation area; 200 - test pins; 201 - power input pin; 202 - signal pin; 203 - power output pin; 204 - total input pin; 205 - total output pin; 206 - intermediate input pin; 300 - protective sealing ring; 400 - wafer to be tested. Specific embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. Generally, the components of the embodiments of the present utility model described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present utility model provided in the drawings is not intended to limit the scope of the claimed present utility model, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts fall within the scope of protection of the present utility model.

[0024] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present utility model is usually placed during use. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model. In addition, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0025] The following will describe in detail some embodiments of the present utility model with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0026] Embodiment 1

[0027] This embodiment provides a wafer test packaging module, including: a test bottom plate 100, on which at least a first installation area 101 and a second installation area 102 are provided. The first installation area 101 and the second installation area 102 are respectively used for installing different wafers 400 to be tested. A plurality of test pins 200 are respectively provided in the first installation area 101 and the second installation area 102. The test pins 200 are electrically connected to the wafers 400 to be tested to form a test circuit. The test circuits of the first installation area 101 and the second installation area 102 are connected in series with each other, and the test circuits of the first installation area 101 and the second installation area 102 are symmetrically arranged.

[0028] Please refer to Figure 1 As shown, in this embodiment, a first installation area 101 and a second installation area 102 are provided on the test bottom plate 100, which are respectively used for installing different wafers 400 to be tested. A plurality of test pins 200 are provided on the test bottom plate 100. The output and input terminals of the wafers 400 to be tested are respectively connected to the test pins 200 through wires to form a test circuit. An operator can connect a power supply or a test device to the test pins 200 to energize the wafers 400 to be tested and detect the performance of the wafers 400 to be tested and various parameters during actual use. The test circuits of the first installation area 101 and the second installation area 102 are connected in series with each other, and the test circuits of the first installation area 101 and the second installation area 102 are symmetrically arranged. Please refer to Figure 2As shown, the test circuits of the first installation area 101 and the second installation area 102 are connected in series with each other, so as to connect different wafers 400 to be tested, simulating the usage state of the wafers inside the power semiconductor module connected to each other during actual use, which is convenient for testing the actual usage parameters of the overall structure. At the same time, the test circuit structures of the first installation area 101 and the second installation area 102 are the same and symmetrically arranged. During testing, a single wafer 400 to be tested can be tested separately, and the test data is closer to the electrical performance of the chip body.

[0029] Optionally, in some embodiments of this embodiment, the wafer 400 to be tested has at least a power input terminal, a signal input terminal, and a power output terminal. The test pins 200 include a power input pin 201, a signal pin 202, and a power output pin 203 respectively arranged in the first installation area 101 and the second installation area 102. The power input terminal is connected to the power input pin 201, the signal input terminal is connected to the signal pin 202, the power output terminal is connected to the power output pin 203, and the power output terminal of the wafer 400 to be tested in the first installation area 101 is connected in series with the power input terminal of the wafer 400 to be tested in the second installation area 102.

[0030] Please refer to Figure 2 as shown Figure 2 is the wafer circuit structure diagram provided by this embodiment. In this embodiment, the wafer 400 to be tested has a power input terminal, a signal input terminal, and a power output terminal. The power input terminal, the signal input terminal, and the power output terminal are respectively connected to the power input pin 201, the signal pin 202, and the power output pin 203 on the test base plate 100, which is convenient for the operator to connect the external test circuit.

[0031] In some embodiments of this embodiment, the test pins 200 further include a total input pin 204, a total output pin 205, and an intermediate input pin 206. The total input pin 204 is electrically connected to the power input terminal of the wafer 400 to be tested in the first installation area 101, the total output pin 205 is electrically connected to the power output terminal of the wafer 400 to be tested in the second installation area 102, and the intermediate input pin 206 is simultaneously connected to the power output terminal of the wafer 400 to be tested in the first installation area 101 and the power input terminal of the wafer 400 to be tested in the second installation area 102.

[0032] Please refer to Figure 1 and Figure 2As shown, in this embodiment, the power output terminal of the wafer 400 to be tested in the first installation area 101 is connected in series with the power input terminal of the wafer 400 to be tested in the second installation area 102. The power output terminal of the test wafer in the first installation area 101 is connected to the total input pin 204 on the test base plate 100, and the power output terminal of the wafer 400 to be tested in the second installation area 102 is connected to the total output pin 205. An intermediate input pin 206 is provided at the connection between the wafer 400 to be tested in the first installation area 101 and the wafer 400 to be tested in the second installation area 102, and the intermediate input pin 206 is connected to both the power output terminal of the wafer 400 to be tested in the first installation area 101 and the power input terminal of the wafer 400 to be tested in the second installation area 102. Please refer to Figure 3 As shown, Figure 3 is the schematic diagram of the dynamic test circuit of the wafer provided in this embodiment. In this embodiment, the total input pin 204, the total output pin 205, and the intermediate input pin 206 are high-current terminals for inputting drive current. The signal input terminal and the power output terminal of the wafer 400 to be tested form a drive signal input circuit for inputting control signals. The power input terminal and the power output terminal of the wafer 400 to be tested also serve as test sampling terminals, and data detection can be performed by connecting a test device between the power input terminal and the power output terminal. Please refer to Figure 4 and Figure 5 As shown, Figure 4 and Figure 5 are the static test circuit structure diagrams of the wafer test packaging module. When testing the data of a single wafer, corresponding test devices (such as ammeters, voltmeters, etc.) can be connected to the power input terminal and the power output terminal of the corresponding wafer. The specific test devices are determined according to the actual test items, and are not limited in this embodiment.

[0033] Optionally, in some implementation manners of this embodiment, the total input pin 204 and the total output pin 205 are arranged on the same side of the test base plate 100, and the power input pins 201, the signal pins 202, and the power output pins 203 in the first installation area 101 and the second installation area 102 are all arranged and symmetrically distributed at both ends of the test base plate 100.

[0034] Please refer to Figure 1As shown, in this embodiment, the total input pins 204 and the total output pins 205 are arranged at intervals on one side of the test base plate 100, and the total input pins 204 and the total output pins 205 are respectively arranged in the first installation area 101 and the second installation area 102. The total input pins 204 are connected to the wafers 400 to be tested in the first installation area 101, and the total output pins 205 are electrically connected to the wafers 400 to be tested in the second installation area 102. Arranging the total input pins 204 and the total output pins 205 in the first installation area 101 and the second installation area 102 respectively can effectively reduce the wiring path, the wiring is shorter and more uniform, and the wiring layout realizes current sharing. At the same time, the total input pins 204 and the total output pins 205 are arranged side by side, which is convenient for the operator to connect the driving power supply to supply power to the wafers. Please refer to Figure 1 As shown, power input pins 201, signal pins 202 and power output pins 203 are arranged in both the first installation area 101 and the second installation area 102. The output pins in the first installation area 101 and the second installation area 102 are symmetrically arranged at both ends of the test base plate 100, which is convenient for wiring during testing and avoids wiring interference.

[0035] Optionally, in some embodiments of this embodiment, the test pins 200 are bent at 90 degrees and extend in a direction away from the test base plate 100.

[0036] Please refer to Figure 1 As shown, in this embodiment, the test pins 200 are all set to a right-angle structure, and the test pins 200 extend in a direction away from the test base plate 100, so that the test pins 200 protrude from the test base plate 100, which is convenient for the operator to connect the wiring or contact pins to the test pins 200, thereby improving the detection efficiency.

[0037] Optionally, in some embodiments of this embodiment, the test pins 200 are all arranged at the edge of the test base plate 100.

[0038] Please refer to Figure 1 As shown, in this embodiment, the test pins 200 are all arranged at the edge of the test base plate 100, and the center of the test base plate 100 is used to install the wafers 400 to be tested, which is convenient for the wiring connection between the wafers 400 to be tested and the test pins 200, and is also convenient for external sampling devices to connect to the test pins 200, improving the sampling efficiency and test accuracy.

[0039] Optionally, in some embodiments of this embodiment, the wafers 400 to be tested are IGBT wafers.

[0040] The wafer test packaging module provided by this embodiment is applicable to verifying IGBT wafers, and can verify the performance of a single wafer and test the performance of a product module.

[0041] Optionally, in some embodiments of the present embodiment, an annular protective sealing ring 300 is provided on the test bottom plate 100, and the wafer 400 to be tested and the test pins 200 are both arranged inside the sealing ring.

[0042] Please refer to Figure 1 As shown, in the present embodiment, an annular sealing ring is provided at the edge of the test bottom plate 100, and the size of the sealing ring can be adjusted according to the shape of the test bottom plate 100 and the number of wafers 400 to be tested. The sealing ring protrudes from the test bottom plate 100, and an installation space is formed inside the sealing ring for installing structures such as the wafer 400 to be tested and the test pins 200.

[0043] Optionally, in some embodiments of the present embodiment, the inside of the protective sealing ring 300 is filled with an insulating encapsulation layer.

[0044] In the present embodiment, the insulating encapsulation layer is used to isolate and protect the wafers 400 to be tested in the first installation area 101 and the second installation area 102, prevent the wafers 400 to be tested from contacting the external environment, ensure the stability of the wafers 400 to be tested, and thus accurately measure the parameter performance of the wafers in the actual packaging environment.

[0045] Optionally, in some embodiments of the present embodiment, the test bottom plate 100 is a ceramic copper clad laminate, and the insulating encapsulation layer is a silicone filling layer.

[0046] Specifically, in the present embodiment, the copper clad ceramic substrate has excellent thermal cycling performance, stable shape, good rigidity, high thermal conductivity, and high reliability, and is a common semiconductor packaging substrate. Its manufacturing process is mature and the cost is low. Using a ceramic copper clad laminate to package the wafer 400 to be tested is also closer to the actual use environment of the wafer, can better reflect the actual chip performance, and the collected data is more accurate. After the wafer 400 to be tested is welded and installed on the test bottom plate 100, silicone filling encapsulation is used to form a silicone filling layer under the action of the sealing ring.

[0047] In summary, the present utility model provides a wafer test packaging module, including: a test bottom plate 100, on which at least a first installation area 101 and a second installation area 102 are provided. The first installation area 101 and the second installation area 102 are respectively used for installing different wafers 400 to be tested. A plurality of test pins 200 are respectively arranged in the first installation area 101 and the second installation area 102. The test pins 200 are electrically connected to the wafers 400 to be tested to form test circuits. The test circuits of the first installation area 101 and the second installation area 102 are connected in series with each other, and the test circuits of the first installation area 101 and the second installation area 102 are symmetrically arranged. By connecting multiple wafers to be tested in series to form a symmetric test circuit structure, only half of the bridge needs to be verified during the test to accurately know the wafer performance, thereby improving the test efficiency. During the test, the performance of a single wafer can be tested separately, which can better reflect the actual chip performance, and the collected data is also more accurate.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model and are not intended to limit them. Although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present utility model.

Claims

1. A wafer test packaging module, characterized in that, Including: A test base plate (100), on which at least a first installation area (101) and a second installation area (102) are provided. The first installation area (101) and the second installation area (102) are respectively used for installing different wafers to be tested (400). A plurality of test pins (200) are respectively provided in the first installation area (101) and the second installation area (102). The test pins (200) are electrically connected to the wafers to be tested (400) to form test circuits. The test circuits of the first installation area (101) and the second installation area (102) are connected in series with each other, and the test circuits of the first installation area (101) and the second installation area (102) are symmetrically arranged.

2. The wafer test packaging module according to claim 1, wherein The wafer to be tested (400) has at least a power input terminal, a signal input terminal and a power output terminal. The test pins (200) include a power input pin (201), a signal pin (202) and a power output pin (203) respectively provided in the first installation area (101) and the second installation area (102). The power input terminal is connected to the power input pin (201), the signal input terminal is connected to the signal pin (202), and the power output terminal is connected to the power output pin (203). The power output terminal of the wafer to be tested (400) in the first installation area (101) is connected in series with the power input terminal of the wafer to be tested (400) in the second installation area (102).

3. The wafer test packaging module according to claim 2, wherein, The test pins (200) further include a total input pin (204), a total output pin (205) and an intermediate input pin (206). The total input pin (204) is electrically connected to the power input terminal of the wafer to be tested (400) in the first installation area (101), the total output pin (205) is electrically connected to the power output terminal of the wafer to be tested (400) in the second installation area (102), and the intermediate input pin (206) is simultaneously connected to the power output terminal of the wafer to be tested (400) in the first installation area (101) and the power input terminal of the wafer to be tested (400) in the second installation area (102).

4. The wafer test package module according to claim 3, wherein The total input pin (204) and the total output pin (205) are arranged on the same side of the test base plate (100). The power input pins (201), signal pins (202) and power output pins (203) in the first installation area (101) and the second installation area (102) are all arranged and symmetrically distributed at both ends of the test base plate (100) with the center as the symmetry axis.

5. The wafer test packaging module according to claim 1, wherein The test pins (200) are bent at 90 degrees and extend in a direction away from the test base plate (100).

6. The wafer test packaging module according to claim 1, wherein The test pins (200) are all provided at the edge of the test base plate (100).

7. The wafer test packaging module according to any one of claims 1-6, characterized in that, The wafer to be tested (400) is an IGBT wafer.

8. The wafer test package module according to any one of claims 1-6, characterized in that, An annular protective sealing ring (300) is provided on the test base plate (100), and the wafer to be tested (400) and the test pins (200) are both arranged inside the sealing ring.

9. The wafer test packaging module according to claim 8, wherein The inside of the protective sealing ring (300) is filled with an insulating encapsulation layer.

10. The wafer test package module according to claim 9, wherein The test base plate (100) is a ceramic copper clad board, and the insulating encapsulation layer is a silica gel filling layer.

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