High-anti-interference PWM (Pulse Width Modulation) high-voltage loop interlocking detection circuit
Through the PWM signal dual-end complementary transmission and the differential amplifier to filter out common mode interference, the problem of insufficient anti-interference capability in high-voltage loop interlock detection is solved, and high reliability monitoring is achieved in complex electromagnetic environments.
Patent Information
- Application Number
- CN202421220065.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-30
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-05-30
AI Technical Summary
In the existing high-voltage loop interlock detection technology, the constant current source method is costly and susceptible to component parameter fluctuations. The single-ended PWM square wave signal has poor anti-interference ability in complex electromagnetic environments, resulting in reduced signal distortion and monitoring results reliability.
The PWM signal dual-terminal complementary transmission method is adopted, and the excitation source module is driven by the uC microprocessor outputs complementary PWM signals. The signal is processed by the HVIL loop and the detection and acquisition module and then input into the uC microprocessor. The common mode interference is filtered out by a differential amplifier and compared with the reference value through the comparator to achieve high anti-interference detection.
It improves the anti-interference ability of high-voltage loop interlock detection, ensures the accuracy and reliability of signals in complex electromagnetic environments, and avoids signal distortion and false alarms.
Smart Images
Figure CN223065484U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of high-voltage circuit interlock detection, and specifically, to a high-anti-interference PWM-mode high-voltage loop interlock detection circuit. Background Technique
[0002] High-voltage interlock or high-voltage interlock loop, abbreviated as HVIL loop, is a technology that uses low-voltage signals to monitor the electrical connection continuity of all high-voltage circuits (battery systems, motor controllers, connectors, DC / DC, high-voltage boxes, etc.) connected to the high-voltage bus on electric vehicles, aiming to protect personnel at any stage of the electric vehicle life cycle (during vehicle assembly, repair, maintenance, and operation).
[0003] Nowadays, there are generally two schemes to realize the detection of the high-voltage loop interlock loop, namely, using a constant current source and a single-ended PWM square wave. The problems existing in the way of using a constant current source are as follows: First, if a dedicated integrated chip is used to realize constant current, the cost is high; Second, if discrete devices are used to realize constant current, it is easily affected by the parameter fluctuations of components at high and low temperatures; Third, if the loop cable is long, there is a large loss of constant current on the cable; Fourth, in the above two cases of the second and third, it will cause numerical deviation of the collected voltage and generate false alarm phenomena. The way of using a single-ended PWM square wave also has deficiencies. For example, when using a single-ended PWM voltage signal transmission, in the complex electromagnetic environment of the vehicle, the anti-interference ability is poor, and it is very easy to be affected by common-mode interference and cause signal distortion, thus seriously affecting the reliability of the monitoring results.
[0004] In view of this, we propose a high-anti-interference PWM-mode high-voltage loop interlock detection circuit. Content of the Utility Model
[0005] The purpose of the utility model is to provide a high-voltage loop interlock detection circuit that uses the dual-ended complementary transmission method of PWM signals to solve the problems proposed in the above background technique.
[0006] To achieve the above purpose, the utility model provides the following technical scheme:
[0007] A high-anti-interference PWM-mode high-voltage loop interlock detection circuit includes an HVIL loop and an electronic controller connected in series with the HVIL loop. The electronic controller includes an excitation source module, a detection and acquisition module, and a uC microprocessor. The output end of the uC microprocessor outputs complementary PWM signals to drive the excitation source module. The excitation source module emits PWM signals from the output end and transmits them to the input end of the HVIL loop, outputs from the output end of the HVIL loop, and transmits them to the input end of the detection and acquisition module. The PWM signals are processed by the detection and acquisition module and then input to the uC microprocessor.
[0008] As a further solution of the utility model: the HVIL loop includes several HVIL interfaces connected to high-voltage components, and each HVIL interface is connected in series.
[0009] As a further solution of the utility model: the uC microprocessor includes at least two output terminals and two input terminals. Two output terminals of the uC microprocessor are respectively connected to two input terminals of the excitation source module and respectively send complementary PWM signals. The frequency range of the PWM signals is 50 - 150 Hz, and the duty cycle range of the PWM signals is 20 - 80%. Two input terminals of the uC microprocessor are respectively connected to two output terminals of the detection and acquisition module, receive two paths of PWM signals processed by the detection and acquisition module, and judge the state of high-voltage loop interlock according to the duty cycles of the two paths of signals.
[0010] As a further solution of the utility model: two output ports of the excitation source module are respectively connected to the uC_HVIL_P and uC_HVIL_N nodes of the HVIL loop.
[0011] As a further solution of the utility model: the detection and acquisition module includes at least two input terminals. The PWM signal passing through the uC_HVIL_N node enters one input terminal of the detection and acquisition module from the HVIL_DN node after passing through the HVIL loop. The PWM signal passing through the uC_HVIL_P node enters the input terminal of the excitation source module after passing through the HVIL loop and enters the other input terminal of the detection and acquisition module from the HVIL_DP node of the excitation source module.
[0012] As a further solution of the utility model: the detection and acquisition module includes a differential amplifier for amplifying the signal output by the excitation source module to the detection and acquisition module and filtering out common-mode interference, and a comparator for receiving the output signal of the differential amplifier and comparing it with a preset reference value.
[0013] As a further solution of the utility model: the differential amplifier includes at least two input terminals and one output terminal. The number of comparators is two, and one output terminal of the differential amplifier is respectively connected to the input terminal of one comparator.
[0014] As a further solution of the utility model: the signals input from the HVIL-DN node and the signals input from the HVIL-DP node pass through the differential amplifier and are respectively output as HVIL-PWM1 and HVIL-PWM2 signals through one comparator.
[0015] Compared with the prior art, the beneficial effects of the utility model are:
[0016] 1. In the high anti-interference PWM-based high-voltage loop interlock detection circuit, complementary PWM signals are output from the output terminal of the uC microprocessor to drive the excitation source module. The excitation source module sends out PWM signals from the output terminal and transmits them to the input terminal of the HVIL loop, outputs from the output terminal of the HVIL loop, and transmits them to the input terminal of the detection and acquisition module. After being processed by the detection and acquisition module, the PWM signals are input to the uC microprocessor for judgment, solving the problem that in a complex electromagnetic environment of a vehicle, the single-ended PWM square wave signal with poor anti-interference ability is easily affected by common-mode interference, resulting in signal distortion, thus seriously affecting the reliability of the monitoring results. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the overall working principle of this solution;
[0018] Figure 2 It is a schematic diagram of the signal flow of the HVIL loop of this solution;
[0019] Figure 3 It is a schematic diagram of the circuit of the detection and acquisition module of this solution.
[0020] The meanings of each label in the figure are as follows:
[0021] 100, HVIL loop; 101, HVIL interface;
[0022] 200, electronic controller; 210, excitation source module; 220, detection and acquisition module; 221, differential amplifier; 222, comparator; 230, uC microprocessor. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0024] Embodiment 1
[0025] As Figure 1As shown in the figure, this embodiment provides a high anti-interference high-voltage loop interlock detection circuit in PWM mode, which includes a HVIL loop 100 and an electronic controller 200 connected in series with the HVIL loop 100. The electronic controller 200 includes an excitation source module 210, a detection and acquisition module 220, and a uC microprocessor 230. The output end of the uC microprocessor 230 outputs complementary PWM signals to drive the excitation source module 210. The excitation source module 210 emits PWM signals from the output end and transmits them to the input end of the HVIL loop 100, and outputs from the output end of the HVIL loop 100. The PWM signals are transmitted to the input end of the detection and acquisition module 220. After being processed by the detection and acquisition module 220, the PWM signals are input to the uC microprocessor 230.
[0026] The improvement of this embodiment lies in that: the output end of the uC microprocessor 230 outputs complementary PWM signals to drive the excitation source module 210. The excitation source module 210 emits PWM signals from the output end and transmits them to the input end of the HVIL loop 100, outputs from the output end of the HVIL loop 100, and is transmitted to the input end of the detection and acquisition module 220. After being processed by the detection and acquisition module 220, the PWM signals are input to the uC microprocessor 230 for judgment, solving the problem that in a complex electromagnetic environment of a vehicle, the single-ended PWM square wave signal with poor anti-interference ability is easily affected by common-mode interference, resulting in signal distortion, thus seriously affecting the reliability of the monitoring results.
[0027] Considering the detection of each HVIL interface 101, therefore, the HVIL loop 100 includes a plurality of HVIL interfaces 101 connected to high-voltage components, and each HVIL interface 101 is connected in series.
[0028] Such as Figure 2As shown in the figure, considering that the incoming PWM signals need to be compared with each other to achieve comparison, the uC microprocessor 230 includes at least two output terminals and two input terminals. The two output terminals of the uC microprocessor 230 are respectively connected to the two input terminals of the excitation source module 210 and respectively emit complementary PWM signals. The frequency range of the PWM signals is 50 - 150 Hz, and the duty cycle range of the PWM signals is 20 - 80%. In this embodiment, a PWM signal with a frequency of 52 Hz and a duty cycle of 30% is preferably output, and the two output PWM signals have the same frequency. The two input terminals of the uC microprocessor 230 are respectively connected to the two output terminals of the detection and acquisition module 220, receive the two PWM signals processed by the detection and acquisition module 220, and judge the state of the high-voltage loop interlock according to the duty cycles of the two signals. The two output ports of the excitation source module 210 are respectively connected to the uC_HVIL_P and uC_HVIL_N nodes of the HVIL loop 100. The detection and acquisition module 220 includes at least two input terminals. Among them, the PWM signal passing through the uC_HVIL_N node is introduced into one input terminal of the detection and acquisition module 220 from the HVIL_DN node after passing through the HVIL loop 100, and the PWM signal passing through the uC_HVIL_P node is introduced into the input terminal of the excitation source module 210 after passing through the HVIL loop 100 and is introduced into the other input terminal of the detection and acquisition module 220 from the HVIL_DP node of the excitation source module 210.
[0029] As Figure 3 shown in the figure, considering ensuring the stability and accuracy of the signals output from the HVIL_DP node and the HVIL_DN node, so as to facilitate subsequent comparison, the detection and acquisition module 220 includes a differential amplifier 221 for amplifying the output PWM signal and filtering out common-mode interference. The differential amplifier 221 includes at least two input terminals and two output terminals. The current signals introduced from the HVIL_DP node and the HVIL_DN node are corrected by the differential amplifier 221 to reduce errors in subsequent comparison.
[0030] Considering that the HVIL loop 100 is in different states and needs to be compared and referenced to confirm the state of the HVIL loop 100. Therefore, the detection and acquisition module 220 includes a comparator 222 for comparing the PWM signal output by the differential amplifier 221 with a preset reference value. The number of comparators 222 is two. The output end of the differential amplifier 221 is connected to the input end of the comparator 222. After the signal input from the HVIL_DN node is corrected by the differential amplifier 221, it is then compared with the preset reference value by one of the comparators 222 and output as the HVIL-PWM1 signal. After the signal input from the HVIL_DP node is corrected by the differential amplifier 221, it is then compared with the preset reference value by the other comparator 222 and output as the HVIL-PWM2 signal. Finally, the state of the HVIL loop 100 is obtained through the HVIL-PWM1 signal and the HVIL-PWM2 signal.
[0031] For the HVIL loop 100 in different states, further explanations are given for the HVIL-PWM1 signal and the HVIL-PWM2 signal with different percentages:
[0032] In the first state, when the HVIL loop 100 is normally connected, both the HVIL-PWM1 signal and the HVIL-PWM2 signal are output at 50% ± 5%.
[0033] In the second state, when the HVIL loop 100 has a short circuit to the power supply, the HVIL-PWM1 signal is output at 0%, and the HVIL-PWM2 signal is output at 50% ± 10%.
[0034] In the third state, when the HVIL loop 100 has a short circuit to the ground, the HVIL-PWM1 signal is output at 50% ± 10%, and the HVIL-PWM2 signal is output at 0%.
[0035] In the fourth state, when the HVIL loop 100 is open, both the HVIL-PWM1 signal and the HVIL-PWM2 signal are output at 15% ± 5%.
[0036] The whole vehicle needs to perform different controls according to the state of the HVIL loop 100. Therefore, when the HVIL loop 100 is in the second, third, or fourth state, the uC microprocessor 230 in the whole vehicle system comprehensively processes the signals input through the comparator 222 and issues an instruction to the whole vehicle controller, so that the whole vehicle controller controls the vehicle to give an alarm prompt or cut off the power supply.
[0037] Embodiment 2
[0038] Select a PWM signal with a frequency of 148 Hz and a duty cycle of 70% for output, and the rest is the same as in Embodiment 1.
[0039] In summary, the working principle of this solution is as follows:
[0040] When the driver starts the vehicle, the entire vehicle is powered on. The uC microprocessor 230 outputs two complementary PWM signals to drive the excitation source module 210. The frequency range of the PWM signals is 50 - 150 Hz, and the duty cycle range of the PWM signals is 20 - 80%. The two output PWM signals have the same frequency. After being processed by the excitation source module 210, the PWM signals are input from the input end of the HVIL loop 100 and output from the output end of the HVIL loop 100. Among them, the PWM signal passing through the uC_HVIL_N node is input from the HVIL_DN node to an input end of the detection and acquisition module 220, and the PWM signal passing through the uC_HVIL_P node is input to the input end of the excitation source module 210 and input from the HVIL_DP node of the excitation source module 210 to the other input end of the detection and acquisition module 220. The two input signals input to the detection and acquisition module 220 are amplified by the differential amplifier 221 and processed to filter out common-mode interference, and then enter the comparator 222, where they are compared with the preset reference value in the comparator 222. The comparator 222 outputs the HVIL-PWM1 signal and the HVIL-PWM2 signal to the uC microprocessor 230 for comprehensive processing by the uC microprocessor 230. When the processing result indicates that the HVIL loop 100 is in a short power supply, short ground, or open circuit state, the uC microprocessor 230 issues an instruction to the vehicle controller, causing the vehicle controller to control the vehicle to give an alarm prompt or cut off the power supply.
[0041] Although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0042] Therefore, the above description is only a preferred embodiment of the present application and is not used to limit the scope of implementation of the present application; that is, all equivalent transformations made according to the scope of the claims of the present application are within the protection scope of the claims of the present application.
Claims
1. A high anti-interference PWM-based high-voltage loop interlock detection circuit, comprising an HVIL loop (100) and an electronic controller (200) connected in series with the HVIL loop (100), characterized in that: The electronic controller (200) includes an excitation source module (210), a detection and acquisition module (220), and a uC microprocessor (230). The output end of the uC microprocessor (230) outputs complementary PWM signals to drive the excitation source module (210). The excitation source module (210) emits PWM signals from its output end and inputs them into the input end of the HVIL loop (100), outputs from the output end of the HVIL loop (100), and inputs them into the input end of the detection and acquisition module (220). The PWM signals are input to the uC microprocessor (230) after being processed by the detection and acquisition module (220).
2. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 1, wherein: The HVIL loop (100) includes several HVIL interfaces (101) connected to high-voltage components, and each HVIL interface (101) is in series.
3. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 1, characterized in that: The uC microprocessor (230) includes at least two output ends and two input ends. Two output ends of the uC microprocessor (230) are respectively connected to two input ends of the excitation source module (210), and complementary PWM signals are respectively emitted. The frequency range of the PWM signals is between 50 and 150 Hz, and the duty cycle range of the PWM signals is between 20 and 80%. Two input ends of the uC microprocessor (230) are respectively connected to two output ends of the detection and acquisition module (220), receive two paths of PWM signals processed by the detection and acquisition module (220), and judge the state of high-voltage loop interlock according to the duty cycles of the two paths of signals.
4. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 1, characterized in that: Two output ports of the excitation source module (210) are respectively connected to the uC_HVIL_P and uC_HVIL_N nodes of the HVIL loop (100).
5. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 4, characterized in that: The detection and acquisition module (220) includes at least two input ends. The PWM signal passing through the uC_HVIL_N node is input into one input end of the detection and acquisition module (220) from the HVIL_DN node after passing through the HVIL loop (100). The PWM signal passing through the uC_HVIL_P node is input into the input end of the excitation source module (210) after passing through the HVIL loop (100), and is input into the other input end of the detection and acquisition module (220) from the HVIL_DP node of the excitation source module (210).
6. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 1, characterized in that: The detection and acquisition module (220) includes a differential amplifier (221) for amplifying the signal output by the excitation source module (210) to the detection and acquisition module (220) and filtering out common-mode interference, and a comparator (222) for receiving the output signal of the differential amplifier (221) and comparing it with a preset reference value.
7. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 6, wherein: The differential amplifier (221) includes at least two input ends and one output end. The number of the comparators (222) is two, and one output end of the differential amplifier (221) is respectively connected to the input end of one comparator (222).
8. The high-anti-interference PWM-based high-voltage loop interlock detection circuit according to claim 5, wherein: The signals input from the HVIL_DN node and the HVIL_DP node pass through the differential amplifier (221) and are respectively output as HVIL-PWM1 and HVIL-PWM2 signals through one comparator (222).