Package chip and electronic device
By setting grooves on the peripheral side wall of the chip body and embeding the packaging layer to form a ring buckle structure, the problem of gaps between the chip body and the packaging layer is solved, and the reliability and service life of the packaging chip are improved.
Patent Information
- Application Number
- CN202422240123.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-09-12
AI Technical Summary
In the prior art, the chip covered with crystal thin film is prone to bend when subjected to external forces, resulting in a gap between the chip body and the packaging layer, which in turn leads to water vapor infiltration, affecting the reliability and service life of the packaging chip.
The circumferential side wall of the chip body is provided, and the packaging layer is embedded in the groove, forming a ring-lock structure, increasing the connection surface and generating a reverse force under the action of external forces, reducing the possibility of separation between the chip body and the packaging layer.
It effectively reduces the possibility of water vapor infiltration, improves the service life and reliability of the packaging chip, and reduces the risk of packaging layer separation caused by external forces.
Smart Images
Figure CN223066160U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of chip technology, and particularly relates to a packaged chip and an electronic device. Background Art
[0002] In the related art, Chip On Flex (COF) is a chip soft film packaging technology that fixes an integrated circuit on a flexible printed circuit board. A chip packaged using COF usually includes a chip body, a substrate, and a packaging layer. The packaging layer is used to package the chip body and the substrate. When an external force acts on the chip body, it will bend, and thus a gap will be formed between the chip body and the packaging layer. The appearance of the gap will cause moisture and the like to penetrate, resulting in the failure of the packaged chip. Utility Model Content
[0003] The purpose of the embodiments of this application is to provide a packaged chip and an electronic device, which can effectively solve the technical problem of the appearance of a gap between the chip body and the packaging layer.
[0004] In a first aspect, the embodiments of this application provide a packaged chip, including:
[0005] A substrate;
[0006] A chip body, disposed on one side of the substrate, the chip body having a groove, and the opening of the groove being located on the circumferential sidewall of the chip body;
[0007] A packaging layer, packaging the chip body and the substrate, and a part of the packaging layer being embedded in the groove.
[0008] As a possible implementation manner, the groove is a ring structure, and the opening of the groove surrounds the circumferential sidewall of the chip body; or
[0009] The number of grooves is at least two, and at least two grooves are spaced apart from each other on the chip body.
[0010] As a possible implementation manner, the circumferential sidewall is a prism structure, and each surface of the circumferential sidewall has an opening of the groove.
[0011] As a possible implementation manner, the chip body further includes a first end face and a second end face that are opposite to each other. The first end face faces the substrate. The circumferential sidewall of the chip body includes a first sidewall, a second sidewall, and a stepped sidewall. The first sidewall, the second sidewall, and the stepped sidewall form a stepped shape. The stepped sidewall is located between the first end face and the second end face, and the opening of the groove is located on the stepped sidewall.
[0012] As a possible implementation manner, the stepped sidewall faces away from the substrate.
[0013] As a possible implementation manner, the groove extends from the stepped sidewall towards the first end face.
[0014] As a possible implementation manner, the groove extends from the circumferential sidewall into the interior of the chip body.
[0015] As a possible implementation manner, the chip body further includes opposite first end face and second end face, the first end face faces the substrate, and along the direction from the first end face to the second end face, there are at least two grooves.
[0016] As a possible implementation manner, the encapsulation layer covers the circumferential sidewall.
[0017] In a second aspect, an embodiment of the present application provides an electronic device, including:
[0018] The encapsulated chip provided in the embodiment of the first aspect.
[0019] In the embodiment of the present application, the encapsulated chip includes a substrate, a chip body, and an encapsulation layer. The encapsulation layer is used to encapsulate the chip body and the substrate, and there is a groove on the chip body. The opening of the groove is located on the circumferential sidewall of the chip body. During encapsulation, the encapsulation layer will be embedded into the groove, thereby increasing the connection surface between the chip body and the encapsulation layer. When the chip body is bent by an external force, due to the existence of the groove, when a reverse force is generated between the chip body and the encapsulation layer, a certain reverse force can be formed, thereby reducing the possibility of cracking between the chip body and the encapsulation layer, reducing the possibility of water vapor and the like infiltrating into the encapsulated chip, and improving the service life of the encapsulated chip. Description of the Drawings
[0020] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:
[0021] Figure 1 Shows a cross-sectional view of an encapsulated chip provided by an embodiment of the present application;
[0022] Figure 2 Shows a cross-sectional view of the chip body in the encapsulated chip provided by an embodiment of the present application;
[0023] Figure 3 Shows a cross-sectional view of the encapsulated chip provided by an embodiment of the present application when the chip body is stressed;
[0024] Figure 4 Shows a cross-sectional view of the encapsulated chip provided by an embodiment of the present application;
[0025] Figure 5 Shows a cross-sectional view of the chip body in the encapsulated chip provided by an embodiment of the present application;
[0026] Figure 6 Shows a schematic diagram of an electronic device provided by an embodiment of the present application.
[0027] Figures 1 to 6 Reference Numerals:
[0028] 100 Encapsulated Chip, 110 Substrate, 120 Chip Body, 1202 Sharp Corner, 122 Peripheral Side Wall, 1222 First Side Wall, 1224 Second Side Wall, 1226 Step Side Wall, 124 Groove, 1242 Opening, 126 First End Face, 128 Second End Face, 130 Encapsulation Layer, 140 Conductive Bump, 150 Lead, 160 Rubber, 200 Electronic Device, 210 Main Board. Detailed Embodiment
[0029] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.
[0030] The terms "first" and "second" in the description and claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.
[0031] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "inner", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application.
[0032] In the description of the present application, it should be noted that, unless otherwise clearly specified and defined, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0033] The following will be combined with Figures 1 to 6 Describe the encapsulated chip 100 and the electronic device 200 according to the embodiments of the present application.
[0034] In a first aspect, as shown in Figure 1 , Figure 2 , Figure 4 and Figure 5 , an embodiment of the present application provides a packaged chip 100, including: a substrate 110; a chip body 120 disposed on one side of the substrate 110, the chip body 120 having a groove 124, and an opening 1242 of the groove 124 being located on a circumferential sidewall 122 of the chip body 120; a packaging layer 130 for packaging the chip body 120 and the substrate 110, and a part of the packaging layer 130 being embedded in the groove 124.
[0035] In the embodiment of the present application, the packaged chip 100 includes a substrate 110, a chip body 120, and a packaging layer 130. The packaging layer 130 is used to package the chip body 120 and the substrate 110. Moreover, the chip body 120 has a groove 124, and an opening 1242 of the groove 124 is located on the circumferential sidewall 122 of the chip body 120. During packaging, the packaging layer 130 will be embedded into the groove 124, thereby increasing the connection surface between the chip body 120 and the packaging layer 130. When the chip body 120 is bent by an external force, due to the existence of the groove 124, when a reverse force is generated between the chip body 120 and the packaging layer 130, a certain reverse force can be formed, thereby reducing the possibility of cracking between the chip body 120 and the packaging layer 130, and reducing the possibility of moisture and the like infiltrating into the packaged chip 100, and improving the service life of the packaged chip 100.
[0036] Through the structure in which the packaging layer 130 is embedded in the chip body 120, the present application can reduce the separation between the packaging layer 130 and the chip body 120, and reduce the risk of reduced reliability of the packaged chip 100 during long-term use. Specifically, a groove 124 is provided on the sidewall of the chip body 120, and the packaging layer 130 is embedded in the groove 124 to form a loop structure, thereby effectively reducing the possibility of separation between the chip body 120 and the packaging layer 130 and improving the protection effect on the chip body 120.
[0037] As a possible implementation manner, the groove 124 is a ring structure, and the opening 1242 of the groove 124 surrounds the circumferential sidewall 122 of the chip body 120; or the number of the grooves 124 is at least two, and at least two grooves 124 are provided on the chip body 120 at intervals.
[0038] Specifically, the groove 124 can be a ring structure, and the opening 1242 of the groove 124 surrounds the circumferential sidewall 122 of the chip body 120. That is, an embedding effect is formed on both the circumferential side of the encapsulation layer 130 and the chip body 120. When the chip body 120 is bent by an external force, the contact surface between the encapsulation layer 130 and the chip body 120 can form a reverse force on the entire circumferential side of the chip body 120, thereby ensuring the sealing performance between the chip body 120 and the encapsulation layer 130, further reducing the possibility of water vapor and the like infiltrating into the packaged chip 100, and enhancing the service life of the packaged chip 100.
[0039] Alternatively, the number of the grooves 124 is at least two, and the at least two grooves 124 are provided on the chip body 120 at intervals. That is, the grooves 124 are not arranged to surround the chip body 120, thereby reducing the occupied space of the grooves 124 on the chip body 120 and helping to reduce the volume of the chip body 120.
[0040] As a possible implementation manner, the circumferential sidewall 122 is a prism structure, and each surface of the circumferential sidewall 122 has the opening 1242 of the groove 124.
[0041] Specifically, the circumferential sidewall 122 is a prism structure, that is, the circumferential sidewall 122 is formed with multiple surfaces, and each surface has the opening 1242 of the groove 124. Each surface has the embedding of the encapsulation layer 130. That is, an embedding effect is formed on each side surface of the encapsulation layer 130 and the chip body 120. When the chip body 120 is bent by an external force, the contact surface between the encapsulation layer 130 and the chip body 120 can form a reverse force on each side surface of the chip body 120, thereby ensuring the sealing performance between the chip body 120 and the encapsulation layer 130, further reducing the possibility of water vapor and the like infiltrating into the packaged chip 100, and enhancing the service life of the packaged chip 100.
[0042] As Figure 1 and Figure 2 shown, as a possible implementation manner, the chip body 120 further includes a first end face 126 and a second end face 128 that are opposite to each other. The first end face 126 faces the substrate 110. The circumferential sidewall 122 of the chip body 120 includes a first sidewall 1222, a second sidewall 1224, and a stepped sidewall 1226. The first sidewall 1222, the second sidewall 1224, and the stepped sidewall 1226 form a stepped shape. The stepped sidewall 1226 is located between the first end face 126 and the second end face 128, and the opening 1242 of the groove 124 is located on the stepped sidewall 1226.
[0043] Specifically, the chip body 120 further includes a first end face 126 and a second end face 128 that face away from each other. The first end face 126 faces the substrate 110, and the second end face 128 is away from the substrate 110. The peripheral side wall 122 includes a first side wall 1222, a second side wall 1224, and a stepped side wall 1226. That is, the peripheral side wall 122 is formed in a stepped shape, and the opening 1242 of the groove 124 is provided on the stepped side wall 1226, which is more convenient for the embedding of the encapsulation material and improves the reliability of the connection between the encapsulation layer 130 and the chip body 120.
[0044] As Figure 1 and Figure 2 shown, as a possible implementation manner, the stepped side wall 1226 faces away from the substrate 110.
[0045] Specifically, the stepped side wall 1226 is arranged to face away from the substrate 110, so that the size of the side of the chip body 120 away from the substrate 110 is smaller than the size of the side of the chip body 120 close to the substrate 110. Thus, the size of the encapsulation layer 130 at the upper position of the chip body 120 can be reduced, the total amount of the encapsulation layer 130 can be reduced, and the production cost can be lowered.
[0046] As Figure 1 and Figure 2 shown, as a possible implementation manner, the groove 124 extends from the stepped side wall 1226 towards the first end face 126.
[0047] Specifically, the groove 124 extends from the stepped side wall 1226 towards the first end face 126, and thus a protrusion similar to a hook is formed on the peripheral side of the chip body 120. After the encapsulation layer 130 is embedded in the groove 124, a structure in which the two can be buckled with each other is formed, thereby improving the connection strength between the encapsulation layer 130 and the chip body 120.
[0048] As Figure 1 shown, the packaged chip 100 includes a chip body 120, conductive bumps 140, a substrate 110, leads 150, rubber 160, and an encapsulation layer 130. The first side wall 1222 is in contact with the encapsulation layer 130, and the two form a first contact surface. The second side wall 1224 is in contact with the encapsulation layer 130, and the two form a second contact surface. The encapsulation layer 130 is embedded in the groove 124 to form a loop structure, and the first contact surface and the second contact surface are separated by the loop structure.
[0049] As Figure 3 shown, when an external force F acts on the chip body 120, the sharp corner 1202 on the side of the chip body 120 away from the substrate 110 will release stress upward, and the loop structure formed by the groove 124 and the encapsulation layer 130 will generate a stress that makes the second contact surface move towards the inside of the chip body 120 to prevent the separation of the second contact surface.
[0050] When an external force is applied in the reverse direction of F, the loop structure formed by the groove 124 and the encapsulation layer 130 will generate a stress that causes the first contact surface to face the outside of the chip body 120, so as to prevent the separation of the first contact surface.
[0051] The first contact surface and the second contact surface are separated by the loop structure, reducing the possibility of external water vapor infiltrating into the packaged chip 100, enhancing the protection effect on the chip body 120, and reducing the possibility of damage to the packaged chip 100.
[0052] In this application, by providing the groove 124 on the circumferential sidewall 122 of the chip, the loop structure is formed by the groove 124 and the encapsulation layer 130, thereby effectively reducing the possibility of separation between the circumferential sidewall 122 of the chip and the encapsulation layer 130 caused by external forces, and enhancing the reliability of the packaged chip 100.
[0053] As Figure 4 and Figure 5 shown, as a possible implementation manner, the groove 124 extends from the circumferential sidewall 122 towards the inside of the chip body 120.
[0054] Specifically, the groove 124 extends from the circumferential sidewall 122 towards the inside of the chip body 120, so that the chip body 120 and the encapsulation layer 130 form an interlocking structure, thereby enhancing the connection strength between the encapsulation layer 130 and the chip body 120.
[0055] As Figure 4 and Figure 5 shown, as a possible implementation manner, the chip body 120 further includes opposite first end face 126 and second end face 128. The first end face 126 faces the substrate 110, and along the direction AB from the first end face 126 to the second end face 128, there are at least two grooves 124.
[0056] Specifically, the chip body 120 further includes opposite first end face 126 and second end face 128. The first end face 126 faces the substrate 110, and the second end face 128 is away from the substrate 110. Along the direction AB from the first end face 126 to the second end face 128, there are at least two grooves 124. Increasing the number of grooves 124 can increase the contact surface between the encapsulation layer 130 and the chip body 120. Furthermore, when the chip body 120 bends, more contact surfaces can provide a greater anti-bending force, thereby increasing the bending tolerance of the chip body 120 and further reducing the service life of the packaged chip 100.
[0057] As Figure 4As shown in the figure, for the encapsulated chip 100 provided in the present application, two grooves 124 are provided on the chip body 120 along the direction AB from the first end face 126 to the second end face 128, strengthening the bonding strength between the chip body 120 and the encapsulation layer 130. Further, if one groove 124 is separated from the encapsulation layer 130, there is still another groove 124 that can prevent the separation of the chip body 120 and the encapsulation layer 130. The encapsulated chip 100 provided in the present application improves the bonding strength between the encapsulation layer 130 and the chip body 120, and improves the reliability of the encapsulated chip 100.
[0058] As Figure 1 , Figure 2 , Figure 4 and Figure 5 shown, as a possible implementation, the encapsulation layer 130 covers the peripheral side wall 122.
[0059] Specifically, the encapsulation layer 130 covers the entire peripheral side wall 122 of the chip body 120, thereby improving the protection effect of the encapsulation layer 130 on the chip body 120. The encapsulation layer 130 and the chip body 120 have a sufficient contact area, which can improve the sealing effect between the encapsulation layer 130 and the chip body 120.
[0060] As a possible implementation, the substrate 110 is a flexible substrate, such as: Polyimide Tape (PI Tape), and the encapsulated chip 100 is fabricated using a flip chip thin film.
[0061] In a second aspect, as Figure 6 shown, the present application provides an electronic device 200, including: a main board 210; and the encapsulated chip 100 provided in the first aspect embodiment.
[0062] Since the electronic device 200 provided in the present application includes the encapsulated chip 100 provided in the first aspect embodiment, therefore, it has all the beneficial effects of the encapsulated chip 100 provided in the first aspect embodiment, which will not be elaborated one by one here.
[0063] As a possible implementation, the electronic device 200 further includes a screen, a camera, a housing, etc.
[0064] As a possible implementation, the electronic device 200 may be a mobile phone, a tablet computer, a notebook computer, a handheld computer, an in-vehicle electronic device, a private network communication terminal device (such as a walkie-talkie), a Mobile Internet Device (MID), an augmented reality / virtual reality / mixed reality device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. It may also be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc. The embodiments of the present application do not make specific limitations thereto.
[0065] In the description of this specification, the description referring to terms such as "one embodiment" or "specific embodiment" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.
[0066] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the present application is defined by the claims and their equivalents.
Claims
1. An encapsulated chip, characterized in that, Comprising: Substrate; Chip body, disposed on one side of the substrate, the chip body having a groove, and an opening of the groove located on a circumferential sidewall of the chip body; Encapsulation layer, encapsulating the chip body and the substrate, and a part of the encapsulation layer being embedded in the groove.
2. The encapsulated chip according to claim 1, wherein: The groove is a ring structure, and the opening of the groove surrounds the circumferential sidewall of the chip body; or The number of the grooves is at least two, and at least two of the grooves are disposed on the chip body at intervals.
3. The encapsulated chip according to claim 1, wherein: The circumferential sidewall is a prism structure, and each surface of the circumferential sidewall has an opening of the groove.
4. The encapsulated chip according to any one of claims 1 to 3, characterized in that, The chip body further includes opposite first end face and second end face, the first end face faces the substrate, the circumferential sidewall of the chip body includes a first sidewall, a second sidewall and a stepped sidewall, the first sidewall, the second sidewall and the stepped sidewall form a stepped shape, the stepped sidewall is located between the first end face and the second end face, and the opening of the groove is located on the stepped sidewall.
5. The encapsulated chip according to claim 4, wherein: The stepped sidewall faces away from the substrate.
6. The encapsulated chip according to claim 4, wherein: The groove extends from the stepped sidewall to the first end face.
7. The encapsulated chip according to any one of claims 1 to 3, wherein: The groove extends from the circumferential sidewall into the interior of the chip body.
8. The encapsulated chip according to any one of claims 1 to 3, wherein: The chip body further includes opposite first end face and second end face, the first end face faces the substrate, and along the direction from the first end face to the second end face, there are at least two of the grooves.
9. The encapsulated chip according to any one of claims 1 to 3, wherein: The encapsulation layer covers the circumferential sidewall.
10. An electronic device, characterized in that, Comprising: Main board; The encapsulated chip according to any one of claims 1 to 9, the encapsulated chip being disposed on the main board.