CJTAG test board

Abstract

The utility model discloses a CJTAG test board, which relates to the technical field of electronic test, and comprises a controller module, which comprises a master controller and a slave controller which are electrically connected with each other; the external control input module is respectively connected with the master controller and the slave controller through JTAG (Joint Test Action Group) ports; the external test function module is electrically connected with the controller module; and the power supply module provides 3.3 V and 1.2 V power supplies for the controller module, the external control input module and the external test function module. The CJTAG test board provided by the utility model has the beneficial effects that compared with the conventional test board of the same type, the CJTAG test board provided by the utility model can be configured with more abundant and freer test resources, and can test various types of protocol ports or functions more conveniently. Besides, the two MCUs are used for configuration, the two MCUs are connected through ports, and by means of the design, multiple JTAG testing can be completed on one testing board.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic testing, in particular to a CJTAG test board. Background Art

[0002] The main function of the CJTAG test board is to configure perfect test resources for JTAG testing to help complete JTAG testing. Users can interact with the test board through the JTAG standard port to detect or configure a variety of test resources on the test board. These rich test resources include: LED control port, button detection port, ADC SPI detection port, adjustable resistor detection port, IIC EEPROM detection port, SRAM detection port, dual-chip MCU detection port, etc.

[0003] However, at present, it is still impossible to implement the JTAG multi-chip test function and freely switch between the JTAG standard IEEE STD 1149.1 protocol and 1149.7 protocol on a test board. Summary of the Utility Model

[0004] Some simplifications or omissions may be made in this part, as well as in the abstract and the title of the specification of this application, to avoid obscuring the purpose of this part, the abstract and the title of the specification, and such simplifications or omissions shall not be used to limit the scope of the utility model.

[0005] In view of the problems existing in the above or the prior art, the present utility model is proposed.

[0006] Therefore, the purpose of the present utility model is to provide a CJTAG test board, which aims to solve the existing problems.

[0007] To solve the above technical problems, the present utility model provides the following technical solution: A CJTAG test board includes a controller module, which includes a main controller and a slave controller that are electrically connected to each other; an external control input module, which is respectively connected to the main controller and the slave controller through the JTAG port; an external test function module, which is electrically connected to the controller module; and a power supply module, which provides 3.3V and 1.2V power supplies to the controller module, the external control input module, and the external test function module.

[0008] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the external control input module includes a JTAG connector, and the IDI pins of the JTAG connector are respectively connected to the TDI pins of the main controller and the TDI pins of the slave controller through a first main switch and a first slave switch; the IDO pins of the JTAG connector are respectively connected to the TDO pins of the main controller and the TDO pins of the slave controller through a fourth main switch and a fourth slave switch; the TDO pin of the main controller is connected to the TDI pin of the slave controller through an isolation switch.

[0009] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the ICK pins of the JTAG connector are respectively connected to the TCK pins of the main controller and the TCK pins of the slave controller through a second main switch and a second slave switch; the IMS pins of the JTAG connector are respectively connected to the TMS pins of the main controller and the TMS pins of the slave controller through a third main switch and a third slave switch.

[0010] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the external test function module includes a static random access memory, an analog-to-digital converter, a variable resistor, an electrically erasable programmable read-only memory, a light-emitting diode, and a button; the static random access memory is electrically connected to the slave controller; the electrically erasable programmable read-only memory, the light-emitting diode, and the button are electrically connected to the main controller; one end of the analog-to-digital converter is electrically connected to the variable resistor, and the other end is electrically connected to the main controller.

[0011] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the power supply module includes a first step-down voltage regulator and a second step-down voltage regulator; the first step-down voltage regulator converts the 5V input voltage into 3.3V and outputs it to the static random access memory, the analog-to-digital converter, the variable resistor, the electrically erasable programmable read-only memory, the button, the main controller, and the slave controller; the second step-down voltage regulator converts the 5V input voltage into 1.2V and outputs it to the main controller and the slave controller.

[0012] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the SCL pin and the SDA pin of the electrically erasable programmable read-only memory are respectively connected to the GPIO30 pin and the GPIO31 pin of the first chip of the main controller.

[0013] As a preferred embodiment of the CJTAG test board of the present utility model, wherein: the SCLK pin, the CS pin, the DOUT pin, and the DIN pin of the fifth chip of the analog-to-digital converter are respectively connected to the GPIO05 pin, the GPIO04 pin, the GPIO09 pin, and the GPIO39 pin of the first chip.

[0014] As a preferred solution of the CJTAG test board described in the present utility model, among them: the button is connected to the GPIO29 pin of the first chip.

[0015] Advantages of the present utility model: Compared with the previous test boards of the same type, this CJTAG test board can be configured with richer and more flexible test resources, and can more conveniently test various types of protocol ports or functions. In addition, 2 MCUs are used for configuration, and there are also ports for interconnection between the 2 MCUs. Using this design, multi-chip JTAG testing can be completed on one test board. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0017] Figure 1 is the overall structure diagram of the CJTAG test board described in the present utility model;

[0018] Figure 2 is the circuit schematic diagram of the power supply module of the CJTAG test board described in the present utility model;

[0019] Figure 3 is the circuit schematic diagram of the external control input module and the power input terminal;

[0020] Figure 4 is the circuit schematic diagram of the main controller;

[0021] Figure 5 is the circuit schematic diagram of the static random access memory;

[0022] Figure 6 is the circuit schematic diagram of the electrically erasable programmable read-only memory;

[0023] Figure 7 is the circuit schematic diagram of the adjustable resistor;

[0024] Figure 8 is the circuit schematic diagram of the analog-to-digital converter;

[0025] Figure 9 is the circuit schematic diagram of the button. Detailed Embodiments

[0026] In order to make the above objects, features, and advantages of the present utility model more obvious and understandable, the following will describe the detailed embodiments of the present utility model in conjunction with the drawings of the specification.

[0027] In the following description, many specific details are set forth in order to provide a thorough understanding of the present utility model. However, the present utility model may also be implemented in other ways different from those described herein. Those skilled in the art may make similar extensions without departing from the connotation of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.

[0028] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation manner of the present utility model. The appearances of "in one embodiment" in different places in this specification do not all refer to the same embodiment, nor are they separate or selectively exclusive embodiments from other embodiments.

[0029] Embodiment 1

[0030] Referring to Figures 1-9 , which is the first embodiment of the present utility model. This embodiment provides a CJTAG test board, which includes a controller module 100, including a main controller 101 and a slave controller 102 that are electrically connected to each other; an external control input module 200, which is respectively connected to the main controller 101 and the slave controller 102 through a JTAG port; an external test function module 300, which is electrically connected to the controller module 100; and a power supply module 400, which provides 3.3V and 1.2V power supplies to the controller module 100, the external control input module 200, and the external test function module 300.

[0031] The external control input module 200 includes a JTAG connector 201. The IDI pins of the JTAG connector 201 are respectively connected to the TDI pins of the main controller 101 and the slave controller 102 through a first main switch A1 and a first slave switch B1; the IDO pins of the JTAG connector 201 are respectively connected to the TDO pins of the main controller 101 and the slave controller 102 through a fourth main switch A4 and a fourth slave switch B4; the TDO pin of the main controller 101 is connected to the TDI pin of the slave controller 102 through an isolation switch K.

[0032] The ICK pins of the JTAG connector 201 are respectively connected to the TCK pins of the main controller 101 and the slave controller 102 through a second main switch A2 and a second slave switch B2; the IMS pins of the JTAG connector 201 are respectively connected to the TMS pins of the main controller 101 and the slave controller 102 through a third main switch A3 and a third slave switch B3.

[0033] The components of the controller module 100 are two F280049CPZS modules and their peripheral circuits.

[0034] The components of the external test function module 300 are SRAM, LED, SPI ADC, adjustable resistor, IIC EEPROM, button test port and its peripheral circuits.

[0035] The workflow is divided into three steps: First, obtain the data from the upstream JTAG controller through the port, then the module in the test board processes the original data, and finally, send the data back through the port.

[0036] The specific workflow is as follows:

[0037] In the first step, receive the test instructions and data sent by the upstream JTAG controller through the JTAG port, and the main controller 101 in the test board receives these data.

[0038] In the second step, after the main controller 101 of the test board receives the test instructions and data, it will parse the test instructions to clarify the specific instruction types, specifically the following test instructions: IDcode, Bypass, Sample, and ExTest.

[0039] In the third step, corresponding to different instruction types, perform corresponding operations. For example, the IDcode instruction is to read the IDcode data of the target device, the Bypass instruction is to skip the current device, the Sample instruction is to collect the level status of the target device pins, and the ExTest instruction is to apply a specified level value to the target device pins.

[0040] In the fourth step, return the data to the upstream JTAG controller through the JTAG port.

[0041] Embodiment 2

[0042] Refer to Figures 1-9 , which is the second embodiment of the present invention. The difference from the first embodiment is that this embodiment provides the building process of the test board.

[0043] The external test function module 300 includes a static random access memory SRAM, an analog-to-digital converter SPI ADC, an adjustable resistor, an electrically erasable programmable read-only memory EEPROM, a light-emitting diode LED, and a button BUTTON; the static random access memory SRAM is electrically connected to the slave controller 102; the electrically erasable programmable read-only memory EEPROM, the light-emitting diode LED, and the button BUTTON are electrically connected to the main controller 101; one end of the analog-to-digital converter SPI ADC is electrically connected to the adjustable resistor, and the other end is electrically connected to the main controller 101.

[0044] The SCL pin and SDA pin of the electrically erasable programmable read-only memory EEPROM are respectively connected to the GPIO30 pin and GPIO31 pin of the first chip U1A of the main controller 101.

[0045] The SCLK pin, CS pin, DOUT pin, and DIN pin of the fifth chip U5 of the SPI ADC of the analog-to-digital converter are respectively connected to the GPIO05 pin, GPIO04 pin, GPIO09 pin, and GPIO39 pin of the first chip U1A.

[0046] The button BUTTON is connected to the GPIO29 pin of the first chip U1A.

[0047] The building process is as follows:

[0048] The first step is to build a conversion hardware platform: First, connect the 5V external power input through the external input port, and complete the step-down conversion from 5V to 3.3V and 1.2V through the internal power module to complete the power supply system of this board.

[0049] The second step is to build a JTAG communication platform: Design the main controller 101 and its peripheral circuits, including 2 MCUs, connect the external control input and output module signals to the main controller 101 to complete the construction of the JTAG communication module.

[0050] The third step is to build a JTAG multi-chip function hardware platform: These 2 MCUs can be connected to each other through JTAG signals to complete the construction of the JTAG multi-chip test function.

[0051] The fourth step is to build a multi-functional test platform: The 2 MCUs are respectively connected to external function test modules through their ports, such as SRAM module, EEPROM module, adjustable resistor module, SPI ADC module, and button module, etc., to complete the construction of the multi-functional test environment.

[0052] Embodiment 3

[0053] Refer to Figures 2-8 , which is the third embodiment of the present utility model. Different from the previous two embodiments, this embodiment provides a power module. The power module 400 includes a first step-down converter 401 and a second step-down converter 402; the first step-down converter 401 converts the 5V input voltage into 3.3V and outputs it to the static random access memory SRAM, analog-to-digital converter SPI ADC, adjustable resistor, electrically erasable programmable read-only memory EEPROM, button BUTTON, main controller 101, and slave controller 102; the second step-down converter 402 converts the 5V input voltage into 1.2V and outputs it to the main controller 101 and the slave controller 102.

[0054] The components of the power module 400 are powered by a 5V power supply, and the 3.3V and 1.2V step-down modules are TPS82130SILR.

[0055] Importantly, it should be noted that the construction and arrangement of the present application shown in multiple different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who refer to this disclosure should easily understand that many modifications are possible without materially departing from the novel teachings and advantages of the subject matter described in this application (e.g., changes in the dimensions, scales, structures, shapes, and proportions of various elements, as well as parameter values (such as temperature, pressure, etc.), installation arrangements, use of materials, colors, orientations, etc.). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of the element may be inverted or otherwise changed, and the nature, number, or position of discrete elements may be altered or changed. Accordingly, all such modifications are intended to be included within the scope of the present utility model. The order or sequence of any process or method steps may be changed or reordered according to alternative embodiments. In the claims, any "means-plus-function" clauses are intended to cover the structures that perform the recited functions described herein, and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the exemplary embodiments without departing from the scope of the present utility model. Therefore, the present utility model is not limited to specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0056] In addition, in order to provide a concise description of the exemplary embodiments, not all features of the actual embodiments may be described (i.e., those features that are not relevant to the currently contemplated best mode of carrying out the present utility model or those features that are not relevant to the implementation of the present utility model).

[0057] It should be understood that in the development of any actual implementation, as in any engineering or design project, numerous specific implementation decisions may be made. Such development efforts may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, without undue experimentation, such development efforts will be a routine task of design, manufacturing, and production.

[0058] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model and not to limit them. Although the present utility model has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present utility model may be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present utility model, and all of them should be covered by the scope of the claims of the present utility model.

Claims

1. A CJTAG test board, characterized in that: including, a controller module (100) including a main controller (101) and a slave controller (102) electrically connected to each other; an external control input module (200) connected to the main controller (101) and the slave controller (102) respectively through a JTAG port; an external test function module (300) electrically connected to the controller module (100); a power supply module (400) providing 3.3V and 1.2V power supplies to the controller module (100), the external control input module (200), and the external test function module (300).

2. The CJTAG test board according to claim 1, wherein: The external control input module (200) includes a JTAG connector (201), and the IDI pins of the JTAG connector (201) are connected to the TDI pins of the main controller (101) and the slave controller (102) respectively through a first main switch (A1) and a first slave switch (B1); the IDO pins of the JTAG connector (201) are connected to the TDO pins of the main controller (101) and the slave controller (102) respectively through a fourth main switch (A4) and a fourth slave switch (B4); the TDO pin of the main controller (101) is connected to the TDI pin of the slave controller (102) through an isolation switch (K).

3. The CJTAG test board according to claim 2, characterized in that: the ICK pins of the JTAG connector (201) are connected to the TCK pins of the main controller (101) and the slave controller (102) respectively through a second main switch (A2) and a second slave switch (B2); the IMS pins of the JTAG connector (201) are connected to the TMS pins of the main controller (101) and the slave controller (102) respectively through a third main switch (A3) and a third slave switch (B3).

4. The CJTAG test board according to claim 3, wherein: The external test function module (300) includes a static random access memory (SRAM), an analog-to-digital converter (SPIADC), a variable resistor, an electrically erasable programmable read-only memory (EEPROM), a light-emitting diode (LED), and a button (BUTTON); the static random access memory (SRAM) is electrically connected to the slave controller (102); the electrically erasable programmable read-only memory (EEPROM), the light-emitting diode (LED), and the button (BUTTON) are electrically connected to the main controller (101); one end of the analog-to-digital converter (SPIADC) is electrically linked to the variable resistor, and the other end is electrically connected to the main controller (101).

5. The CJTAG test board according to claim 4, characterized in that: The power supply module (400) includes a first step-down voltage regulator (401) and a second step-down voltage regulator (402); the first step-down voltage regulator (401) converts the 5V input voltage into 3.3V and outputs it to the static random access memory (SRAM), the analog-to-digital converter (SPIADC), the variable resistor, the electrically erasable programmable read-only memory (EEPROM), the button (BUTTON), the main controller (101), and the slave controller (102); The second step-down voltage regulator (402) converts the 5V input voltage into 1.2V and outputs it to the main controller (101) and the slave controller (102).

6. The CJTAG test board according to claim 5, wherein: The SCL pin and the SDA pin of the electrically erasable programmable read-only memory (EEPROM) are respectively connected to the GPIO30 pin and the GPIO31 pin of the first chip (U1A) of the main controller (101).

7. The CJTAG test board according to claim 6, wherein: The SCLK pin, the CS pin, the DOUT pin, and the DIN pin of the fifth chip (U5) of the analog-to-digital converter (SPI ADC) are respectively connected to the GPIO05 pin, the GPIO04 pin, the GPIO09 pin, and the GPIO39 pin of the first chip (U1A).

8. The CJTAG test board according to any one of claims 4-7, characterized in that: The button (BUTTON) is connected to the GPIO29 pin of the first chip (U1A).

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