Control circuit and chip test circuit

Abstract

The utility model discloses a control circuit and a chip test circuit. A rate controller generates a flag signal according to a first control signal, a random number generator generates a random signal according to the flag signal, a loading signal, a seed signal and a reset signal, and a selection circuit selects one of the random signal, an input signal, a zero setting signal and a one setting signal as a second control signal according to a mode signal and outputs the second control signal. Therefore, the precision of flip rate control can be improved, and the stability and the accuracy of chip testing are further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a control circuit and a chip test circuit. Background Art

[0002] In the field of semiconductor chip manufacturing and testing, the high-temperature aging test of chips is an important link to evaluate their long-term reliability and stability. This test method accelerates the aging process of chips by simulating the high-temperature conditions that chips may encounter in the actual working environment, so as to detect potential defects and faults in advance. In the high-temperature aging test, the switching rate, as a key parameter, is of great significance for ensuring the effectiveness and accuracy of the test.

[0003] The switching rate refers to the switching frequency of the internal logic circuit of the chip during the test. There are still some deficiencies in the control of the switching rate in the prior art. If the switching rate is too low, the test process will not be sufficient and potential defects of the chip cannot be fully exposed. If the switching rate is too high, the chip will age rapidly and at the same time, the risk of chip burnout will also increase. Summary of the Utility Model

[0004] In view of this, the purpose of the embodiments of the present utility model is to provide a control circuit and a chip test circuit, which can improve the accuracy of switching rate control, and further improve the stability and accuracy of chip testing.

[0005] In a first aspect, the embodiments of the present utility model provide a control circuit, which includes:

[0006] A rate controller configured to generate a flag signal according to a first control signal;

[0007] A random number generator configured to generate a random signal according to the flag signal, a load signal, a seed signal, and a reset signal;

[0008] A selection circuit configured to select one of the random signal, an input signal, a zero setting signal, and a one setting signal as a second control signal and output it.

[0009] In some embodiments, the selection circuit includes:

[0010] A first multiplexer configured to select one of the input signal and the one setting signal as a first output signal according to the mode signal;

[0011] A second multiplexer configured to select one of the random signal and the zero setting signal as a second output signal according to the mode signal;

[0012] A third multiplexer, configured to select one of the first output signal and the second output signal as the second control signal according to the mode signal and output it.

[0013] In some embodiments, the mode signal includes a first status bit and a second status bit, the first status bit is high level or low level, and the second status bit is high level or low level.

[0014] In some embodiments, the first multiplexer includes:

[0015] A first input terminal, configured to receive an input signal;

[0016] A second input terminal, configured to receive a set-to-one signal;

[0017] A first output terminal, configured to output a first output signal;

[0018] A first selection terminal, configured to control the first output signal output by the first output terminal to be the input signal when the first status bit of the mode signal is low level, and control the first output signal output by the first output terminal to be the set-to-one signal when the first status bit of the mode signal is high level.

[0019] In some embodiments, the second multiplexer includes:

[0020] A third input terminal, configured to receive a set-to-zero signal;

[0021] A fourth input terminal, configured to receive a random signal;

[0022] A second output terminal, configured to output a second output signal;

[0023] A second selection terminal, configured to control the second output signal output by the second output terminal to be the set-to-zero signal when the first status bit of the mode signal is low level, and control the second output signal output by the second output terminal to be the random signal when the first status bit of the mode signal is high level.

[0024] In some embodiments, the third multiplexer includes:

[0025] A fifth input terminal, connected to the first output terminal, configured to receive the first output signal;

[0026] A sixth input terminal, connected to the second output terminal, configured to receive the second output signal;

[0027] A third output terminal, configured to output the second control signal;

[0028] The third selection terminal is configured to control the second control signal output by the third output terminal to be the first output signal when the second state bit of the mode signal is at a low level, and control the second control signal output by the third output terminal to be the second output signal when the second state bit of the mode signal is at a high level.

[0029] In some embodiments, the rate controller includes:

[0030] A first logic circuit configured to generate the (n - i + 1)-th bit of the intermediate signal according to the i-th bit of the first control signal and the low (n - i + 1) bits of the clock signal, where n is the number of bits of the first control signal and i = 1, 2,..., n;

[0031] An OR gate configured to generate the flag signal according to the signals of each bit of the intermediate signal.

[0032] In some embodiments, the random number generator includes:

[0033] A second logic circuit configured to set each bit in the random signal to zero when the reset signal is valid.

[0034] In some embodiments, the random number generator includes:

[0035] A third logic circuit configured to set each bit in the random signal to the value of the seed signal in a cyclic manner when the load signal is valid.

[0036] In some embodiments, the random number generator includes:

[0037] A fourth logic circuit configured to generate the current output random signal by performing an exclusive OR operation on the previous random signal and the feedback signal when the flag signal is valid.

[0038] In a second aspect, an embodiment of the present invention provides a chip test circuit, and the chip test circuit includes:

[0039] The control circuit as described in the first aspect;

[0040] A chip connected to the output terminal of the control circuit.

[0041] The technical solution of the embodiment of the present invention generates a flag signal by a rate controller according to a first control signal, generates a random signal by a random number generator according to the flag signal, a load signal, a seed signal, and a reset signal, and a selection circuit selects one of the random signal, an input signal, a signal for setting to zero, and a signal for setting to one as a second control signal according to a mode signal and outputs it. Thus, the accuracy of flip rate control can be improved, and further the stability and accuracy of chip testing can be improved. Description of the Drawings

[0042] Through the following description of the embodiments of the present utility model with reference to the accompanying drawings, the above and other objects, features, and advantages of the present utility model will become clearer. In the drawings:

[0043] Figure 1 is the circuit diagram of the chip test circuit of the embodiment of the present utility model;

[0044] Figure 2 is the circuit diagram of the control circuit of an embodiment of the present utility model;

[0045] Figure 3 is the circuit diagram of the control circuit of another embodiment of the present utility model. Detailed Embodiments

[0046] The following describes the present utility model based on embodiments, but the present utility model is not limited to these embodiments. In the following detailed description of the present utility model, some specific details are described in detail. Those skilled in the art can fully understand the present utility model without the description of these details. In order to avoid obscuring the essence of the present utility model, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0047] In addition, those of ordinary skill in the art should understand that the accompanying drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0048] At the same time, it should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one component or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or when an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0049] Unless the context clearly requires otherwise, words such as "including" and "comprising" in the entire application document should be interpreted as having an inclusive meaning rather than an exclusive or exhaustive meaning; that is, it is the meaning of "including but not limited to".

[0050] In the description of the present utility model, it should be understood that terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present utility model, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0051] Chip high-temperature aging test (High Temp Operating Life, HTOL) is to run the chip in a high-temperature environment for a long time to simulate the thermal stress and aging process in actual use, so as to evaluate the stability and long-term reliability of the chip in a high-temperature environment. In actual testing, the flip rate is usually controlled by test software or hardware. The test software will send specific test vectors to the chip according to the preset test plan to control the on-off state of its internal logic circuit, so as to achieve the required flip rate. The level of the flip rate directly affects the activation degree and stress level of the internal circuit of the chip. A high flip rate can ensure that the chip undergoes more state transitions during the test, thus more comprehensively exposing potential defects and faults. This is crucial for improving the test coverage and reliability. In the prior art, the flip rate is generally uncontrollable. A high flip rate will generate periodic transient large currents, and the cumulative effect will cause the degradation of material properties. At the same time, local high temperatures will be generated, which will further cause the breaking of material chemical bonds and chip failure. Therefore, the embodiments of the present utility model provide a chip test circuit and a control circuit to achieve controllable flip rate, thereby improving the stability and accuracy of chip testing.

[0052] Figure 1 is the circuit diagram of the chip test circuit according to the embodiment of the present utility model. As Figure 1 shown, the chip test circuit according to the embodiment of the present utility model includes a control circuit 1 and a chip 2. Among them, the chip 2 is connected to the output end of the control circuit 1.

[0053] The control circuit 1 is configured to generate and output a second control signal.

[0054] The chip 2 is configured to operate according to the second control signal.

[0055] Among them, the chip 2 includes a plurality of test modules, and each test module includes a plurality of scan chains. In Figure 1 the illustrated embodiment, taking the number of test modules as M as an example for illustration, they are B1, B2,..., BM respectively.

[0056] Specifically, a chip, also known as an integrated circuit (IC), is an electronic device that integrates multiple electronic components (such as transistors, resistors, capacitors, etc.) and interconnections on a tiny substrate. These components jointly achieve specific circuit functions through complex wiring and logic design. In a chip, flip-flops are just one of many logic units, and they usually work together with other logic gates (such as AND gates, OR gates, NOT gates, etc.), memory units (such as SRAM, DRAM), digital signal processors (DSPs), microcontrollers (MCUs), or more complex processor cores (such as CPUs, GPUs), etc. to achieve complex computing, control, communication, and data processing functions.

[0057] In the high-temperature aging test of a chip, a scan chain is a commonly used design for testability technique. A scan chain is a test technique that connects the flip-flops in a chip into a long string (or several long strings), allowing testers to access and control the state of the flip-flops inside the chip through an external port. This technique greatly simplifies the complexity of testing internal flip-flops and improves the test coverage and efficiency.

[0058] Furthermore, the second control signal is a multi-dimensional vector composed of 0s or 1s, and the dimension of the vector is the same as the number of scan chains. Each bit in the second control signal is output to the corresponding scan chain. That is to say, for each output of the second control signal, each scan chain can receive an input with a value of 0 or 1. At the same time, as described above, a scan chain is formed by connecting multiple flip-flops in series, and the input received by the scan chain is provided to the first flip-flop. The output terminal of the last flip-flop in the scan chain is designated as the scan-out port, which is used to serially shift out the test response data from the scan chain for external test equipment to capture and analyze. According to the preset logic of each scan chain, it is determined what output will be generated under a given input. Furthermore, based on the input and output of the scan chain, it is determined whether the scan chain is working correctly.

[0059] Furthermore, in Figure 1 the illustrated embodiment, each scan chain is configured as a non-compressed scan. Taking B1 as an example, each scan chain includes a decompressor Ba and a compressor Bb. Among them, the decompressor Ba receives the second control signal as the scan input value. When the scan input value is shifted, the decompressor Ba distributes them into multiple scan chains, and the output width of the decompressor is equal to the number of scan chains. Each scan chain transmits the output result to the compressor Bb, and the input width of the compressor Bb is equal to the number of scan chains. The output of the compressor Bb is driven by different combinations of compressors Bb, and the exclusive OR logic is used in combination. The compressor Bb reduces the data captured from a large number of scan chains and improves the test efficiency.

[0060] In the embodiment of the present utility model, the control circuit generates and outputs the second control signal, and the chip operates according to the second control signal, thereby realizing the test of the chip.

[0061] Figure 2 is the circuit diagram of the control circuit of an embodiment of the present utility model. As Figure 2 shown, the control circuit 1 of the embodiment of the present utility model includes a rate controller 11, a random number generator 12, and a selection circuit 13.

[0062] Among them, the rate controller 11 is configured to generate a flag signal fg according to the first control signal fs.

[0063] The random number generator 12 is configured to generate a random signal rand according to the flag signal fg, the load signal load, the seed signal seed, and the reset signal rst.

[0064] The selection circuit 13 is configured to select one of the random signal rand, the input signal cin, the clear signal f0, and the set signal f1 as the second control signal cout and output it.

[0065] In the embodiment of the present utility model, the rate controller generates a flag signal according to the first control signal, the random number generator generates a random signal according to the flag signal, the load signal, the seed signal, and the reset signal, and the selection circuit selects one of the random signal, the input signal, the clear signal, and the set signal as the second control signal and outputs it according to the mode signal. Thus, the accuracy of the flip rate control can be improved, and further the stability and accuracy of the chip test can be improved.

[0066] Figure 3 is the circuit diagram of the control circuit of another embodiment of the present utility model. As Figure 3 shown, the control circuit 1 of the embodiment of the present utility model includes a rate controller 11, a random number generator 12, and a selection circuit 13. As 3 is Figure 2 functionally consistent with, the difference is that, Figure 3 shows a more detailed circuit structure and signals. The following will further describe the control circuit in combination with Figure 2 and Figure 3 for further illustration.

[0067] In this embodiment, the rate controller 11 is configured to generate a flag signal fg according to the first control signal fs. More specifically, the rate controller 11 is configured to generate a flag signal fg according to the first control signal fs and the clock signal clk.

[0068] Among them, the first control signal fs is a flip rate control signal. Specifically, the first control signal fs is an n-bit binary number. n is a positive integer greater than 1.

[0069] The clock signal clk is also an n-bit binary number and gradually increases according to a predetermined clock frequency. Specifically, in the embodiment of the present utility model, the clock signal is generated based on a counter. When the edge of the test clock signal changes from low to high (rising edge) or the edge of the reset signal changes from high to low (falling edge), the clock signal is generated. If the reset signal rst is at a low level (i.e., the reset signal is active low), the counter is cleared. When the load signal load is true (i.e., high level or logically "true"), the counter is also cleared. If the mode signal mode is true (i.e., binary 11 or decimal 3), the clock signal output by the counter increments by 1. Thus, the value of the clock can be incremented in each clock cycle (if the mode condition is satisfied).

[0070] Further, the rate controller 11 includes a first logic circuit 111 and an OR gate 112. Among them, the first logic circuit 111 is configured to generate the (n - i + 1)-th bit of the intermediate signal according to the i-th bit of the first control signal fs and the low (n - i + 1) bits of the clock signal clk, where n is the number of bits of the first control signal and i = 1, 2,..., n. The OR gate 112 is configured to generate the flag signal according to the signals of each bit of the intermediate signal.

[0071] That is to say, the intermediate signal is also n-bit. For the (n - i + 1)-th bit of the intermediate signal, take the value of the i-th bit of the first control signal fs and the value of the low (n - i + 1) bits of the clock signal clk, and generate the (n - i + 1)-th bit of the intermediate signal according to these two values. Specifically, if the value of the i-th bit of the first control signal fs is 1 and the value of the low (n - i + 1) bits of the clock signal clk meets certain conditions, the value of the (n - i + 1)-th bit of the intermediate signal is determined to be 1; otherwise, the value of the (n - i + 1)-th bit of the intermediate signal is 0.

[0072] For example, assume n = 7 and the i-th bit of the intermediate signal is fzi, then:

[0073] When the 7th bit of fs (index is 6 because the index starts from 0) is 1 and the lowest bit of clk (index is 0) is 1, fz1 is set to 1. At this time, i = 7.

[0074] When the 6th bit of fs is 1 and the low two bits of clk (index from 1 to 0) are 10, fz2 is set to 1. At this time, i = 6.

[0075] When the 5th bit of fs is 1 and the low three bits of clk (index from 2 to 0) are 100, fz3 is set to 1. At this time, i = 5.

[0076] When the 4th bit of fs is 1 and the low four bits of clk (index from 3 to 0) are 1000, fz4 is set to 1. At this time, i = 4.

[0077] When the 3rd bit of fs is 1 and the lower 5 bits of clk (indexed from 4 to 0) are 10000, fz5 is set to 1. At this time, i = 3.

[0078] When the 2nd bit of fs is 1 and the lower 6 bits of clk (indexed from 5 to 0) are 100000, fz6 is set to 1. At this time, i = 2.

[0079] When the 1st bit of fs is 1 and the lower 7 bits of clk (indexed from 6 to 0) are 1000000, fz7 is set to 1. At this time, i = 1.

[0080] The inputs of OR gate 112 are the bits of the intermediate signal fz, and the output is the flag signal fg. That is, when any bit of the intermediate signal is 1, the flag signal fg is 1; when all bits of the intermediate signal are 0, the flag signal fg is 0.

[0081] Thus, assuming that the clock signal clk increases from 0000000 to 1111111, if the first control signal fs is 0000001, the flip rate is the lowest, which is 1 / 256; if the first control signal fs is 1111111, the flip rate is the highest, which is 127 / 256, approaching 1 / 2.

[0082] The above first logic circuit can be implemented by a circuit composed of devices such as flip - flops, AND gates, and OR gates. The embodiments of the present invention only provide the functions of the first logic circuit, and the implementation manner of the specific circuit can be set according to the functions.

[0083] In this embodiment, the random number generator 12 is configured to generate a random signal rand according to the flag signal fg, the load signal load, the seed signal seed, and the reset signal rst.

[0084] Among them, the random number generator 12 can implement three functions: reset operation, load operation, and update operation. Correspondingly, the random number generator 12 includes a second logic circuit 121, a third logic circuit 122, and a fourth logic circuit 123. Among them, the second logic circuit 121 is used to implement the reset operation, the third logic circuit 122 is used to implement the load operation, and the fourth logic circuit 123 is used to implement the update operation.

[0085] The second logic circuit 121 is configured to set each bit in the random signal rand to zero when the reset signal rst is valid. That is, for the reset operation, when the reset signal rst is low (low - level effective), the second logic circuit 121 outputs the random signal rand, and the random signal rand is set to all 0s.

[0086] The third logic circuit 122 is configured to set each bit in the random signal rand to the value of the seed signal seed in a cyclic manner when the load signal load is valid. That is, for the loading operation, when the load signal load is high (active high), the third logic circuit 122 outputs the random signal rand, and each bit of the random signal rand is set to the value in the seed signal seed array.

[0087] In some embodiments, the seed signal seed is an 8-bit array, and the value in the seed signal seed is cyclically used to initialize the random signal rand by i % 8.

[0088] The fourth logic circuit 123 is configured to generate the random signal rand according to the flag signal fg and the feedback signal fb. The fourth logic circuit 123 is configured to update the current random signal according to the flag signal fg and the feedback signal fb to obtain the random signal to be output this time. Among them, the feedback signal fb is the output signal of the scan chain. Since the number of bits of the random signal is the same as the number of scan chains and they correspond one by one, the number of bits of the feedback signal is the same as the number of bits of the random signal.

[0089] Specifically, for the update operation, assuming that the random signal is an m-bit signal, since the index of the (i + 1)-th bit is i, the (i + 1)-th bit of the random signal before update is denoted as randt[i], and the (i + 1)-th bit of the random signal after update is denoted as rand[i]. When the flag signal fg is valid:

[0090] For rand[0], the value of randt[m] output last time is used as the value of rand[0].

[0091] For rand[1] to rand[3], if the mode signal mode is true, the value of rand[i] is equal to the value of the exclusive OR operation of randt[i - 1] and fb[i], where fb[i] is the (i + 1)-th bit of the feedback signal fb and the index is i.

[0092] For rand[4] to rand[6], the value of rand[i] is equal to the value of the exclusive OR operation of randt[i - 1] and fb[m - 1], where fb[m - 1] is the m-th bit of the feedback signal fb, that is, the last bit, and the index is m - 1.

[0093] For rand[7] to rand[m - 1], the value of rand[i] is equal to randt[i - 1]. That is, the update is achieved through a shift operation.

[0094] Further, the random number generator 12 is also configured to keep the random signal unchanged in other cases except for the above-mentioned reset, load, and update.

[0095] The above-mentioned second logic circuit, third logic circuit, and fourth logic circuit can be implemented by a circuit composed of devices such as flip-flops, AND gates, and OR gates. The embodiments of the present invention only provide the functions of the above-mentioned logic circuits, and the implementation manners of the specific circuits can be set according to the functions. At the same time, when setting up the circuits, the second logic circuit, third logic circuit, and fourth logic circuit can share some devices, or can be implemented by independent devices respectively. Moreover, since the random number generator needs to select one of the output signals of the second logic circuit, third logic circuit, and fourth logic circuit for output, and needs to keep the random signal unchanged in other cases, the random number generator also includes other devices or circuits other than the second logic circuit, third logic circuit, and fourth logic circuit, which will not be elaborated one by one in the embodiments of the present invention.

[0096] In this embodiment, the selection circuit 13 is configured to select one of the random signal rand, input signal cin, clear signal f0, and set signal f1 as the second control signal cout and output it.

[0097] Specifically, the selection circuit 13 includes a first multiplexer mux1, a second multiplexer mux2, and a third multiplexer mux3. Among them, a multiplexer (MUX, Multiplexer) is a logic circuit that has multiple inputs and one output. It selects one of the inputs as the output according to the selection signal. The multiplexer in the embodiments of the present invention is a 2-input MUX, and the 2-input MUX has a selection signal and two inputs.

[0098] Among them, the selection signals of the first multiplexer mux1, the second multiplexer mux2, and the third multiplexer mux3 are all mode signals. The mode signal is a 2-bit binary number, including four cases, namely 00, 01, 10, and 11. Among them, the high bit is the first status bit mode1, and the low bit is the second status bit mode2. The first status bit is high level or low level, and the second status bit is high level or low level. High level is 1, and low level is 0.

[0099] Among them, the first multiplexer mux1 is configured to select one of the input signal Cin and the set signal f1 as the first output signal according to the mode signal mode.

[0100] The first multiplexer mux1 includes a first input terminal, a second input terminal, a first output terminal, and a first selection terminal. Among them, the first input terminal is configured to receive the input signal Cin. The second input terminal is configured to receive the set-one signal f1. The first output terminal is configured to output a first output signal. The first selection terminal is configured to control the first output signal output by the first output terminal to be the input signal Cin when the first status bit mode1 of the mode signal is at a low level, and to control the first output signal output by the first output terminal to be the set-one signal f1 when the first status bit mode1 of the mode signal is at a high level. Among them, the set-one signal is a binary number with all bits being 1.

[0101] The second multiplexer mux2 is configured to select one of the random signal rand and the reset signal f0 as the second output signal according to the mode signal mode.

[0102] The second multiplexer includes a third input terminal, a fourth input terminal, a second output terminal, and a second selection terminal. Among them, the third input terminal is configured to receive the reset signal f0. The fourth input terminal is configured to receive the random signal rand. The second output terminal is configured to output a second output signal. The second selection terminal is configured to control the second output signal output by the second output terminal to be the reset signal f0 when the first status bit mode1 of the mode signal is at a low level, and to control the second output signal output by the second output terminal to be the random signal rand when the first status bit mode1 of the mode signal is at a high level. The reset signal is a binary number with all bits being 0.

[0103] The third multiplexer mux3 is configured to select one of the first output signal and the second output signal as the second control signal Cout and output it according to the mode signal mode.

[0104] The third multiplexer includes a fifth input terminal, a sixth input terminal, a third output terminal, and a third selection terminal. The third output terminal is the output terminal of the control circuit. The fifth input terminal is connected to the first output terminal and is configured to receive the first output signal. The sixth input terminal is connected to the second output terminal and is configured to receive the second output signal. The third output terminal is configured to output the second control signal Cout. The third selection terminal is configured to control the second control signal output by the third output terminal to be the first output signal when the second status bit mode2 of the mode signal is at a low level, and to control the second control signal output by the third output terminal to be the second output signal when the second status bit mode2 of the mode signal is at a high level.

[0105] That is to say, the selection circuit of the embodiment of the present utility model includes three multiplexers, four inputs, and one selection signal. The three multiplexers are the first multiplexer mux1, the second multiplexer mux2, and the third multiplexer mux3. The four inputs are the random signal rand, the input signal cin, the clear signal f0, and the set signal f1. The one selection signal is the mode signal, which includes four states: 00, 01, 10, and 11. The high bit of the mode signal serves as the selection signal for the first multiplexer mux1 and the second multiplexer mux2, and the low bit of the mode signal serves as the selection signal for the third multiplexer mux3.

[0106] Thus, when the mode signal is 00, the selection circuit 13 outputs the input signal Cin.

[0107] When the mode signal is 01, the selection circuit 13 outputs the clear signal f0.

[0108] When the mode signal is 10, the selection circuit 13 outputs the set signal f1.

[0109] When the mode signal is 11, the selection circuit 13 outputs the random signal rand.

[0110] Thus, the control can achieve the switching of different signals, improving the flexibility of chip testing.

[0111] In the embodiment of the present utility model, the rate controller generates a flag signal according to the first control signal, the random number generator generates a random signal according to the flag signal, the load signal, the seed signal, and the reset signal, and the selection circuit selects one of the random signal, the input signal, the clear signal, and the set signal as the second control signal and outputs it according to the mode signal. Thus, the accuracy of flip rate control can be improved, and further the stability and accuracy of chip testing can be improved.

[0112] It should be understood that the mode signal mode, the input signal Cin, the seed signal seed, the load signal load, the reset signal rst, the first control signal fs, and the clock signal clk of the embodiment of the present utility model are all provided by other modules. The embodiment of the present utility model mainly realizes the functions of the control circuit according to these signals, and the sources of these signals can be realized based on various methods. The embodiment of the present utility model does not limit this.

[0113] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A control circuit, characterized in that, The control circuit includes: A rate controller configured to generate a flag signal according to a first control signal; A random number generator configured to generate a random signal according to the flag signal, a load signal, a seed signal, and a reset signal; A selection circuit configured to select one of the random signal, an input signal, a zero setting signal, and a one setting signal as a second control signal and output it.

2. The control circuit according to claim 1, characterized in that, The selection circuit includes: A first multiplexer configured to select one of the input signal and the one setting signal as a first output signal according to a mode signal; A second multiplexer configured to select one of the random signal and the zero setting signal as a second output signal according to the mode signal; A third multiplexer configured to select one of the first output signal and the second output signal as the second control signal and output it according to the mode signal.

3. The control circuit according to claim 2, wherein The mode signal includes a first status bit and a second status bit, the first status bit is high level or low level, and the second status bit is high level or low level.

4. The control circuit according to claim 3, wherein The first multiplexer includes: A first input terminal configured to receive the input signal; A second input terminal configured to receive the one setting signal; A first output terminal configured to output the first output signal; A first selection terminal configured to control the first output signal output by the first output terminal to be the input signal when the first status bit of the mode signal is low level, and control the first output signal output by the first output terminal to be the one setting signal when the first status bit of the mode signal is high level.

5. The control circuit according to claim 4, wherein, The second multiplexer includes: A third input terminal configured to receive the zero setting signal; A fourth input terminal configured to receive the random signal; A second output terminal configured to output the second output signal; A second selection terminal configured to control the second output signal output by the second output terminal to be the zero setting signal when the first status bit of the mode signal is low level, and control the second output signal output by the second output terminal to be the random signal when the first status bit of the mode signal is high level.

6. The control circuit according to claim 5, wherein The third multiplexer includes: A fifth input terminal connected to the first output terminal and configured to receive the first output signal; A sixth input terminal connected to the second output terminal and configured to receive the second output signal; A third output terminal configured to output the second control signal; A third selection terminal configured to control the second control signal output by the third output terminal to be the first output signal when the second status bit of the mode signal is low level, and control the second control signal output by the third output terminal to be the second output signal when the second status bit of the mode signal is high level.

7. The control circuit according to claim 1, wherein The rate controller includes: A first logic circuit configured to generate the (n - i + 1)-th bit of an intermediate signal according to the i-th bit of the first control signal and the low (n - i + 1) bits of a clock signal, where n is the number of bits of the first control signal and i = 1, 2,..., n; An OR gate configured to generate the flag signal according to the signals of each bit of the intermediate signal.

8. The control circuit according to claim 1, wherein The random number generator includes: A second logic circuit, configured to set each position in the random signal to zero when the reset signal is valid.

9. The control circuit according to claim 1, characterized in that, The random number generator includes: A third logic circuit, configured to set each bit in the random signal to the value of the seed signal in a cyclic manner when the load signal is valid.

10. The control circuit according to claim 1, wherein The random number generator includes: A fourth logic circuit, configured to generate the current output random signal by performing an exclusive OR operation on the previous random signal and the feedback signal when the flag signal is valid.

11. A chip test circuit, characterized in that, The chip test circuit includes: The control circuit according to any one of claims 1-10; A chip, connected to the output end of the control circuit.

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