Impedance matching circuit and voltage stabilizing circuit
By designing impedance matching circuits and conversion circuits, flexible switching of impedance in high-voltage circuits is achieved, and the chip area and cost increase caused by impedance switching in high-voltage circuits is solved, achieving compatibility in multiple application scenarios at a lower cost.
Patent Information
- Application Number
- CN202422360914.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-26
AI Technical Summary
Impedance switching in high-voltage circuits requires controlling switching between two sets of output stages to avoid the overvoltage and current backsinking of MOS tubes, resulting in increased chip area and cost.
An impedance matching circuit is designed, including multiple branches and clamping units. By adjusting the conduction or shutdown of the branch through the control signal and clamping signal, the resistance adjustment of the impedance matching circuit is realized, and the control signal is converted between different voltage domains through the conversion circuit.
It realizes flexible impedance switching in different application scenarios, reduces chip area and cost, and avoids the problems of overvoltage and current backsinking of MOS tubes.
Smart Images
Figure CN223078636U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of integrated circuits, and particularly relates to an impedance matching circuit and a voltage stabilizing circuit. Background Art
[0002] In some circuit applications, it is necessary to adjust the output impedance according to the change of the scenario; however, for high-voltage circuits, impedance switching often needs to be controlled and switched between two reserved output stages to avoid overvoltage and current reverse injection problems of MOS transistors, which consumes a large chip area and thus increases the cost.
[0003] The information disclosed in this background art section is only intended to enhance the overall understanding of the utility model and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Utility Model
[0004] The purpose of the utility model is to provide an impedance matching circuit and a voltage stabilizing circuit, which have a simple structure and can be compatible with multiple application scenarios at a lower cost.
[0005] To achieve the above purpose, a specific embodiment of the utility model provides an impedance matching circuit, including: multiple branches and a clamping unit. The first end of each branch is connected to the output end of the previous-stage circuit, and the second ends of the branches are connected to form a signal output end. At least one branch has a control end and a receiving end. The control end is used to receive a control signal, and the branch realizes its own conduction or cutoff based on the control of the control signal and the signal at the receiving end to adjust the resistance of the impedance matching circuit.
[0006] The clamping unit is used to generate at least one clamping signal based on at least one control signal to clamp the voltage at the receiving end of at least one branch, and the branch realizes its own conduction or cutoff based on the control of the control signal and the clamping signal.
[0007] In one or more embodiments of the utility model, the clamping unit includes multiple clamping branches. Each clamping branch is connected to the corresponding control signal and the receiving end of at least one branch. The clamping branch generates a clamping signal based on the control signal, and each branch realizes its own conduction or cutoff based on the control of the control signal and the clamping signal.
[0008] In one or more embodiments of the present utility model, at least the first branch and the second branch are included in the multiple branches. The first ends of the first branch and the second branch are both connected to the output end of the previous-stage circuit. The second ends of the first branch and the second branch are connected to form a signal output end. The first branch has a first control end for receiving a first control signal and a first receiving end. The first branch realizes its own conduction or cutoff based on the control of the first control signal and the signal of the first receiving end. The second branch has a second control end for receiving a second control signal and a second receiving end. The second branch realizes its own conduction or cutoff based on the control of the second control signal and the signal of the second receiving end.
[0009] In one or more embodiments of the present utility model, the clamping unit is connected to the first receiving end, the second receiving end, the first control signal, and the second control signal. The clamping unit is used to generate a clamping signal based on the first control signal or the second control signal to clamp the voltages of the first receiving end and the second receiving end. The first control signal and the second control signal are inverse signals to each other.
[0010] In one or more embodiments of the present utility model, the clamping unit at least includes a first clamping branch and a second clamping branch. The first clamping branch is connected to the first receiving end, the second receiving end, and the first control signal. The first clamping branch generates a first clamping signal based on the first control signal to clamp the voltages of the first receiving end and the second receiving end. The second clamping branch is connected to the first receiving end, the second receiving end, and the second control signal. The second clamping branch generates a second clamping signal based on the second control signal to clamp the voltages of the first receiving end and the second receiving end.
[0011] In one or more embodiments of the present utility model, the first clamping branch includes a first transistor. The control end of the first transistor is connected to the first receiving end and the second receiving end. The first end of the first transistor is connected to the first control signal; or
[0012] The first clamping branch includes a first transistor and a first voltage module. The control end of the first transistor is connected to the first receiving end and the second receiving end. The first end of the first transistor is connected to the first end of the first voltage module. The second end of the first voltage module is connected to the first control signal. The first voltage module is used to generate a first voltage based on the first control signal.
[0013] In one or more embodiments of the present utility model, the second clamping branch includes a second transistor. The control end of the second transistor is connected to the first receiving end and the second receiving end. The first end of the second transistor is connected to the second control signal; or
[0014] The second clamping branch includes a second transistor and a second voltage module. The control end of the second transistor is connected to the first receiving end and the second receiving end. The first end of the second transistor is connected to the first end of the second voltage module. The second end of the second voltage module is connected to the second control signal. The second voltage module is configured to generate a second voltage based on the second control signal.
[0015] In one or more embodiments of the present invention, the first branch includes a first switching tube. The control end of the first switching tube forms the first control end of the first branch, and the first end of the first switching tube forms the first receiving end of the first branch; and / or
[0016] The second branch includes a second switching tube and one or more load units. The load units are connected in series with the second switching tube. The control end of the second switching tube forms the second control end of the second branch, and the first end of the second switching tube forms the second receiving end of the second branch.
[0017] In one or more embodiments of the present invention, the impedance matching circuit further includes a conversion circuit. The conversion circuit is configured to convert a reference signal in a first voltage domain to generate at least one control signal in a second voltage domain.
[0018] In one or more embodiments of the present invention, the impedance matching circuit further includes a voltage stabilization and protection unit. The first end of the voltage stabilization and protection unit is connected to the power supply voltage, and the second end of the voltage stabilization and protection unit is connected to the receiving end of each branch. The voltage stabilization and protection unit is configured to clamp the minimum voltage of the receiving end.
[0019] The present invention also discloses a voltage stabilization circuit, including a pre-stage circuit and the impedance matching circuit connected to the output end of the pre-stage circuit.
[0020] In one or more embodiments of the present invention, the pre-stage circuit includes a current source, an amplifier, a first resistor, a second resistor, and an output tube. The first input end of the amplifier is connected to the first end of the current source and the first end of the first resistor. The second input end of the amplifier is connected to the first end of the second resistor and the first end of the output tube. The output end of the amplifier is connected to the control end of the output tube. The second end of the current source is connected to the ground voltage. The second end of the first resistor and the second end of the second resistor are connected to the power supply voltage. The second end of the output tube is connected to the impedance matching circuit.
[0021] Compared with the prior art, the impedance matching circuit and the voltage stabilization circuit of the present invention change the output impedance of the pre-stage circuit by selectively connecting different branches into the output path of the pre-stage circuit, so as to flexibly switch between different application requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0023] Figure 1 It is the circuit schematic diagram of the impedance matching circuit and the voltage stabilizing circuit in an embodiment.
[0024] Figure 2 It is the circuit schematic diagram of the conversion circuit in an embodiment. Detailed implementation manners
[0025] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0026] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connections through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connections through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.
[0027] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, in which the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized without departing from the scope of the present disclosure, and structural or logical changes can be made. Therefore, the following detailed description should not be considered limiting.
[0028] The various operations in the specification can be described, in turn, as a number of discrete actions or operations in a manner that is most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0029] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
[0030] Various components and devices may be referred to or shown herein in the singular form (e.g., "transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.
[0031] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc., used with respect to the embodiments of the present disclosure are synonymous.
[0032] As Figure 1 shown, an impedance matching circuit in an embodiment of the present utility model includes: a plurality of branches and a clamping unit, and the conduction of each branch corresponds to a resistance value. The first end of each branch is connected to the output end of the pre-stage circuit, and the second ends of the branches are connected to form a signal output end VOUT. Among them, at least one branch has a control end and a receiving end, the control end is used to receive a control signal, the signal of the receiving end is clamped by the clamping unit, and the branch realizes the conduction or cut-off of the corresponding branch based on the control signal and the signal of the receiving end to adjust the resistance of the impedance matching circuit.
[0033] The pre-stage circuit may be various circuits such as a voltage stabilizing circuit, and the impedance matching circuit is applicable to application circuits with output impedance adjustment and switching.
[0034] The clamping unit generates at least one clamping signal based on at least one control signal to clamp the voltage of the receiving end of at least one branch, and the branch realizes its own controlled conduction or cut-off based on the control signal and the clamping signal.
[0035] The clamping unit includes a plurality of clamping branches. Each clamping branch is connected to a corresponding control signal and the receiving end of at least one branch. The clamping branch generates a clamping signal based on the control signal, and each branch realizes its own conduction or cutoff based on the control of the control signal and the clamping signal.
[0036] In one embodiment, the number of branches can be selected as needed, and the number of clamping branches can also be selected as needed. The number of branches and the number of clamping branches can be equal. All branches have corresponding control ends and receiving ends. Then all control ends receive corresponding control signals. Each clamping branch can select one or more control signals from multiple control signals as reference signals to generate corresponding one or more clamping signals. By these clamping signals and the corresponding control signals, the number of conducting branches is controlled, so that the overall resistance value of the impedance matching circuit can be adjusted. In other embodiments, one or more branches can be set as branches that are not controlled by signals, and this branch has a fixed resistance value.
[0037] In addition, the impedance matching circuit further includes a conversion circuit, and the conversion circuit is used to convert a reference signal in the first voltage domain to generate at least one control signal in the second voltage domain.
[0038] In Figure 1 In an example shown, there are two branches, namely the first branch 10 and the second branch 20. The first end of the first branch 10 and the first end of the second branch 20 are both connected to the output end of the previous-stage circuit, and the second end of the first branch 10 and the second end of the second branch 20 are connected to form a signal output end.
[0039] The first branch 10 has a first control end for receiving a first control signal SWB_H and a first receiving end. The first branch 10 realizes its own conduction or cutoff based on the control of the first control signal SWB_H and the signal of the first receiving end. The second branch 20 has a second control end for receiving a second control signal SW_H and a second receiving end. The second branch 20 realizes its own conduction or cutoff based on the control of the second control signal SW_H and the signal of the second receiving end.
[0040] The clamping unit 30 is connected to the first receiving end, the second receiving end, the first control signal SWB_H, and the second control signal SW_H. The clamping unit 30 is used to generate a clamping signal based on the first control signal SWB_H or the second control signal SW_H to clamp the voltages of the first receiving end and the second receiving end. The first control signal SWB_H and the second control signal SW_H are inverse-phase signals to each other.
[0041] As Figure 1As shown, the clamping unit 30 includes at least a first clamping branch 31 and a second clamping branch 32. The first clamping branch 31 is connected to the first receiving end, the second receiving end, and the first control signal SWB_H. The first clamping branch 31 generates a first clamping signal based on the first control signal SWB_H to clamp the voltages of the first receiving end and the second receiving end. The second clamping branch 32 is connected to the first receiving end, the second receiving end, and the second control signal SW_H. The second clamping branch 32 generates a second clamping signal based on the second control signal SW_H to clamp the voltages of the first receiving end and the second receiving end.
[0042] Among them, the first clamping branch 31 includes a first transistor Ma and a first voltage module. The control end of the first transistor Ma is connected to the first receiving end and the second receiving end. The first end of the first transistor Ma is connected to the first end of the first voltage module. The second end of the first transistor Ma is connected to the power supply voltage AVDD. The second end of the first voltage module is connected to the first control signal SWB_H. The first voltage module is used to generate a first voltage based on the first control signal SWB_H. In other embodiments, the first voltage module may not be provided.
[0043] The first voltage module may be composed of one or more MOS transistors. The multiple MOS transistors are connected in series with each other. The control end of each MOS transistor is connected to the second end of the MOS transistor. In one embodiment, two MOS transistors are provided, namely the first MOS transistor Ma1 and the second MOS transistor Ma2. The control end of the first MOS transistor Ma1 is connected to the second end of the first MOS transistor Ma1 and the first end of the first transistor Ma. The control end of the second MOS transistor Ma2 is connected to the second end of the second MOS transistor Ma2 and the first end of the first MOS transistor Ma1. The first end of the second MOS transistor Ma2 is used to receive the first control signal SWB_H. It can be seen that the number of MOS transistors determines the magnitude of the first voltage. In other embodiments, the first voltage module may also be composed of one or more diodes. The multiple diodes are connected in series with each other. By changing the number of diodes, the magnitude of the first voltage can also be changed. Or the first voltage module may also be other circuit structures that can generate the first voltage based on the first control signal SWB_H.
[0044] The second clamping branch 32 includes a second transistor Mb and a second voltage module. The control end of the second transistor Mb is connected to the first receiving end and the second receiving end. The first end of the second transistor Mb is connected to the first end of the second voltage module. The second end of the second transistor Mb is connected to the power supply voltage AVDD. The second end of the second voltage module is connected to the second control signal SW_H. The second voltage module is used to generate a second voltage based on the second control signal SW_H. In other embodiments, the second voltage module may not be provided.
[0045] The second voltage module may be composed of one or more MOS transistors, and the multiple MOS transistors are connected in series with each other. The control terminal of each MOS transistor is connected to the second terminal of the MOS transistor. In one embodiment, two MOS transistors are provided, namely the third MOS transistor Mb1 and the fourth MOS transistor Mb2. The control terminal of the third MOS transistor Mb1 is connected to the second terminal of the third MOS transistor Mb1 and the first terminal of the second transistor Mb. The control terminal of the fourth MOS transistor Mb2 is connected to the second terminal of the fourth MOS transistor Mb2 and the first terminal of the third MOS transistor Mb1. The first terminal of the fourth MOS transistor Mb2 is used to receive the second control signal SW_H. It can be seen that the number of MOS transistors determines the magnitude of the second voltage. In other embodiments, the second voltage module may also be composed of one or more diodes, and the multiple diodes are connected in series with each other. By changing the number of diodes, the magnitude of the first voltage can also be changed. Or the first voltage module may also be other circuit structures that can generate the second voltage based on the second control signal SW_H.
[0046] In one embodiment, the first branch 10 includes a first switching transistor M1, and the first switching transistor M1 is a high-voltage-resistant transistor. The control terminal of the first switching transistor M1 forms the first control terminal of the first branch 10 to receive the first control signal SWB_H. The first terminal of the first switching transistor M1 forms the first receiving terminal of the first branch 10 and at the same time forms the first terminal of the first branch 10. The second terminal of the first switching transistor M1 forms the second terminal of the first branch 10.
[0047] The second branch 20 includes a second switching transistor M2 and one or more load units, and the second switching transistor M2 is a high-voltage-resistant transistor. The load units are connected in series with the second switching transistor M2. The control terminal of the second switching transistor M2 forms the second control terminal of the second branch 20. The first terminal of the second switching transistor M2 forms the second receiving terminal of the second branch 20. In one example, one load unit Rp is provided, and the load unit Rp is a resistor. The first terminal of the load unit Rp is connected to the second terminal of the second switching transistor M2. The second terminal of the load unit Rp forms the second terminal of the second branch 20. The first terminal of the second switching transistor M2 forms the second receiving terminal of the second branch 20 and forms the first terminal of the second branch. The number of load units can be increased or decreased as needed. When the second switching transistor M2 is turned on, the number of load units determines the total resistance value of the second branch 20. In other embodiments, the load unit Rp can not only be a resistor, but also other types of components or circuit structures such as inductors, capacitors, or the series-parallel connections between various components or circuit structures, so as to not only change the output impedance, but also change into other output characteristics.
[0048] by Figure 1As can be seen, the first receiving end of the first branch 10 is connected to the second receiving end of the second branch 20. In other embodiments, the positions of the second switching transistor M2 and the load unit Rp can be swapped. At this time, the first end of the second switching transistor M2 used as the second receiving end of the second branch 20 will also change. Alternatively, without considering the change in the position of the second switching transistor M2, the first end and the second receiving end of the second branch 20 are always the same node. That is, the first end and the second receiving end of the second branch 20 can both be connected to one end of the load unit Rp.
[0049] The impedance matching circuit further includes a voltage stabilizing and protecting unit. The first end of the voltage stabilizing and protecting unit is connected to the power supply voltage AVDD, and the second end of the voltage stabilizing and protecting unit is connected to the receiving end of each branch. The voltage stabilizing and protecting unit is used to clamp the minimum voltage of the receiving end.
[0050] As Figure 1 shown, in one embodiment, the voltage stabilizing and protecting unit includes a zener diode D1. The cathode of the zener diode D1 is connected to the power supply voltage AVDD, and the anode of the zener diode D1 is connected to the first receiving end of the first branch 10 and the second receiving end of the second branch 20. When the latch up or electrostatic discharge (ESD) occurs in the circuit, resulting in the voltage of the first receiving end of the first branch 10 and the second receiving end of the second branch 20 being pulled down too low, the voltage of the first receiving end of the first branch 10 and the second receiving end of the second branch 20 is clamped by the zener diode D1, so that the voltage difference between the power supply voltage AVDD and the voltage of the first receiving end of the first branch 10 and the second receiving end of the second branch 20 is stabilized at the voltage stabilizing value of the zener diode D1, ensuring the minimum voltage of the first receiving end of the first branch 10 and the second receiving end of the second branch 20, thereby protecting the circuit. In other embodiments, the voltage stabilizing and protecting unit can also be a protection circuit with other structures.
[0051] As Figure 2 shown, the conversion circuit is used to convert the reference signal SW in the first voltage domain to generate the first control signal SWB_H and the second control signal SW_H in the second voltage domain. The first voltage domain is a low voltage domain, and the second voltage domain is a high voltage domain. That is, the reference signal SW is generated based on the low power supply voltage AVDDL, and the first control signal SWB_H and the second control signal SW_H are generated based on the high power supply voltage AVDD.
[0052] The conversion circuit includes a first inverter U1, a second inverter U2, a first level shift circuit Levelshift1, and a second level shift circuit Levelshift2. The first level shift circuit Levelshift1 and the second level shift circuit Levelshift2 are both connected to the power supply voltage AVDD. The input terminal of the first inverter U1 is used to receive a reference signal SW. The output terminal of the first inverter U1 is connected to the input terminal of the second inverter U2 and the input terminal of the second level shift circuit Levelshift2. The output terminal of the second inverter U2 is connected to the input terminal of the first level shift circuit Levelshift1. The output terminal of the first level shift circuit Levelshift1 is used to output a second control signal SW_H, and the output terminal of the second level shift circuit Levelshift2 is used to output a first control signal SWB_H. In an embodiment, the first control signal SWB_H and the second control signal SW_H are inverse signals to each other. The reference signal SW is in a low voltage domain, and the first control signal SWB_H and the second control signal SW_H are in a high voltage domain. It can be considered that when the first control signal SWB_H and the second control signal SW_H are at a high level, they are equal to the power supply voltage AVDD.
[0053] In an embodiment, the output transistor MO, the first switching transistor M1, and the second switching transistor M2 are P-channel MOS transistors; the first transistor Ma, the first MOS transistor Ma1, the second MOS transistor Ma2, the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 are N-channel MOS transistors. In other embodiments, the output transistor MO, the first switching transistor M1, and the second switching transistor M2 can be N-channel MOS transistors; the first transistor Ma, the first MOS transistor Ma1, the second MOS transistor Ma2, the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 can be P-channel MOS transistors.
[0054] The first ends of the output transistor MO, the first switching transistor M1, the second switching transistor M2, the first transistor Ma, the first MOS transistor Ma1, the second MOS transistor Ma2, the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 are source electrodes; the second ends of the output transistor MO, the first switching transistor M1, the second switching transistor M2, the first transistor Ma, the first MOS transistor Ma1, the second MOS transistor Ma2, the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 are drain electrodes; the control ends of the output transistor MO, the first switching transistor M1, the second switching transistor M2, the first transistor Ma, the first MOS transistor Ma1, the second MOS transistor Ma2, the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 are gate electrodes.
[0055] When the reference signal SW is at a low level, the second control signal SW_H is also at a logical low level, and the first control signal SWB_H is at a logical high level. At this time, the voltages at the first receiving end of the first branch 10 and the second receiving end of the second branch 20 are clamped to the second clamping signal, and the second clamping signal is equal to the sum of the voltages between the control end and the first end of the second transistor Mb, between the control end and the first end of the third MOS transistor Mb1, and between the control end and the first end of the fourth MOS transistor Mb2 of the second control signal SW_H. At this time, the first switching transistor M1 is turned off, the second switching transistor M2 is turned on, and the output impedance Rout of the signal output terminal VOUT is connected in series with the load unit Rp on the basis of the original resistance R0 of the pre-stage circuit (assuming that the on-resistance of the switching transistor is very small and can be ignored), that is, the output impedance Rout = R0 + Rp.
[0056] When the reference signal SW is at a high level, the second control signal SW_H is at a logic high level, and the first control signal SWB_H is at a logic low level. At this time, the voltages at the first receiving end of the first branch 10 and the second receiving end of the second branch 20 are clamped to the first clamping signal, and the first clamping signal is equal to the sum of the voltage between the control end and the first end of the first transistor Ma, the voltage between the control end and the first end of the first MOS transistor Ma1, and the voltage between the control end and the first end of the second MOS transistor Ma2. At this time, the first switching transistor M1 is turned on, and the second switching transistor M2 is turned off. The output impedance Rout of the signal output terminal VOUT is connected in series with the on-resistance of the first switching transistor M1 on the basis of the original resistance R0 of the pre-stage circuit (assuming that the on-resistance of the switching transistor is very small and can be ignored), that is, the output impedance Rout = R0.
[0057] It can be seen that in the case of setting two branches and two clamping branches, it can be considered that each branch is controlled by a corresponding clamping branch, and the control signal corresponding to the clamping branch that plays a role is the same as the control signal corresponding to the conducting branch. For example, when the first branch 10 is conducting, the first branch 10 is controlled by the first control signal SWB_H and the first clamping signal. At this time, the first clamping branch 31 plays a role, and the first clamping signal is also generated by the first clamping branch 31 based on the first control signal SWB_H.
[0058] In one embodiment, the first clamping signal generated by the series connection of the first transistor Ma, the first MOS transistor Ma1, and the second MOS transistor Ma2 determines the minimum value that the first control signal SWB_H can be set to, so as to ensure on the one hand that the first switching transistor M1 of the first branch 10 can be turned on within the voltage variation range of the output end of the pre-stage circuit, and on the other hand, to protect the voltage difference between the gate and the source of the first switching transistor M1 to be less than the maximum withstand voltage of the device, avoiding damage to the device. Similarly, the second clamping signal generated by the series connection of the second transistor Mb, the third MOS transistor Mb1, and the fourth MOS transistor Mb2 determines the minimum value that the second control signal SW_H can be set to, so as to ensure on the one hand that the second switching transistor M2 of the second branch 20 can be turned on within the voltage variation range of the output end of the pre-stage circuit, and on the other hand, to protect the voltage difference between the gate and the source of the second switching transistor M2 to be less than the maximum withstand voltage of the device, avoiding damage to the device.
[0059] As Figure 1 shown, the present invention also discloses a voltage stabilizing circuit, including a pre-stage circuit and an impedance matching circuit connected to the output terminal OUT of the pre-stage circuit.
[0060] The pre-stage circuit includes a current source A1, an amplifier CMP, a first resistor R1, a second resistor R2, and an output transistor MO. Due to the voltage division of the impedance matching circuit, the output transistor MO can be set as a low-voltage transistor, but the first switching transistor M1 and the second switching transistor M2 need to be set as high-voltage-resistant transistors. The first input terminal of the amplifier CMP is connected to the first terminal of the current source A1 and the first terminal of the first resistor R1. The second input terminal of the amplifier CMP is connected to the first terminal of the second resistor R2 and the first terminal of the output transistor MO. The output terminal of the amplifier CMP is connected to the control terminal of the output transistor MO. The second terminal of the current source A1 is connected to the ground voltage. The second terminals of the first resistor R1 and the second resistor R2 are connected to the power supply voltage. The second terminal of the output transistor MO is connected to the impedance matching circuit.
[0061] When the first switching transistor M1 is turned off and the second switching transistor M2 is turned on, the output impedance Rout of the signal output terminal VOUT is connected in series with the load unit Rp on the basis of the original equivalent output resistance R0 of the pre-stage circuit (assuming that the on-resistance of the switching transistor is very small and can be ignored), that is, the output impedance Rout = R0 + Rp.
[0062] When the first switching transistor M1 is turned on and the second switching transistor M2 is turned off, the output impedance Rout of the signal output terminal VOUT is connected in series with the on-resistance of the first switching transistor M1 on the basis of the original equivalent output resistance R0 of the pre-stage circuit (assuming that the on-resistance of the switching transistor is very small and can be ignored), that is, the output impedance Rout = R0.
[0063] Under the high-voltage power supply voltage AVDD, by controlling and switching the switching transistors, different resistors are connected in series to the output terminal of the pre-stage circuit, so as to flexibly switch between different output impedance applications to meet different requirements.
[0064] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present utility model. Any reference signs in the claims should not be regarded as limiting the claimed rights.
[0065] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only includes an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. An impedance matching circuit, characterized in that, Including: Multiple branches, the first end of each branch is connected to the output end of the previous-stage circuit, the second ends of the branches are connected to form a signal output end, at least one branch has a control end and a receiving end, the control end is used to receive a control signal, and the branch realizes its own conduction or cutoff based on the control of the control signal and the signal at the receiving end to adjust the resistance of the impedance matching circuit; The impedance matching circuit further includes a clamping unit, and the clamping unit is used to generate at least one clamping signal based on at least one control signal to clamp the voltage at the receiving end of at least one branch, and the branch realizes its own conduction or cutoff based on the control of the control signal and the clamping signal.
2. The impedance matching circuit according to claim 1, wherein The clamping unit includes multiple clamping branches, each clamping branch is connected to the corresponding control signal and the receiving end of at least one branch, the clamping branch generates a clamping signal based on the control signal, and each branch realizes its own conduction or cutoff based on the control of the control signal and the clamping signal.
3. The impedance matching circuit according to claim 1, wherein At least the first branch and the second branch are included in the multiple branches, the first end of the first branch and the first end of the second branch are both connected to the output end of the previous-stage circuit, the second end of the first branch and the second end of the second branch are connected to form a signal output end, the first branch has a first control end for receiving a first control signal and a first receiving end, the first branch realizes its own conduction or cutoff based on the control of the first control signal and the signal at the first receiving end, the second branch has a second control end for receiving a second control signal and a second receiving end, and the second branch realizes its own conduction or cutoff based on the control of the second control signal and the signal at the second receiving end.
4. The impedance matching circuit according to claim 3, characterized in that, The clamping unit is connected to the first receiving end, the second receiving end, the first control signal and the second control signal, and the clamping unit is used to generate a clamping signal based on the first control signal or the second control signal to clamp the voltages at the first receiving end and the second receiving end, and the first control signal and the second control signal are anti-phase signals to each other.
5. The impedance matching circuit according to claim 3, wherein The clamping unit at least includes a first clamping branch and a second clamping branch, the first clamping branch is connected to the first receiving end, the second receiving end and the first control signal, the first clamping branch generates a first clamping signal based on the first control signal to clamp the voltages at the first receiving end and the second receiving end, the second clamping branch is connected to the first receiving end, the second receiving end and the second control signal, and the second clamping branch generates a second clamping signal based on the second control signal to clamp the voltages at the first receiving end and the second receiving end.
6. The impedance matching circuit according to claim 5, wherein The first clamping branch includes a first transistor, the control end of the first transistor is connected to the first receiving end and the second receiving end, and the first end of the first transistor is connected to the first control signal; or The first clamping branch includes a first transistor and a first voltage module, the control end of the first transistor is connected to the first receiving end and the second receiving end, the first end of the first transistor is connected to the first end of the first voltage module, the second end of the first voltage module is connected to the first control signal, and the first voltage module is used to generate a first voltage based on the first control signal.
7. The impedance matching circuit according to claim 5, wherein The second clamping branch includes a second transistor, the control terminal of the second transistor is connected to the first receiving terminal and the second receiving terminal, and the first terminal of the second transistor is connected to the second control signal; or The second clamping branch includes a second transistor and a second voltage module, the control terminal of the second transistor is connected to the first receiving terminal and the second receiving terminal, the first terminal of the second transistor is connected to the first terminal of the second voltage module, the second terminal of the second voltage module is connected to the second control signal, and the second voltage module is configured to generate a second voltage based on the second control signal.
8. The impedance matching circuit according to claim 3, wherein The first branch includes a first switching transistor, the control terminal of the first switching transistor forms the first control terminal of the first branch, and the first terminal of the first switching transistor forms the first receiving terminal of the first branch; and / or The second branch includes a second switching transistor and one or more load units, the load units are connected in series with the second switching transistor, the control terminal of the second switching transistor forms the second control terminal of the second branch, and the first terminal of the second switching transistor forms the second receiving terminal of the second branch.
9. The impedance matching circuit according to claim 1, wherein The impedance matching circuit further includes a conversion circuit, and the conversion circuit is configured to convert a reference signal in the first voltage domain to generate at least one control signal in the second voltage domain.
10. The impedance matching circuit according to claim 1, characterized in that, The impedance matching circuit further includes a voltage stabilizing and protecting unit, the first terminal of the voltage stabilizing and protecting unit is connected to the power supply voltage, the second terminal of the voltage stabilizing and protecting unit is connected to the receiving terminal of each branch, and the voltage stabilizing and protecting unit is configured to clamp the minimum voltage of the receiving terminal.
11. A voltage stabilizing circuit, characterized in that, Comprising a pre-stage circuit and the impedance matching circuit according to any one of claims 1 to 10 connected to the output terminal of the pre-stage circuit.
12. The voltage stabilizing circuit according to claim 11, characterized in that, The pre-stage circuit includes a current source, an amplifier, a first resistor, a second resistor, and an output transistor, the first input terminal of the amplifier is connected to the first terminal of the current source and the first terminal of the first resistor, the second input terminal of the amplifier is connected to the first terminal of the second resistor and the first terminal of the output transistor, the output terminal of the amplifier is connected to the control terminal of the output transistor, the second terminal of the current source is connected to the ground voltage, the second terminals of the first resistor and the second resistor are connected to the power supply voltage, and the second terminal of the output transistor is connected to the impedance matching circuit.