TYPE-C port logic detection circuit

Abstract

The utility model discloses a TYPE-C port logic detection circuit. The TYPE-C port logic detection circuit comprises a USB device end, a Type-c interface, a switch IC circuit, an MOS tube Q1 circuit and an MOS tube Q2 circuit, the CCRP / RDEN signal end of the USB equipment end is respectively connected with the corresponding ends of the switch IC circuit, the MOS tube Q1 circuit and the MOS tube Q2 circuit; the corresponding end of the MOS tube Q1 circuit is electrically connected with the CC1 pin of the Type-c interface and the corresponding end of the switch IC circuit. The circuit corresponding end of the MOS tube Q2 is electrically connected with the CC2 pin of the Type-c interface and the circuit corresponding end of the switch IC. According to the utility model, the USB 2.0 mobile equipment product can realize CC logic detection and control of the Type-C port and supports a DRP function on the premise that expensive and complex circuit design of a PD chip is not added and a large amount of time is not spent on software drive development.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and particularly relates to a TYPE-C port logic detection circuit. Background Art

[0002] With the rapid development of portable electronic devices, the Universal Serial Bus (USB) interface has become the mainstream interface for data transmission and power supply in electronic devices. In particular, the USB Type-C interface, with its features of supporting plugging in either way, high-speed data transmission, and high-power power supply, has been widely used in devices such as smart phones, laptops, and tablets.

[0003] Although the USB Type-C interface offers many advantages, many existing USB devices still adopt the USB 2.0 standard and have the USB On-The-Go (OTG) function, allowing the device to switch between the USB host and slave roles. These devices face challenges when upgrading from the traditional micro USB interface to the USB Type-C interface. To support connections with various Type-C devices, such as Type-C adapters, laptops, headphones, mobile phones, etc., it is usually necessary to integrate a USB Power Delivery (PD) chip, which not only involves complex circuit design but also requires a large amount of software development work to implement the Dual Role Port (DRP) function, including automatically identifying the type of connected device and charging and discharging through the Type-C interface.

[0004] For most small portable consumer electronic products, these USB 2.0 devices that only support the OTG function usually do not require high-current charging or frequent switching of the data transmission direction. Therefore, in order to simplify the process of upgrading these devices to the Type-C interface and reduce costs and development time, manufacturers often choose a fixed role setting: by connecting the CC line of the Type-C interface to VBUS through a pull-up resistor, the device defaults as the host; or by connecting it to GND through a pull-down resistor, the device defaults as the slave. Although this design choice simplifies the circuit design, it also sacrifices the implementation of the DRP function and limits the flexibility and compatibility of the device.

[0005] In addition, the USB Type-C interface usually relies on complex circuit design to support USB PD and data transmission functions. For example, by using multiple N-channel enhancement MOS transistors to design two paths, the switching of the two states of pulling up RP or pulling down Rd on the CC pin is realized to detect the device connection state on the USB Type-C interface. However, this method has limitations, especially in dealing with the problem of inability to charge when the battery is completely depleted, which limits the charging and data transmission capabilities of the device under low-power conditions. Summary of the Invention

[0006] In view of the problems existing in the prior art, the present utility model provides a TYPE-C port logic detection circuit.

[0007] In order to achieve the above object, the technical solution of the present utility model is as follows:

[0008] The present utility model provides a TYPE-C port logic detection circuit, including:

[0009] A USB device end, a Type-c interface, a switch IC circuit, a MOS transistor Q1 circuit, and a MOS transistor Q2 circuit;

[0010] The CC_RP / RD_EN signal terminals of the USB device end are respectively connected to the corresponding terminals of the switch IC circuit, the MOS transistor Q1 circuit, and the MOS transistor Q2 circuit;

[0011] The corresponding terminal of the MOS transistor Q1 circuit is also electrically connected to the CC1 pin of the Type-c interface and the corresponding terminal of the switch IC circuit; the corresponding terminal of the MOS transistor Q2 circuit is also electrically connected to the CC2 pin of the Type-c interface and the corresponding terminal of the switch IC circuit; wherein, the MOS transistor Q1 circuit and the MOS transistor Q2 circuit are used to conduct when a high level is output at the CC_RP / RD_EN signal terminal, so as to output a high level to the CC1 pin and the CC2 pin; the switch IC circuit is used to conduct the CC1 pin and the CC2 pin when a low level is output at the CC_RP / RD_EN signal terminal or no power is supplied.

[0012] Preferably, one path of the CC_RP / RD_EN signal terminal of the USB device end is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q1 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC1 pin of the Type-c interface.

[0013] Preferably, one path of the CC_RP / RD_EN signal terminal of the USB device end is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q2 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC2 pin of the Type-c interface.

[0014] Preferably, the switch IC circuit includes a switch IC, and the model of the switch IC is RS553YUC9.

[0015] Preferably, the MOS transistor Q1 circuit includes a MOS transistor Q1, a diode D02, a diode D04, and a resistor R47; the gate of the MOS transistor Q1 is respectively connected to the MOS transistor Q2 circuit, the corresponding end of the switch IC, and the CC_RP / RD_EN signal terminal. The drain of the MOS transistor Q1 is respectively connected to the first end of the diode D02 and the first end of the diode D04. The second end of the diode D02 is connected to the VDD_3V3 power supply terminal of the USB device through the resistor R47. The second end of the diode D04 is correspondingly connected to the USB_ID terminal. The source of the MOS transistor Q1 is electrically connected to the CC1 pin and the corresponding end of the switch IC.

[0016] Preferably, the MOS transistor Q2 circuit includes a MOS transistor Q2, a diode D01, a diode D03, and a resistor R46; the gate of the MOS transistor Q2 is correspondingly connected to the gate of the MOS transistor Q1. The drain of the MOS transistor Q2 is respectively connected to the first end of the diode D03 and the first end of the diode D01. The second end of the diode D01 is connected to the VDD_3V3 power supply terminal of the USB device and the second end of the resistor R46 through the resistor R46. The second end of the diode D03 is correspondingly connected to the second end of the diode D04 and the USB_ID terminal. The source of the MOS transistor Q2 is electrically connected to the CC2 pin and the corresponding end of the switch IC.

[0017] Preferably, the V-BUS power line terminal of the USB device is also connected to the V-BUS power line terminal of the Type-c interface.

[0018] Preferably, the TYPE-C port logic detection circuit further includes an overvoltage and overcurrent protection circuit. The V-BUS power line terminal of the USB device is connected to the V-BUS power line terminal of the Type-c interface through the overvoltage and overcurrent protection circuit.

[0019] The overvoltage and overcurrent protection circuit includes an overvoltage and overcurrent protection chip, a diode TVS1, a capacitor C101, a capacitor C102, a capacitor C103, and a capacitor C104. The OUT terminal of the overvoltage and overcurrent protection chip is respectively connected to the first end of the capacitor C104, the first end of the capacitor C103, and the V-BUS power line terminal of the USB device. The VIN terminal of the overvoltage and overcurrent protection chip is respectively connected to the first end of the capacitor C102, the first end of the capacitor C101, the first end of the diode TVS1, and the V-BUS power line terminal of the Type-c interface. The second ends of the diode TVS1, the capacitor C101, the capacitor C102, the capacitor C103, and the capacitor C104 are all grounded.

[0020] Preferably, the USB_DN signal terminal of the USB device end is connected to the DN1 and DN2 pins of the Type-c interface through the resistor R17.

[0021] Preferably, the USB_DP signal terminal of the USB device end is connected to the DP1 and DP2 pins of the Type-c interface through the resistor R18.

[0022] Adopting the technical solution of the present utility model has the following beneficial effects:

[0023] The technology of this application takes into account the DRP (Dual Role Port) function of the USB Type-C interface, allowing the device to dynamically switch between USB host and device without the need for additional PD chips and complex circuit designs. This not only improves the compatibility and flexibility of the USB device, but also reduces costs and development difficulties.

[0024] The present utility model simplifies the circuit design by using specific MOS transistors and switch ICs, without the need for additional integration of complex PD chips, thereby reducing the design difficulty and cost. Due to eliminating the dependence on PD chips, the present utility model reduces the workload of software development and hardware debugging, and reduces the overall development cost.

[0025] This application realizes the device detection and charging functions in the case of completely depleted battery through an innovative circuit design, using specific MOS transistors and switch ICs, and optimized control logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the circuit diagram of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present utility model, and should not be construed as a limitation of the present utility model.

[0028] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model.

[0029] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.

[0030] In the present utility model, unless otherwise clearly specified and defined, the terms such as "mounted", "connected", "connected to", "fixed" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0031] In the present utility model, unless otherwise clearly specified and defined, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over" and "on the top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "beneath" and "under the bottom of" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0032] Refer to Figure 1 , the present utility model adopts a TYPE-C port logic detection circuit, including: a USB device end 100, a Type-c interface 200, a switch IC circuit 300, a MOS transistor Q1 circuit, and a MOS transistor Q2 circuit;

[0033] The CC_RP / RD_EN signal terminals of the USB device end 100 are respectively connected to the corresponding terminals of the switch IC circuit 300, the MOS transistor Q1 circuit, and the MOS transistor Q2 circuit;

[0034] The corresponding terminals of the MOS transistor Q1 circuit are also respectively electrically connected to the CC1 pin of the Type-c interface 200 and the corresponding terminals of the switch IC circuit 300; the corresponding terminals of the MOS transistor Q2 circuit are also respectively electrically connected to the CC2 pin of the Type-c interface 200 and the corresponding terminals of the switch IC circuit 300; among them, the MOS transistor Q1 circuit and the MOS transistor Q2 circuit are used to conduct when a high level is output at the CC_RP / RD_EN signal terminal, so as to output a high level to the CC1 pin and the CC2 pin for device detection; the switch IC circuit is used to conduct the CC1 pin and the CC2 pin when a low level is output at the CC_RP / RD_EN signal terminal or when no power is supplied for device detection; USB device end 100: As the main part of the entire circuit, it provides an interface for connecting other components and the control logic required to implement the device functions; Type-C interface 200, which is used to connect external devices, supports data transmission and power supply, and at the same time provides a reversible plug-and-play function.

[0035] Further, one path of the CC_RP / RD_EN signal terminal of the USB device end 100 is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q1 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC1 pin of the Type-c interface 200;

[0036] The MOS transistor Q1 circuit is used to conduct when the CC_RP / RD_EN signal is at a high level, controlling the current flow to the CC1 pin for device detection. Through the MOS transistor Q1, the circuit can control the power path from VDD_3V3 to the CC1 pin, which allows power to be provided to the CC1 pin when needed or the power to be cut off when not needed, thus achieving more effective power management. Through the control of the MOS transistor Q1 at the CC_RP / RD_EN signal terminal, the MOS transistor Q1 can act as a protection component to prevent overvoltage or overcurrent from damaging the CC1 pin or the connected device. When an abnormal voltage or current is detected, the MOS transistor Q1 can quickly disconnect the connection to protect the circuit.

[0037] Further, one path of the CC_RP / RD_EN signal terminal of the USB device end 100 is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q2 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC2 pin of the Type-c interface. Among them, the CC2 pin of the Type-C interface 200 is used to communicate with the connected device to negotiate power supply and data transmission parameters; through the MOS transistor Q2, the circuit can control the power supply path from VDD_3V3 to the CC2 pin. This allows power to be supplied to the CC2 pin when needed or cut off when not needed, thus achieving more efficient power management. The MOS transistor Q2 can be used as a protection component to prevent overvoltage or overcurrent from damaging the CC2 pin or the connected device. When an abnormal voltage or current is detected, the MOS transistor Q2 can quickly disconnect the connection to protect the circuit.

[0038] Further, the switch IC circuit 300 includes a switch IC, and the model of the switch IC is RS553YUC9; through the MOS transistors Q1 and Q2, RS553YUC9 can control the power supply states of the CC1 and CC2 pins to achieve device detection and power negotiation; RS553YUC9 determines whether to conduct the CC1 and CC2 pins according to the state of the CC_RP / RD_EN signal terminal, thereby controlling the power supply and data transmission states of the device.

[0039] Further, the MOS transistor Q1 circuit includes a MOS transistor Q1, a diode D02, a diode D04, and a resistor R47; the gate of the MOS transistor Q1 is respectively connected to the MOS transistor Q2 circuit, the corresponding terminal of the switch IC, and the CC_RP / RD_EN signal terminal. The drain of the MOS transistor Q1 is respectively connected to the first end of the diode D02 and the first end of the diode D04. The second end of the diode D02 is connected to the VDD_3V3 power supply terminal of the USB device end through the resistor R47, and the second end of the diode D04 is correspondingly connected to the USB_ID terminal; the source of the MOS transistor Q1 is respectively electrically connected to the CC1 pin and the corresponding terminal of the switch IC; the diodes D02 and D04 and the resistor R47 provide an additional protection mechanism to prevent the circuit from being damaged by reverse current or overcurrent.

[0040] Further, the MOS transistor Q2 circuit includes a MOS transistor Q2, a diode D01, a diode D03, and a resistor R46; the gate of the MOS transistor Q2 is correspondingly connected to the gate of the MOS transistor Q1, the drain of the MOS transistor Q2 is respectively connected to the first end of the diode D03 and the first end of the diode D01, the second end of the diode D01 is respectively connected to the VDD_3V3 power supply terminal of the USB device terminal and the second end of the resistor R46 through the resistor R46, and the second end of the diode D03 is correspondingly connected to the second end of the diode D04 and the USB_ID terminal; the source of the MOS transistor Q2 is respectively electrically connected to the CC2 pin and the corresponding end of the switch IC; the diodes D01 and D03 and the resistor R46 provide an additional protection mechanism to prevent the circuit from being damaged by reverse current or overcurrent.

[0041] Further, the V-BUS power line terminal of the USB device terminal 100 is also connected to the V-BUS power line terminal of the Type-c interface 200; the TYPE-C port logic detection circuit further includes an overvoltage and overcurrent protection circuit 400, and the V-BUS power line terminal of the USB device terminal 100 is connected to the V-BUS power line terminal of the Type-c interface 200 through the overvoltage and overcurrent protection circuit 400; the overvoltage and overcurrent protection circuit 400 includes an overvoltage and overcurrent protection chip, a diode TVS1, capacitors C101, C102, C103, and C104; the OUT terminal of the overvoltage and overcurrent protection chip is respectively connected to the first end of the capacitor C104, the first end of the capacitor C103, and the V-BUS power line terminal of the USB device terminal, the VIN terminal of the overvoltage and overcurrent protection chip is respectively connected to the first end of the capacitor C102, the first end of the capacitor C101, the first end of the diode TVS1, and the V-BUS power line terminal of the Type-c interface, and the second ends of the diode TVS1, the capacitors C101, C102, C103, and C104 are all grounded; the V-BUS power line terminal is directly connected to the USB device terminal 100 and the Type-C interface 200 to ensure that the power can be effectively transmitted to the connected device; the overvoltage and overcurrent protection circuit 400 is used to protect the USB device from being damaged by excessive voltage or current, and the model of the overvoltage and overcurrent protection chip can be TPS2041, TPS2581, IR4618, TLE9012, etc.

[0042] Further, the USB_DN signal terminal of the USB device end 100 is connected to the DN1 and DN2 pins of the Type-c interface 200 via the resistor R17 respectively; the USB_DP signal terminal of the USB device end 100 is connected to the DP1 and DP2 pins of the Type-c interface 200 via the resistor R18 respectively; the USB_DN and USB_DP signal terminals are differential signal lines in the USB interface for transmitting high-speed data. Differential signal transmission can reduce electromagnetic interference (EMI) and improve signal integrity; USB_DN carries the negative part of the data signal, while USB_DP carries the positive part of the data signal; the resistors R17 and R18 are usually used to limit the current on the signal line, protect the circuit from damage caused by excessive current, can be used for signal impedance matching, ensure signal integrity and reduce reflections; the DN1 and DN2 pins, as well as the DP1 and DP2 pins of the Type-C interface are the physical connection points of the Type-C interface for receiving and sending differential signals; DN1 and DN2 receive the signals from USB_DN, while DP1 and DP2 receive the signals from USB_DP.

[0043] The technology of this application takes into account the DRP (Dual Role Port) function of the USB Type-C interface, allowing the device to dynamically switch between USB host and device without additional PD chips and complex circuit designs. This not only improves the compatibility and flexibility of USB devices, but also reduces costs and development difficulties.

[0044] The utility model simplifies the circuit design by using specific MOS transistors and switch ICs, without the need to additionally integrate complex PD chips, thereby reducing the design difficulty and cost. Due to eliminating the dependence on PD chips, the utility model reduces the workload of software development and hardware debugging, and reduces the overall development cost.

[0045] The working principle of the utility model:

[0046] When an external device is connected to the USB device end 100 through the Type-C interface 200, the CC1 and CC2 pins of the Type-C interface 200 communicate with the external device through the MOS transistor Q1 and MOS transistor Q2 circuits. The CC_RP / RD_EN signal terminal outputs a high level or a low level according to the logical control state of the USB device end 100 to indicate the current power supply and data transmission states.

[0047] The gates of MOS transistors Q1 and Q2 receive control signals from the CC_RP / RD_EN signal terminal. When the CC_RP / RD_EN signal is at a high level, MOS transistors Q1 and Q2 are turned on, allowing current to flow to the CC1 and CC2 pins, thereby detecting the device and identifying it as a slave device or a master device. The turned-on MOS transistors Q1 and Q2 enable the USB device terminal 100 to supply power to the connected device or receive power from the connected device. When the CC_RP / RD_EN signal is at a low level or not powered, the switch IC circuit 300 takes over the control to ensure that the CC1 and CC2 pins can still communicate, thereby detecting the device and identifying it as a slave device or a master device.

[0048] This application can detect and charge the device when the battery is completely depleted, especially solving the problem that the USB device cannot be charged when it is completely discharged to 0V, which solves the problem that the device cannot be charged under low battery conditions in the prior art. And through innovative circuit design, using specific MOS transistors and switch ICs, as well as optimized control logic, the device detection and charging functions under completely depleted battery conditions are achieved.

[0049] The above are only the preferred embodiments of the present utility model, and do not limit the patent scope of the present utility model. Any equivalent structural transformation made under the inventive concept of the present utility model by using the content of the specification and drawings of the present utility model, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present utility model.

Claims

1. A TYPE-C port logic detection circuit, characterized in that Including: USB device end, Type-c interface, switch IC circuit, MOS transistor Q1 circuit, MOS transistor Q2 circuit; The CC_RP / RD_EN signal terminals of the USB device end are respectively connected to the corresponding terminals of the switch IC circuit, MOS transistor Q1 circuit, and MOS transistor Q2 circuit; The corresponding terminal of the MOS transistor Q1 circuit is also respectively electrically connected to the CC1 pin of the Type-c interface and the corresponding terminal of the switch IC circuit; the corresponding terminal of the MOS transistor Q2 circuit is also respectively electrically connected to the CC2 pin of the Type-c interface and the corresponding terminal of the switch IC circuit; wherein, the MOS transistor Q1 circuit and the MOS transistor Q2 circuit are used to conduct when a high level is output at the CC_RP / RD_EN signal terminal, so as to output a high level to the CC1 pin and the CC2 pin; the switch IC circuit is used to conduct the CC1 pin and the CC2 pin when a low level is output at the CC_RP / RD_EN signal terminal or no power is supplied.

2. The TYPE-C port logic detection circuit according to claim 1, wherein The CC_RP / RD_EN signal terminal of the USB device end is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q1 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC1 pin of the Type-c interface.

3. The TYPE-C port logic detection circuit according to claim 1, characterized in that The CC_RP / RD_EN signal terminal of the USB device end is connected to the VDD_3V3 power supply terminal of the USB device end through the MOS transistor Q2 circuit, and the other path is respectively connected to the corresponding terminal of the switch IC circuit and the CC2 pin of the Type-c interface.

4. The TYPE-C port logic detection circuit according to claim 1, wherein The switch IC circuit includes a switch IC, and the model of the switch IC is RS553YUC9.

5. The TYPE-C port logic detection circuit according to claim 1, characterized in that The MOS transistor Q1 circuit includes MOS transistor Q1, diode D02, diode D04, resistor R47; the gate of the MOS transistor Q1 is respectively connected to the MOS transistor Q2 circuit, the corresponding terminal of the switch IC, and the CC_RP / RD_EN signal terminal, the drain of the MOS transistor Q1 is respectively connected to the first end of the diode D02 and the first end of the diode D04, the second end of the diode D02 is connected to the VDD_3V3 power supply terminal of the USB device end through the resistor R47, and the second end of the diode D04 is correspondingly connected to the USB_ID terminal; the source of the MOS transistor Q1 is respectively electrically connected to the CC1 pin and the corresponding terminal of the switch IC.

6. The TYPE-C port logic detection circuit according to claim 1, wherein The MOS transistor Q2 circuit includes MOS transistor Q2, diode D01, diode D03, resistor R46; the gate of the MOS transistor Q2 is correspondingly connected to the gate of the MOS transistor Q1, the drain of the MOS transistor Q2 is respectively connected to the first end of the diode D03 and the first end of the diode D01, the second end of the diode D01 is respectively connected to the VDD_3V3 power supply terminal of the USB device end and the second end of the resistor R46 through the resistor R46, and the second end of the diode D03 is correspondingly respectively connected to the second end of the diode D04 and the USB_ID terminal; the source of the MOS transistor Q2 is respectively electrically connected to the CC2 pin and the corresponding terminal of the switch IC.

7. The TYPE-C port logic detection circuit according to claim 1, characterized in that The V-BUS power line terminal of the USB device end is also connected to the V-BUS power line terminal of the Type-c interface.

8. The TYPE-C port logic detection circuit according to claim 1, characterized in that The TYPE-C port logic detection circuit further includes an overvoltage and overcurrent protection circuit. The V-BUS power line terminal of the USB device end is connected to the V-BUS power line terminal of the Type-c interface through the overvoltage and overcurrent protection circuit; The overvoltage and overcurrent protection circuit includes an overvoltage and overcurrent protection chip, a diode TVS1, a capacitor C101, a capacitor C102, a capacitor C103, and a capacitor C104. The OUT terminal of the overvoltage and overcurrent protection chip is respectively connected to the first terminal of the capacitor C104, the first terminal of the capacitor C103, and the V-BUS power line terminal of the USB device end. The VIN terminal of the overvoltage and overcurrent protection chip is respectively connected to the first terminal of the capacitor C102, the first terminal of the capacitor C101, the first terminal of the diode TVS1, and the V-BUS power line terminal of the Type-c interface. The second terminals of the diode TVS1, the capacitor C101, the capacitor C102, the capacitor C103, and the capacitor C104 are all grounded.

9. The TYPE-C port logic detection circuit according to claim 1, characterized in that, The USB_DN signal terminal of the USB device end is respectively connected to the DN1 and DN2 pins of the Type-c interface through a resistor R17.

10. The TYPE-C port logic detection circuit according to claim 1, characterized in that, The USB_DP signal terminal of the USB device end is respectively connected to the DP1 and DP2 pins of the Type-c interface through a resistor R18.

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