Small-size packaging structure with multiple vertically stacked chips
Through a multi-chip vertical stacking structure without bonding wires and TSVs, plastic-sealed vias and bump interconnection, the problems of large package size and poor signal transmission quality are solved, and smaller package size and better signal transmission are achieved, while reducing the risk of short circuit and improving thermal conduction performance.
Patent Information
- Application Number
- CN202422273274.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-18
AI Technical Summary
The existing multi-chip vertical stacking packaging technology has problems such as large packaging size, poor signal transmission quality and short circuit of injection molded punch lines, especially in high-density and high-frequency signal transmission.
A multi-chip vertical stacking structure without bonding wires and TSVs is adopted to achieve interconnection between wafers through plastic sealing through holes and bumps, and electrical signal transmission is carried out in combination with the rewiring layer, avoiding the use of bonding wires.
It achieves a smaller package size, improves signal transmission quality, reduces the risk of short circuit in injection molded punch lines, and improves thermal conduction performance.
Smart Images
Figure CN223079119U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to semiconductor packaging technology, electronic chip packaging technology, multi-chip die stacking packaging, wafer-level packaging, substrate packaging, etc., and specifically relates to a small-size packaging structure for multi-chip vertical stacking. Background Art
[0002] The development of electronic packaging technology is rapid. To adapt to the development trends of electronic miniaturization, integration, and systematization, packaging technology is gradually developing towards multi-chip (die) stacking packaging to integrate chips with different functions into one package. The multi-die stacking packaging MCM (Multi-chip module) is currently very mature and widely used in various product fields. The two most common interconnection forms of multi-die vertical stacking packaging are: 1) pure WB (wire bonding) vertical stacking; 2) FC+WB (flip chip + wire bonding) vertical stacking.
[0003] Such as Figure 1 shown, the multi-chip WB interconnection vertical stacking is still the most common packaging form of three-dimensional vertical stacking at present. It only uses bonding wires, with simple process and high adoption rate. However, its main disadvantages are: 1) The number of wire bonds 7 on the bottom die 1 is large. For two-layer wire bonding, the outer expansion size of the substrate 4 is large, resulting in too large packaging size and being not conducive to the development trend of miniaturization. 2) For radio frequency high-frequency and sensitive signals, the parasitic effects brought by wire bonding affect the signal transmission quality. 3) High-density wire bonding or long wire bonding is also prone to the risk of short circuit due to injection molding wire breakage.
[0004] In view of these disadvantages of pure WB interconnection, the multi-chip FC+WB interconnection vertical stacking packaging form has been gradually popularized and developed in recent years. The FC+WB interconnection vertical stacking, because it simultaneously mixes two interconnection processes, is also called hybrid packaging. Since the bottom die 1 uses bumps 5 instead of wire bonds, the substrate size and packaging size have decreased, and the signal transmission quality of the bottom die 1 has been improved. However, the hybrid packaging can never eliminate wire bonding. The middle die 2 and the upper die 3 still need to be wire-bonded 7 to the substrate 4 to form an interconnection with the bottom die 1, and the wire bonding is too long. A certain area needs to be expanded at the edge of the substrate for wire bonding, and the packaging size still cannot be reduced to the optimal value. Summary of the Invention
[0005] In order to further reduce the size of the packaging structure, this technical solution proposes a multi-chip vertical stacking ultra-small size packaging structure without bonding wires and without TSV (through-silicon via). According to the requirements of the number of solder ball pins of the packaging, wafer-level packaging or substrate-like packaging can be further realized on the basis of the basic packaging structure.
[0006] The specific description of this technical solution is as follows.
[0007] A small-size packaging structure with multi-chip vertical stacking, comprising a bottom plastic encapsulation module and one or more upper plastic encapsulation modules;
[0008] a. The structure of the bottom plastic encapsulation module is as follows: it includes a bottom wafer, an intermediate wafer, and a bottom redistribution layer;
[0009] On each contact on the front side of the bottom wafer, there is an upward plastic encapsulation via; the intermediate wafer is mounted face-up on the bottom wafer, and on each contact on the front side of the intermediate wafer, there is a bump, with the bump facing upward; the plastic encapsulation vias are distributed around the intermediate wafer; above the intermediate wafer is the bottom redistribution layer;
[0010] The bottom wafer and the intermediate wafer are encapsulated with plastic encapsulant, which covers the surface of the bottom wafer, wraps the plastic encapsulation vias and the intermediate wafer, and fills the gap between the intermediate wafer and the bottom redistribution layer; the top end of the plastic encapsulation via and the bump of the intermediate wafer are respectively connected to the pads on the bottom surface of the bottom redistribution layer;
[0011] b. The structure of the upper plastic encapsulation module is as follows: it includes an upper wafer and an upper redistribution layer;
[0012] The front side of the upper wafer faces downward, and on each contact of the upper wafer, there is a bump, with the bump facing downward; above the upper wafer is the upper redistribution layer; on the pads on the bottom surface of the upper redistribution layer, there are downward plastic encapsulation vias, and the plastic encapsulation vias are distributed around the upper wafer;
[0013] The plastic encapsulant wraps the upper wafer and the plastic encapsulation vias, and fills the gap between the upper wafer and the upper redistribution layer;
[0014] c. The connection structure between the upper plastic encapsulation module and the bottom plastic encapsulation module is as follows: the bottom end of the plastic encapsulation via in the upper plastic encapsulation module and the bottom end of the bump of the upper wafer are respectively connected to the corresponding pads on the top surface of the bottom redistribution layer; the plastic encapsulant in the upper plastic encapsulation module is bonded to the top surface of the bottom redistribution layer;
[0015] d. If there are multiple upper plastic encapsulation modules, the connection structure between the upper plastic encapsulation module on the top and the upper plastic encapsulation module on the bottom is as follows:
[0016] The bottom end of the plastic encapsulation via in the upper plastic encapsulation module on the top and the bottom end of the bump of the upper wafer are respectively connected to the corresponding pads on the top surface of the upper redistribution layer in the upper plastic encapsulation module on the bottom; the plastic encapsulant in the upper plastic encapsulation module on the top is bonded to the top surface of the upper redistribution layer in the upper plastic encapsulation module on the bottom.
[0017] Further, the first encapsulation structure: In the upper encapsulation module of the top layer, solder balls are correspondingly connected to the pads on the top surface of the upper redistribution layer, thus forming a wafer-level encapsulation structure.
[0018] Further, the second encapsulation structure: In the upper encapsulation module of the top layer, upward bumps are correspondingly connected to the pads on the top surface of the upper redistribution layer. The top of the bump is connected to the pad on one side of the substrate. Underfill is between the top surface of the upper redistribution layer and the substrate. Solder balls are correspondingly connected to the pads on the other side of the substrate, thus forming a substrate-type encapsulation structure.
[0019] In the bottom encapsulation module: The bottom chip and the bottom redistribution layer overlap in the projection on the bottom surface and are outside the projection range of the middle chip on the bottom surface; the edge of the cured encapsulant coincides with the edge of the bottom chip.
[0020] In the upper encapsulation module: The projection of the upper chip on the bottom surface is within the projection range of the upper redistribution layer on the bottom surface.
[0021] The projections of the bottom chip, the bottom redistribution layer, and each upper redistribution layer on the bottom surface overlap.
[0022] The projections of the bottom chip, the bottom redistribution layer, and each upper redistribution layer on the bottom surface are within the projection range of the substrate on the bottom surface.
[0023] The effect of this technical solution is that three (or more) chips can be stacked three-dimensionally in the vertical direction without bonding wires and without TSV (through-silicon via). Compared with a single WB three-dimensional stack and an FC+WB hybrid three-dimensional stack, the advantages of this solution are as follows:
[0024] 1) There is no bonding wire fan-out, the substrate size is smaller, and the package size is smaller, which is conducive to the miniaturization and high-density development trend of electronic products.
[0025] 2) There are no bonding wires. Compared with large-scale high-density wire bonding products, the risk of short circuit due to injection punching wires is avoided.
[0026] 3) There are no bonding wires. All use bumps and TMV with a wider line width and shorter line length for electrical signal transmission, reducing the influence of bonding wire parasitics on signal transmission quality.
[0027] 4) There are no bonding wires. Bumps and TMV are more conducive to heat conduction. The back surface of the bottom chip can directly contact the external module heat sink to conduct heat, and the heat dissipation ability is better. Description of the Drawings
[0028] Figure 1It is a schematic diagram of the size comparison between the multi-chip WB interconnection vertical stacked package structure and the multi-chip FC+WB interconnection vertical stacked package structure; among them, the multi-chip WB interconnection vertical stacked package structure A, the multi-chip FC+WB interconnection vertical stacked package structure B, the width L1 of the multi-chip WB interconnection vertical stacked package structure, and the width L2 of the multi-chip FC+WB interconnection vertical stacked package structure;
[0029] Figure 2 It is a schematic diagram of the basic package structure adopting this solution;
[0030] Figure 3 It is a schematic diagram of the wafer-level package structure adopting this solution;
[0031] Figure 4 It is a schematic diagram of the substrate-type package structure adopting this solution;
[0032] In the figure, the bottom die 1, the middle die 2, the upper die 3, the substrate 4, the bump 5, the encapsulant 6, the wire bonding 7, the solder ball 8, the through mold via (TMV) 9, the bottom encapsulation module 10, the upper encapsulation module 11, the bottom redistribution layer (RDL) 12, and the upper redistribution layer (RDL) 13. Detailed implementation manners
[0033] The following further illustrates this technical solution in combination with the attached drawings and specific implementation manners.
[0034] Refer to Figure 2 , a small-size package structure for multi-chip vertical stacking, including a bottom encapsulation module 10 and one or more upper encapsulation modules 11;
[0035] The structure of the bottom encapsulation module is: including the bottom die 1, the middle die 2, and the bottom redistribution layer 12;
[0036] Upward through mold vias 9 are connected to each contact on the front surface of the bottom die 1; the middle die 2 is mounted face-up on the front surface of the bottom die, and bumps are connected to each contact on the front surface of the middle die, with the bumps facing upward; the through mold vias are distributed around the middle die; above the middle die is the bottom redistribution layer 12;
[0037] The bottom die 1 and the middle die 2 are encapsulated by the encapsulant 6, and the encapsulant covers the surface of the bottom die, wraps the through mold vias and the middle die, and fills the gap between the middle die and the bottom redistribution layer; the top of the through mold via and the bump of the middle die are respectively connected to the pads on the bottom surface of the bottom redistribution layer;
[0038] The structure of the upper encapsulation module is: including the upper die 3 and the upper redistribution layer 13;
[0039] The front side of the upper wafer 3 faces downward, and bumps 5 are connected to each contact of the upper wafer, with the bumps facing downward; above the upper wafer is the upper redistribution layer 13; downward plastic through holes 9 are connected to the pads on the bottom surface of the upper redistribution layer, and the plastic through holes are distributed around the upper wafer;
[0040] The molding compound 6 wraps the upper wafer 3 and the plastic through holes, and fills the gap between the upper wafer and the upper redistribution layer;
[0041] The connection structure between the upper molding module and the lower molding module is as follows: the bottom ends of the plastic through holes in the upper molding module and the bottom ends of the bumps of the upper wafer are respectively connected to the corresponding pads on the top surface of the lower redistribution layer; the molding compound in the upper molding module is bonded to the top surface of the lower redistribution layer.
[0042] In this example, there is 1 upper molding module.
[0043] If there are multiple upper molding modules, the connection structure between the upper molding module on the top and the upper molding module on the bottom is as follows:
[0044] The bottom ends of the plastic through holes in the upper molding module on the top and the bottom ends of the bumps of the upper wafer are respectively connected to the corresponding pads on the top surface of the upper redistribution layer in the upper molding module on the bottom; the molding compound in the upper molding module on the top is bonded to the top surface of the upper redistribution layer in the upper molding module on the bottom.
[0045] Reference Figure 3 For the packaging structure: in the uppermost upper molding module, solder balls 8 are correspondingly connected to the pads on the top surface of the upper redistribution layer 13, thus forming a wafer-level packaging structure.
[0046] Reference Figure 4 For the packaging structure: in the uppermost upper molding module, upward bumps 5 are correspondingly connected to the pads on the top surface of the upper redistribution layer 13, the top ends of the bumps are connected to the pads on one side of the substrate 4, underfill is between the top surface of the upper redistribution layer and the substrate, and solder balls 8 are correspondingly connected to the pads on the other side of the substrate, thus forming a substrate-type packaging structure.
[0047] In the lower molding module: the projections of the lower wafer and the lower redistribution layer on the bottom surface coincide, and are outside the projection range of the middle wafer on the bottom surface; the edge of the cured molding compound coincides with the edge of the lower wafer.
[0048] In the upper molding module: the projection of the upper wafer on the bottom surface is within the projection range of the upper redistribution layer on the bottom surface.
[0049] The projections of the lower wafer, the lower redistribution layer, and each upper redistribution layer on the bottom surface coincide.
[0050] The projections of the bottom wafer, the bottom redistribution layer and each upper redistribution layer on the bottom surface are within the projection range of the substrate on the bottom surface.
[0051] 1. Manufacturing process of wafer-level packaging structure
[0052] 1) Using electroplating process, the bottom wafer (die) 1 is provided with a long plastic sealing through-molding via (TMV).
[0053] 2) Grind and cut the middle layer chip (die) 2 wafer, and mount it (upright mounting) on the bottom chip (die) 1, with the bump (bump) 5 on the front side of the middle layer chip (die) 2 facing upward.
[0054] 3) The bottom chip (die) 1 is injection molded as a whole to cover the TMV and the middle chip (die) 2, and then the plastic molding compound is ground to form the bottom plastic molding module 10, exposing the TMV and the bump.
[0055] 4) The bottom redistribution layer (RDL) 12 process is performed on the TMV and bump surfaces of step 3), and the bottom redistribution layer (RDL) interconnects the bottom wafer and the middle wafer. A pad is reserved on the front side of the bottom redistribution layer for connecting the upper wafer (die) 3.
[0056] 5) The upper chip (die) 3 wafer is ground and cut, and then the bump 5 of the upper chip (die) 3 is facing downward, and the upper chip (die) 3 is flipped on the bottom redistribution layer (RDL) 12, so as to realize the interconnection between the upper chip and the bottom chip.
[0057] 6) Continue to electroplating the reserved bumps / pads of the bottom chip (die) 1 on the bottom redistribution layer to form another set of plastic-encapsulated through-holes TMV.
[0058] 7) The bottom wafer is injection molded as a whole to cover the plastic sealing through hole TMV and the upper wafer (die) 3 in step 6), and then the plastic sealing material is ground to form an upper plastic sealing module to expose the plastic sealing through hole TMV.
[0059] 8) The exposed plastic package through-hole contacts in step 7) are subjected to an upper redistribution layer (RDL) 13 process to redistribute the IO pins that need to be externally led out to grow pads for placing the final solder balls 8.
[0060] 9) Place solder balls on the surface pads of the upper redistribution layer, then grind the back of the bottom wafer and perform final wafer cutting to obtain the final single wafer-level packaged chip.
[0061] For wafer-level packaging, there is no substrate, and the final solder ball pins are placed on the RDL. When the chip is in use, the solder ball is connected to the PCB.
[0062] II. Substrate-based packaging manufacturing process
[0063] Among them, process steps 1) to 7) are exactly the same as those of the wafer-level packaging manufacturing process, and the following will continue to be described from step 8).
[0064] 8) Perform the process of the upper redistribution layer (RDL) 13 on the molded through-hole contacts exposed in step 7), and redistribute and grow pads for the IO pins that need to be externally led out, for placing the final bump 5.
[0065] 9) Grow bumps 5 at the pads on the surface of the upper redistribution layer, then grind the back surface of the bottom wafer, and perform the final wafer dicing to obtain the final single chip module.
[0066] 10) Interconnect the chip module with the substrate 4 using the flip chip process, then perform underfill, substrate ball planting, and substrate dicing to obtain the final single substrate-based packaged chip.
[0067] For substrate-level packaging, there is a substrate, and the final solder ball pins are placed on the outer side of the substrate, that is, on the top surface of the substrate as shown in Figure 4 the substrate.
[0068] On the inner side of the substrate, that is, above the upper redistribution layer (RDL) 13, solder balls cannot be placed, only solder bumps can be placed, that is, the bump 5 between the substrate and the upper redistribution layer (RDL) 13 as shown in Figure 4 the figure. Because the solder bump is an interconnection bump at the chip packaging level and is very small; the solder ball is a board-level interconnection solder ball for SMT soldering of the chip on the PCB and is very large. Bumps are used inside the chip, and solder balls are used for external connection to the next-level PCB.
Claims
1. A small-size packaging structure with multi-chip vertical stacking, characterized in that It includes a bottom encapsulation module and one or more upper encapsulation modules; The structure of the bottom encapsulation module is as follows: it includes a bottom wafer, an intermediate wafer, and a bottom redistribution layer; On each contact on the front side of the bottom wafer, there is an upward encapsulation through-hole connected; the intermediate wafer is mounted face-up on the bottom wafer, and on each contact on the front side of the intermediate wafer, there is a bump connected, with the bump facing upward; the encapsulation through-holes are distributed around the intermediate wafer; above the intermediate wafer is the bottom redistribution layer; The bottom wafer and the intermediate wafer are encapsulated with encapsulation material, the encapsulation material covers the surface of the bottom wafer, wraps the encapsulation through-holes and the intermediate wafer, and fills the gap between the intermediate wafer and the bottom redistribution layer; the top end of the encapsulation through-hole and the bump of the intermediate wafer are respectively connected to the pads on the bottom surface of the bottom redistribution layer; The structure of the upper encapsulation module is as follows: it includes an upper wafer and an upper redistribution layer; The front side of the upper wafer faces downward, and on each contact of the upper wafer, there is a bump connected, with the bump facing downward; above the upper wafer is the upper redistribution layer; on the pads on the bottom surface of the upper redistribution layer, there are downward encapsulation through-holes connected, and the encapsulation through-holes are distributed around the upper wafer; The encapsulation material wraps the upper wafer and the encapsulation through-holes, and fills the gap between the upper wafer and the upper redistribution layer; The connection structure between the upper encapsulation module and the bottom encapsulation module is as follows: the bottom end of the encapsulation through-hole in the upper encapsulation module and the bottom end of the bump of the upper wafer are respectively connected to the corresponding pads on the top surface of the bottom redistribution layer; the encapsulation material in the upper encapsulation module is bonded to the top surface of the bottom redistribution layer; If there are multiple upper encapsulation modules, the connection structure between the upper encapsulation module on the top and the upper encapsulation module on the bottom is as follows: the bottom end of the encapsulation through-hole in the upper encapsulation module on the top and the bottom end of the bump of the upper wafer are respectively connected to the corresponding pads on the top surface of the upper redistribution layer in the upper encapsulation module on the bottom; the encapsulation material in the upper encapsulation module on the top is bonded to the top surface of the upper redistribution layer in the upper encapsulation module on the bottom.
2. The small-size packaging structure with multi-chip vertical stacking according to claim 1, characterized in that In the topmost upper encapsulation module, if there are solder balls correspondingly connected to the pads on the top surface of the upper redistribution layer, a wafer-level package structure is formed.
3. The small-sized packaging structure with multi-chip vertical stacking according to claim 1, characterized in that In the topmost upper encapsulation module, if there are upward bumps correspondingly connected to the pads on the top surface of the upper redistribution layer, the top end of the bump is connected to the pad on one side of the substrate, and there is underfill between the top surface of the upper redistribution layer and the substrate, and if there are solder balls correspondingly connected to the pads on the other side of the substrate, a substrate-type package structure is formed.
4. The small-sized package structure with multi-chip vertical stacking according to claim 1, 2 or 3, characterized in that In the bottom encapsulation module: the projections of the bottom wafer and the bottom redistribution layer on the bottom surface coincide, and are outside the projection range of the intermediate wafer on the bottom surface; the edge of the cured encapsulation material coincides with the edge of the bottom wafer.
5. The small-size packaging structure with multi-chip vertical stacking according to claim 1, 2 or 3, characterized in that In the upper encapsulation module: the projection of the upper wafer on the bottom surface is within the projection range of the upper redistribution layer on the bottom surface.
6. The small-size package structure with multi-chip vertical stacking according to claim 1, 2 or 3, characterized in that The projections of the bottom wafer, the bottom redistribution layer, and each upper redistribution layer on the bottom surface coincide.
7. The small-size package structure with multi-chip vertical stacking according to claim 3, characterized in that The projections of the bottom wafer, the bottom redistribution layer, and each upper redistribution layer on the bottom surface are within the projection range of the substrate on the bottom surface.