Pulse signal generation circuit for delay measurement of logic unit of integrated circuit
By designing the pulse signal generation circuit, the precise measurement of logic unit delay is achieved, and the problem of insufficient accuracy of logic unit delay measurement in large-scale integrated circuits is solved. It is suitable for the measurement needs of high-frequency, low-power, and high-integrated circuits.
Patent Information
- Application Number
- CN202422159485.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-02
AI Technical Summary
In complex integrated circuit environments, especially in large-scale high-density circuit designs, it is difficult for the prior art to accurately measure the delay of logic units, and small delay deviations have a significant impact on overall timing and performance.
A circuit structure including a pulse signal generation circuit, a test oscillation ring and a pulse signal processing circuit is designed. Through the generation of pulse signals, latch and state signal generation, the delay of the logic unit is accurately measured, and the pulse signal width is used to reflect the delay change.
It improves the accuracy of delay measurement of logic unit and the reliability of test results, and is suitable for the measurement needs of high-frequency, low-power, and high-integration circuits. The circuit structure is simple and the area occupied is small.
Smart Images
Figure CN223080010U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of integrated circuits, and particularly relates to a pulse signal generation circuit for measuring the delay of an integrated circuit logic unit. Background Art
[0002] With the continuous progress of integrated circuit technology, the requirements for the speed and performance of circuit operation are also continuously increasing. Especially in high-frequency and high-speed applications, the accurate measurement of signal delay has become particularly crucial. Delay measurement has a wide range of applications in multiple fields such as timing analysis, delay chain calibration, and pulse width modulation, and directly affects the overall performance of the circuit.
[0003] The delay of the logic unit is one of the key factors determining the circuit timing and performance. Especially in high-frequency, low-power, and high-integration circuit designs, accurately measuring the delay of the logic unit is crucial for ensuring the stability and reliability of the circuit. Because, as the process size gradually shrinks, traditional delay measurement methods gradually show the problem of insufficient accuracy when facing complex circuit structures. In large-scale integrated circuits, logic units exist in large quantities, and tiny delay deviations may have a significant impact on the overall timing and performance.
[0004] Therefore, how to accurately measure the delay of a single logic unit (such as a logic gate) in a complex integrated circuit environment, especially in large-scale high-density circuit designs, has become an important technical problem to be solved urgently. Summary of the Utility Model
[0005] The purpose of the utility model is to provide a pulse signal generation circuit for measuring the delay of an integrated circuit logic unit, including a pulse signal generation circuit, a test oscillator ring, and a pulse signal processing circuit, which can realize the generation, latching of the pulse signal, and the generation of the status signal of the pulse signal. By testing the width of the generated pulse signal, the delay change of the logic unit can be accurately reflected, and thus the accurate measurement of the delay of a single logic unit is realized.
[0006] To achieve the above purpose, the utility model provides a pulse signal generation circuit for measuring the delay of an integrated circuit logic unit, including: a pulse signal generation circuit, a test oscillator ring, and a pulse signal processing circuit;
[0007] The pulse signal generation circuit includes: 2N cascaded logic units and an exclusive OR gate; the output end of the last logic unit among the 2N cascaded logic units is connected to the first input end of the exclusive OR gate, the first input end of the first logic unit among the 2N cascaded logic units and the second input end of the exclusive OR gate are both connected to the enable input signal input from the input end of the pulse signal generation circuit; the output end of the exclusive OR gate is the output end of the pulse signal generation circuit, outputting a pulse signal; N≥50;
[0008] The test oscillation loop includes 2M + 1 cascaded NAND gates. Among them, the first input terminal of the first-stage NAND gate is connected to the output terminal of the pulse signal generating circuit, the first input terminal of each of the remaining stages of NAND gates is connected to a constantly valid input signal, the output terminal of each stage of NAND gate is connected to the second input terminal of the next-stage NAND gate, and the output terminal of the last-stage NAND gate is connected to the second input terminal of the first-stage NAND gate; the output terminals of each stage of NAND gates sequentially output output signals with a fixed phase difference; M ≥ 1;
[0009] The pulse signal processing circuit is respectively connected to the output terminal of the pulse signal generating circuit and the output terminals of each stage of NAND gates of the test oscillation loop, and outputs the state signal of the pulse signal.
[0010] Preferably, the pulse signal processing circuit includes: two multi-bit latches, an exclusive-NOR gate, and a multi-bit register;
[0011] The first multi-bit latch inputs a first timing input signal composed of the 2M + 1 output signals. The enable terminal of the first multi-bit latch is connected to the output terminal of the pulse signal generating circuit to input the pulse signal, and the first output terminal of the first multi-bit latch outputs a first pulse state latch signal;
[0012] The second multi-bit latch inputs a second timing input signal composed of the 2M + 1 output signals. There is a phase difference between the second timing input signal and the first timing input signal; the enable terminal of the second multi-bit latch is connected to the output terminal of the pulse signal generating circuit to input the pulse signal, and the first output terminal of the second multi-bit latch outputs a second pulse state latch signal;
[0013] Two input terminals of the exclusive-NOR gate are respectively connected to the first output terminal of the first multi-bit latch and the first output terminal of the second multi-bit latch;
[0014] The input terminal of the multi-bit register is connected to the output terminal of the exclusive-NOR gate. The clock signal terminal of the multi-bit register is connected to the integrated circuit system clock, and the output terminal of the multi-bit register outputs the state signal of the pulse signal.
[0015] More preferably, the second output terminal of the first multi-bit latch outputs a reset signal;
[0016] The second output terminal of the second multi-bit latch is left empty.
[0017] Preferably, the logic unit includes: basic logic gates.
[0018] Preferably, the logic unit specifically includes: one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an exclusive-OR gate, or an exclusive-NOR gate.
[0019] Preferably, the logic unit in the pulse signal generation circuit and the integrated circuit logic unit are fabricated through the same technological process.
[0020] Preferably, the pulse signal generation circuit further includes: a NAND gate delay measurement circuit;
[0021] The NAND gate delay measurement circuit includes: a ring oscillator and a frequency divider;
[0022] The ring oscillator includes: 2X + 1 cascaded NAND gates; wherein, the output terminal of each stage of NAND gate is connected to the first input terminal of the next stage of NAND gate, the second input terminal of each stage of NAND gate is connected to an enable input signal; the output terminal of the last stage of NAND gate is connected to the input terminal of the first stage of NAND gate;
[0023] The input terminal of the frequency divider is connected to the output terminal of the last stage of NAND gate to receive the oscillation signal output by the ring oscillator, and the output terminal of the frequency divider outputs a frequency-divided signal of the oscillation signal, which is a test signal for measuring the NAND gate delay, where X ≥ 50.
[0024] The pulse signal generation circuit for measuring the delay of an integrated circuit logic unit provided by an embodiment of the present invention uses a pulse signal generation circuit, a test oscillation loop, and a pulse signal processing circuit to realize the generation, latching of a pulse signal, and the generation of a status signal of the pulse signal. By testing the width of the generated pulse signal, the delay change of the logic unit is accurately captured, thereby improving the measurement accuracy of the logic unit delay and the reliability of the test result. The circuit structure is simple and easy to implement, occupies a small area in the integrated circuit, is applicable to scenarios such as integrated circuit design verification and fault diagnosis, and can effectively meet the measurement requirements of high-frequency, low-power, and high-integration integrated circuits. Description of the Drawings
[0025] Figure 1 is a logic schematic diagram of the pulse signal generation circuit for measuring the delay of an integrated circuit logic unit provided by an embodiment of the present invention;
[0026] Figure 2 is a circuit diagram of a specific implementation of the pulse signal generation circuit for measuring the delay of an integrated circuit logic unit provided by an embodiment of the present invention;
[0027] Figure 3 is Figure 2 a waveform schematic diagram corresponding to the provided circuit;
[0028] Figure 4 is Figure 2 a pulse width calculation and analysis schematic diagram of the provided circuit;
[0029] Figure 5 A delay measurement circuit for a NAND gate is provided;
[0030] Figure 6 For Figure 5 A waveform schematic diagram of the provided delay measurement circuit. Specific embodiments
[0031] The technical solutions of the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.
[0032] The pulse signal generation circuit for measuring the delay of an integrated circuit logic unit provided by the embodiment of the present utility model Figure 1 is a logic schematic diagram of the pulse signal generation circuit for measuring the delay of an integrated circuit logic unit provided by the embodiment of the present utility model.
[0033] As Figure 1 shown, the pulse signal generation circuit proposed in this embodiment includes: a pulse signal generation circuit 10, a test oscillator ring 20, and a pulse signal processing circuit 30;
[0034] The pulse signal generation circuit 10 includes: 2N cascaded logic units and an exclusive OR gate; the output end of the last logic unit among the 2N cascaded logic units is connected to the first input end of the exclusive OR gate, the first input end of the first logic unit among the 2N cascaded logic units and the second input end of the exclusive OR gate are both connected to the enable input signal inputted at the input end of the pulse signal generation circuit; the output end of the exclusive OR gate is the output end of the pulse signal generation circuit, and a pulse signal is output.
[0035] In this application, the purpose of cascading the logic units in the circuit design is to accumulate the signal delays of the logic units through cascading, so as to achieve the purpose of amplifying the delay of the logic units. Considering that the signal delay of each logic unit is very small, it is preferably set that the cascading is not less than 100 levels, and in order to ensure that the phase of the output signal at the cascaded output end is the same as that at the input end, so as to generate a signal after the enable input signal passes through the cascaded logic unit delay at the input of the exclusive OR gate, so it is set to an even number of cascades, so M≥50 is set.
[0036] The test oscillator ring 20 includes 2M + 1 cascaded NAND gates. Among them, the first input end of the first NAND gate is connected to the output end of the pulse signal generation circuit, the first input end of each of the remaining NAND gates is connected to a constantly valid input signal, the output end of each NAND gate is connected to the second input end of the next NAND gate, and the output end of the last NAND gate is connected to the second input end of the first NAND gate; the output ends of each NAND gate sequentially output output signals with a fixed phase difference; M≥1;
[0037] The pulse signal processing circuit 30 is respectively connected to the output terminal of the pulse signal generating circuit 10 and the output terminals of the NAND gates at all levels of the test oscillator loop 20, and outputs the status signal of the pulse signal.
[0038] In the field of digital circuit technology, a logic unit is a circuit component that performs basic logic operations in a digital circuit. According to classification, it can include: basic logic gates, combinational logic units, sequential logic units, and complex logic units, etc. All kinds of devices in combinational logic units, sequential logic units, and complex logic units are composed of basic logic gates. Therefore, the accurate measurement of the delay of basic logic gates is very important.
[0039] In this embodiment, the logic unit specifically includes basic logic gates. Further, it specifically includes: one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, or an XNOR gate.
[0040] The pulse signal generating circuit for measuring the delay of an integrated circuit logic unit in this solution is fabricated on the integrated circuit. In the design and fabrication of the integrated circuit, there will be a separate area on the layout design for placing the test circuit, that is, a corresponding test circuit is formed on the fabricated chip. The logic unit in the pulse signal generating circuit proposed in this solution and the logic unit in the integrated circuit for measuring the logic unit delay by applying this pulse signal generating circuit are fabricated through the same process. Therefore, the test signal generated by the pulse signal generating circuit can truly reflect the delay of the integrated circuit logic unit.
[0041] To better understand the technical solution of the present invention, a specific example will be described below.
[0042] Figure 2 It is a circuit diagram of a specific implementation of the pulse signal generating circuit for measuring the delay of an integrated circuit logic unit provided in the embodiment of the present invention.
[0043] In this embodiment, the logic unit is a NOT gate, and the cascaded stage number of the logic unit is 100. Figure 2 The ×100 between the two NOT gates in the figure indicates that there are 100 cascaded NOT gates including the two drawn NOT gates. In this way, the delay of the 100 cascaded NOT gates in the ring oscillator each time will be accumulated to cell_delay×100, where cell_delay refers to the delay of a logic unit (a NOT gate in this example).
[0044] The first NOT gate receives the enable input signal en, and after a delay of 100 NOT gates, it is transmitted to the first input terminal of the XOR gate. The second input terminal of the XOR gate receives the enable input signal en. These two signals are XOR - operated by the XOR gate to obtain the pulse signal pulse_out. When there is a time difference between the delayed signal and the original signal, the pulse width of the pulse signal output by the XOR gate reflects this time difference. Because for the input signals of the XOR gate, it is equivalent to one input signal being delayed by cell_delay×100 based on the other input signal. Therefore, the width of the obtained pulse signal pulse_out is the cell_delay of 100 NOT gates.
[0045] The test oscillator ring in this example includes 3 cascaded NAND gates. One input terminal of the first - stage NAND gate is connected to the pulse signal pulse_out, and the other input terminal is connected to the output signal of the last - stage NAND gate as feedback. The input signal 1b of the first input terminals of the second - stage and third - stage NAND gates is a high - level always - active signal. The output terminal of each stage of the NAND gate is connected to the second input terminal of the next - stage NAND gate. Thus, it is realized that the output signal is only related to the second - input signal and the second - input signal is inverted. There is a delay t0 between the output signal of each stage of the NAND gate and the output signal of the previous - stage NAND gate. Thus, output signals D[0], D[1], D[2] with phase differences are formed. In Figure 3 the waveform diagram, the position marked by the red arrow represents the cell delay (i.e., t0) of a NAND gate.
[0046] The pulse - signal processing circuit includes: two multi - bit latches, an XNOR gate, and a multi - bit register.
[0047] The first multi - bit latch (the lower latch in the figure) has its input terminal input the first timing input signal D[0,1,2] composed of the output signals of each stage. The enable terminal of the first multi - bit latch is connected to the output terminal of the pulse - signal generation circuit, inputting the pulse signal pulse_out. The first output terminal of the first multi - bit latch outputs the first pulse - state latch signal Q_Latch[0,1,2].
[0048] The second multi - bit latch (the upper latch in the figure) has its input terminal input the second timing input signal D[1,2,0] composed of the output signals of each stage. There is a phase difference between the second timing input signal and the first timing input signal. The enable terminal of the second multi - bit latch is connected to the output terminal of the pulse - signal generation circuit, inputting the pulse signal pulse_out. The first output terminal of the second multi - bit latch outputs the second pulse - state latch signal Q_Latch[1,2,0].
[0049] The above - mentioned multi - bit latches can also be implemented by a latch array.
[0050] The two input terminals of the exclusive-NOR gate are respectively connected to the first output terminal of the first multi-bit latch and the first output terminal of the second multi-bit latch; that is, the two inputs respectively receive the first pulse state latch signal Q_Latch[0,1,2] and the second pulse state latch signal Q_Latch[1,2,0].
[0051] The input terminal of the multi-bit register is connected to the output terminal of the exclusive-NOR gate, the clock signal terminal of the multi-bit register is connected to the integrated circuit system clock CLK, and the output terminal of the multi-bit register outputs the state signal Q[0,1,2] of the pulse signal.
[0052] In addition, the second output terminal of the first multi-bit latch outputs a reset signal RST and serves as the input signal of the reset control terminal of the multi-bit register, and the second output terminal of the second multi-bit latch is left empty.
[0053] Figure 2 The waveform diagram corresponding to the provided circuit is as Figure 3 shown.
[0054] It can be seen that after the enable input signal en becomes a high-level signal, the output signal B of the delay chain still remains low at this time. According to the logical operation rule of the exclusive-OR gate, if the two input signals are different, the output is 1. Therefore, the pulse signal pulse_out is at a high level.
[0055] The high-level pulse_out is input to the test oscillator loop, and each stage of the output is respectively as Figure 3 shown by D[0], D[1], D[2] in, and there is a time difference of one NAND gate delay between each other.
[0056] After the time delay of 100 logic unit NOT gates, the output signal B of the delay chain jumps to a high level. According to the logical operation rule of the exclusive-OR gate, if the two input signals are the same, the output is 0. Therefore, the pulse signal pulse_out jumps to a low level, that is, the control signals of the signal enable terminals of the two multi-bit latches change to a low level. The two multi-bit latches latch the previously last sent signals D[0,1,2] and signal D[1,2,0], and output the state signal Q[0,1,2] of the pulse signal and the second pulse state latch signal Q_Latch[1,2,0]. When the system clock signal CLK changes from low level to high level next time, the state signal Q[0,1,2] of the pulse signal is output through the output terminal of the multi-bit register.
[0057] Q[0]=0 indicates that between D[0] and D[1], pulse_out always maintains a high-level enabled state, and the signal is normally inverted;
[0058] Q[1]=1 indicates that when it is between D[1] and D[2], the level of pulse_out jumps, and the signal fails to be inverted successfully.
[0059] Q[2]=0 indicates that between D[2] and D[0], pulse_out always maintains a high-level enabled state.
[0060] Therefore, the pulse width of pulse_out = (3 + 1)×t0 + (5 - 1)×(6×t0) + 1×t0, as Figure 4 shown. Combining Figure 4 it can be understood that in the above calculation formula, 3 is the number of NAND gates in the test oscillator ring; 1 in (3 + 1) is the fixed delay value when the pulse_out signal enters the test oscillator ring; 5 is the number of rising edges of D[0], -1 is because there are only four complete cycles on the waveform; t0 is the cell delay value of one NAND gate, 6 is the number of t0 between two adjacent rising edges of D[0], and 6×t0 is the period T of D[0]. 1 in 1×t0 is the number of bits with the XNOR result being high level, that is, within a half cycle, the level of pulse_out just jumps at this stage.
[0061] In the actual circuit, it is preferably to use an 11-stage NAND gate as the test oscillator ring, and more stages can further reduce the error.
[0062] The delay of the NAND gate can be directly substituted with the delay data of the NAND gate obtained by simulation processing in the integrated circuit design stage. Because even if there is a certain error in the delay data of the NAND gate, it is very small compared to the delay of 100 cascaded logic units and can be ignored for the calculation result.
[0063] By calculating the pulse width of pulse_out in the above manner and directly dividing it by 100, the delay of one logic unit can be obtained.
[0064] Of course, in order to obtain a more accurate result, a separate NAND gate delay measurement circuit can also be designed in the test circuit.
[0065] The NAND gate delay measurement circuit includes: a ring oscillator and a frequency divider;
[0066] The ring oscillator includes: 2X + 1 cascaded NAND gates, where the output terminal of each stage of the NAND gate is connected to the first input terminal of the next stage of the NAND gate, and the second input terminal of each stage of the NAND gate is connected to the enable input signal; the output terminal of the last stage of the NAND gate is connected to the input terminal of the first stage of the NAND gate;
[0067] The input terminal of the frequency divider is connected to the output terminal of the last NAND gate, receiving the oscillation signal output by the ring oscillator. The output terminal of the frequency divider outputs a frequency-divided signal of the oscillation signal, which is a test signal for measuring the delay of the NAND gate, where X≥50.
[0068] Figure 5 As shown, there are 101 cascaded NAND gates. Each time the delay of the 101 cascaded NAND gates in the ring oscillator accumulates to cell_delay×101, where cell_delay refers to the delay of a logic cell. Without considering the delay of the last NAND gate that reverses the signal to cause the circuit to oscillate, cell_delay×100 becomes half of the oscillation period. The waveform is schematically shown as Figure 6 shown. Among them, the NAND cell delay indicates the delay of the last NAND gate that reverses the signal. 100 levels of cell delay is half of the oscillation period.
[0069] The oscillation signal (OUT in the figure) output by the ring oscillator is frequency-divided by the frequency divider and then the frequency-divided signal osc_div_out is output. It is measured that cell_delay = t0 = T / (2×N) / 101.
[0070] The test signal generation circuit provided in this embodiment can be applied to specific application scenarios such as integrated circuit design and verification, delay chain calibration, and pulse width modulation.
[0071] The pulse signal generation circuit for measuring the delay of an integrated circuit logic cell provided in the embodiment of the present invention uses a pulse signal generation circuit, a test oscillation loop, and a pulse signal processing circuit to realize the generation, latching of the pulse signal, and generation of the status signal of the pulse signal. By testing the width of the generated pulse signal, the delay change of the logic cell is accurately captured, thereby improving the measurement accuracy of the delay of the logic cell and the reliability of the test result. The circuit structure is simple and easy to implement, occupies a small area in the integrated circuit, is suitable for scenarios such as integrated circuit design verification and fault diagnosis, and can effectively meet the measurement requirements of high-frequency, low-power, and high-integration integrated circuits.
[0072] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A pulse signal generation circuit for measuring the delay of an integrated circuit logic unit, characterized in that, The pulse signal generation circuit includes: a pulse signal generation circuit, a test oscillator loop, and a pulse signal processing circuit; The pulse signal generation circuit includes: 2N cascaded logic units and an exclusive-OR gate; the output terminal of the last logic unit among the 2N cascaded logic units is connected to the first input terminal of the exclusive-OR gate, the first input terminal of the first logic unit among the 2N cascaded logic units and the second input terminal of the exclusive-OR gate are both connected to the enable input signal input at the input terminal of the pulse signal generation circuit; the output terminal of the exclusive-OR gate is the output terminal of the pulse signal generation circuit, outputting a pulse signal; N≥50; The test oscillator loop includes 2M + 1 cascaded NAND gates. Among them, the first input terminal of the first NAND gate is connected to the output terminal of the pulse signal generation circuit, the first input terminal of each of the remaining NAND gates is connected to a constantly valid input signal, the output terminal of each NAND gate is connected to the second input terminal of the next NAND gate, and the output terminal of the last NAND gate is connected to the second input terminal of the first NAND gate; the output terminals of each NAND gate sequentially output output signals with a fixed phase difference; M≥1; The pulse signal processing circuit is respectively connected to the output terminal of the pulse signal generation circuit and the output terminals of each NAND gate of the test oscillator loop, and outputs the status signal of the pulse signal.
2. The pulse signal generating circuit according to claim 1, wherein The pulse signal processing circuit includes: two multi-bit latches, an exclusive-NOR gate, and a multi-bit register; The input terminal of the first multi-bit latch inputs a first timing input signal composed of the 2M + 1 output signals, the enable terminal of the first multi-bit latch is connected to the output terminal of the pulse signal generation circuit, inputting the pulse signal, and the first output terminal of the first multi-bit latch outputs a first pulse status latch signal; The input terminal of the second multi-bit latch inputs a second timing input signal composed of the 2M + 1 output signals, and there is a phase difference between the second timing input signal and the first timing input signal; the enable terminal of the second multi-bit latch is connected to the output terminal of the pulse signal generation circuit, inputting the pulse signal, and the first output terminal of the second multi-bit latch outputs a second pulse status latch signal; The two input terminals of the exclusive-NOR gate are respectively connected to the first output terminal of the first multi-bit latch and the first output terminal of the second multi-bit latch; The input terminal of the multi-bit register is connected to the output terminal of the exclusive-NOR gate, the clock signal terminal of the multi-bit register is connected to the integrated circuit system clock, and the output terminal of the multi-bit register outputs the status signal of the pulse signal.
3. The pulse signal generation circuit according to claim 2, wherein The second output terminal of the first multi-bit latch outputs a reset signal; The second output terminal of the second multi-bit latch is left empty.
4. The pulse signal generation circuit according to claim 1, wherein The logic unit includes: basic logic gates.
5. The pulse signal generating circuit according to claim 1 or 3, characterized in that, Specifically, the logic unit includes one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an exclusive-OR gate, or an exclusive-NOR gate.
6. The pulse signal generation circuit according to claim 1, wherein The logic units in the pulse signal generation circuit and the integrated circuit logic units are prepared through the same process.
7. The pulse signal generation circuit according to claim 1, wherein The pulse signal generation circuit further includes: a NAND gate delay measurement circuit; The NAND gate delay measurement circuit includes: a ring oscillator and a frequency divider; The ring oscillator includes: 2X + 1 cascaded NAND gates; wherein, the output terminal of each stage of NAND gate is connected to the first input terminal of the next stage of NAND gate, the second input terminal of each stage of NAND gate is connected to an enable input signal; the output terminal of the last stage of NAND gate is connected to the input terminal of the first stage of NAND gate; The input terminal of the frequency divider is connected to the output terminal of the last stage of NAND gate to receive the oscillation signal output by the ring oscillator, and the output terminal of the frequency divider outputs a frequency-divided signal of the oscillation signal, which is a test signal for measuring the delay of the NAND gate, X≥50.