VDMOSFET device with embedded drain source

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device with an embedded drain source, which comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a substrate layer, a diffusion layer, a grid electrode, a metal source electrode, a P-well layer and an N-well layer, and the bottom layer of the substrate layer forms an isolated N-well layer through ion implantation; in the preparation of a substrate layer in a single MOS cellular structure, a shape with a convex middle and low-lying two sides is formed by injecting a small amount of ions on two sides and a large amount of ions in the middle; an isolation oxide layer is deposited on the surface of the grid electrode, the drain electrode is in ohmic contact with the isolation N well layer and the substrate layer, and the metal source electrode is in ohmic contact with the heavily-doped N well layer. According to the utility model, the isolated N-well layer is formed through ion implantation in the substrate layer, and the charge resistance of the isolated N-well layer is greater than that of the substrate layer, so that the minimum path of the gate-drain is not easily broken down by charges after the gate voltage is accessed to the gate.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically, to a VDMOSFET device with embedded source and drain. Background Art

[0002] The VDMOSFET device has significant advantages of high frequency and low loss, and is widely used in fields such as electric vehicles, photovoltaic inverters, and charging piles. The semiconductor material silicon carbide has characteristics such as a wide bandgap, high breakdown field strength, high thermal conductivity, high saturated electron migration rate, and stable physical and chemical properties, and is applicable to high temperature, high frequency, high power, and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Utilizing the unique physical, chemical, and electrical characteristics of the VDMOSFET structure, it is a semiconductor material with great development potential in extreme application fields such as high temperature, high frequency, high power, and radiation resistance.

[0003] A prior patent discloses a transistor with embedded source and drain and its manufacturing method (publication number CN111081764A). The transistor structure includes: a weakly p-type doped silicon substrate; trench isolation regions embedded at both ends of the silicon substrate, a heavily N-type doped drain and a heavily N-type doped source embedded near both ends of the silicon substrate; a gate oxide layer located on the silicon substrate; a gate located on the gate oxide layer; a gate contact located on the gate; and sidewalls located on the sides of the gate. In the technology disclosed in this patent, after the gate accesses the gate voltage, an electric field will be formed in the diffusion layer and the substrate layer. This electric field will interfere with the diffusion layer and the substrate layer in adjacent MOS cells, resulting in a problem that a small amount of charge in the diffusion layer drifts outward, thus affecting the current stability after the VDMOSFET structure is turned on. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a VDMOSFET device with embedded source and drain, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a VDMOSFET device with embedded source and drain includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a substrate layer, a diffusion layer, a gate, a metal source, a P-well layer, and an N-well layer. The bottom layer of the substrate layer forms an isolated N-well layer through ion implantation.

[0006] In the preparation of the substrate layer in a single MOS cell structure, ion implantation is carried out with a small amount on both sides and a large amount in the middle to form a shape with a middle bulge and low-lying areas on both sides.

[0007] An isolation oxide layer is deposited on the surface of the gate. The drain is in ohmic contact with both the isolation N-well layer and the substrate layer, and the metal source is in ohmic contact with the heavily doped N-well layer;

[0008] The N-well layer is isolated from the diffusion layer by the P-well layer. When the gate is connected to the gate voltage, a charge channel is formed at a position near the gate inside the P-well layer.

[0009] Furthermore, the P-well layer includes a lightly doped P-well layer 1, a heavily doped P-well layer 1, and a lightly doped P-well layer 2.

[0010] Furthermore, the lightly doped P-well layer 1 between adjacent MOS cells is integrated as a whole.

[0011] Furthermore, the heavily doped P-well layer 1 is located below the N-well layer, and the heavily doped P-well layer 1 isolates the lightly doped P-well layer 2 from the lightly doped P-well layer 1.

[0012] Furthermore, the lightly doped P-well layer 2 is located near the gate position, and the charge channel is formed inside the lightly doped P-well layer 2.

[0013] Furthermore, the N-well layer includes a heavily doped N-well layer and a lightly doped N-well layer, and both the heavily doped N-well layer and the lightly doped N-well layer are in contact with the lightly doped P-well layer 2.

[0014] Furthermore, the lightly doped N-well layer suppresses the drift of charges inside the heavily doped N-well layer.

[0015] Furthermore, the heavily doped N-well layer is doped with high-concentration phosphorus ions by ion implantation;

[0016] Both the isolation N-well layer and the lightly doped N-well layer are doped with low-concentration phosphorus ions by ion implantation.

[0017] Furthermore, the heavily doped P-well layer 1 is doped with high-concentration boron ions by ion implantation;

[0018] Both the lightly doped P-well layer 1 and the lightly doped P-well layer 2 are doped with low-concentration boron ions by ion implantation.

[0019] The beneficial effects of a VDMOSFET device with embedded source and drain of the present utility model are as follows:

[0020] 1. By embedding the metal source into the heavily doped N-well layer in the MOS cell, the present utility model does not require a large gate to cover the VDMOSFET device, which can ensure that the device has the advantages of small size and small on-resistance.

[0021] 2. The utility model provides a P-well layer between adjacent MOS cells, which can ensure that the charges in the diffusion layer move toward the metal source and suppress the charges from drifting toward the diffusion layer in the adjacent MOS cells, thereby ensuring the stability of the VDMOSFET device power amplifier.

[0022] 3. The utility model forms an isolated N-well layer by ion implantation inside the substrate layer. Since the charge resistance of the isolated N-well layer is greater than the charge resistance of the substrate layer, after the gate is connected to the gate voltage, the minimum path between the gate and the drain will not be easily broken down by the charge.

[0023] 4. The utility model reduces the concentration of minority carriers injected into the drift region during the freewheeling period by arranging a lightly doped P- layer in the P+ region, accelerates the speed at which minority carrier holes are swept out of the drift region during the reverse recovery process, improves the minority carrier storage effect of the PN junction, and improves the reverse recovery characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] Figure 1 It is the schematic diagram of VDMOSFET device;

[0026] Figure 2 for Figure 1 A local enlarged and refined image of ;

[0027] Figure 3 It is a schematic diagram of MOS cells in parallel;

[0028] Figure 4 It is a three-dimensional schematic diagram of the utility model.

[0029] In the figure: 1. drain; 2. isolated N-well layer; 3. substrate layer; 4. diffusion layer; 5. gate; 6. metal source; 7. isolation oxide layer; 8. heavily doped N-well layer; 9. lightly doped N-well layer; 10. lightly doped P-well layer 1; 11. heavily doped P-well layer 1; 12. lightly doped P-well layer 2. DETAILED DESCRIPTION

[0030] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0031] like Figures 1-4As shown, according to one aspect of the present utility model, a VDMOSFET device with an embedded drain-source is provided, which includes a plurality of MOS cells arranged in parallel. The MOS cell includes a drain 1, a substrate layer 3, a diffusion layer 4, a gate 5, a metal source 6, a P-well layer, and an N-well layer. The bottom layer of the substrate layer 3 forms an isolated N-well layer 2 through ion implantation (as Figure 1 shown). By embedding the metal source 6 into the heavily doped N-well layer 8 in the MOS cell, there is no need for a large gate 5 to cover the VDMOSFET device, which can ensure that the device has the advantages of small size and small on-resistance.

[0032] In the preparation of the substrate layer 3 in a single MOS cell structure, ion implantation is carried out with a small amount on both sides and a large amount in the middle to form a shape with a middle bulge and low-lying on both sides; an isolation oxide layer 7 is deposited on the surface of the gate 5. The drain 1 is in ohmic contact with both the isolated N-well layer 2 and the substrate layer 3, and the metal source 6 is in ohmic contact with the heavily doped N-well layer 8; the N-well layer and the diffusion layer 4 are isolated by the P-well layer. When the gate 5 is connected to the gate voltage, a charge channel is formed at a position near the gate 5 inside the P-well layer (as Figure 4 shown). The isolated N-well layer 2 is formed by ion implantation inside the substrate layer 3. Since the charge resistance of the isolated N-well layer 2 is greater than that of the substrate layer 3, after the gate 5 is connected to the gate voltage, the minimum path between the gate and the drain will not be easily broken down by charges.

[0033] In this embodiment, the P-well layer includes a lightly doped P-well layer one 10, a heavily doped P-well layer one 11, and a lightly doped P-well layer two 12. The lightly doped P-well layer one 10 between adjacent MOS cells is integrated as a whole. The heavily doped P-well layer one 11 is located on the lower side of the N-well layer, and the heavily doped P-well layer one 11 isolates the lightly doped P-well layer two 12 from the lightly doped P-well layer one 10 (as Figure 3 shown). By providing the lightly doped P-well layer one 10 between adjacent MOS cells, it can ensure that during the movement of charges in the diffusion layer 4 towards the metal source 6, the drift of charges towards the diffusion layer in adjacent MOS cells can be suppressed.

[0034] In this embodiment, the lightly doped P-well layer two 12 is located near the gate 5, and a charge channel is formed inside the lightly doped P-well layer two 12. The N-well layer includes a heavily doped N-well layer 8 and a lightly doped N-well layer 9, and both the heavily doped N-well layer 8 and the lightly doped N-well layer 9 are in contact with the lightly doped P-well layer two 12. The lightly doped N-well layer 9 suppresses the drift of charges inside the heavily doped N-well layer 8.

[0035] In this embodiment, the heavily doped N-well layer 8 is doped with 2.3 - 7.4×10 18 mol / cm 3 phosphorus element by ion implantation; both the isolated N-well layer 2 and the lightly doped N-well layer 9 are doped with 9.2×1015 ~7.4×10 16 mol / cm 3 phosphorus element. The heavily doped P-well layer 11 is doped with 7.3×10 18 ~9.4×10 18 mol / cm 3 of boron element by ion implantation method; the lightly doped P-well layer 10 and the lightly doped P-well layer 12 are both doped with 8.7×10 16 ~2.1×10 17 mol / cm 3 of boron element by ion implantation method.

[0036] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A VDMOSFET device with an embedded drain-source, characterized in that, It includes multiple MOS cells arranged in parallel with each other. The MOS cell includes a drain (1), a substrate layer (3), a diffusion layer (4), a gate (5), a metal source (6), a P-well layer, and an N-well layer. Among them, an isolation N-well layer (2) is formed by ion implantation at the bottom of the substrate layer (3). In the preparation of the substrate layer (3) in a single MOS cell structure, ion implantation with a small amount on both sides and a large amount in the middle is used to form a shape with a middle bulge and low-lying areas on both sides. An isolation oxide layer (7) is deposited on the surface of the gate (5). The drain (1) is in ohmic contact with both the isolation N-well layer (2) and the substrate layer (3). The metal source (6) is in ohmic contact with the heavily doped N-well layer (8). The N-well layer and the diffusion layer (4) are isolated by the P-well layer. When the gate (5) is connected to the gate voltage, a charge channel is formed inside the P-well layer near the gate (5).

2. The VDMOSFET device with an embedded drain-source according to claim 1, characterized in that: The P-well layer includes a lightly doped P-well layer one (10), a heavily doped P-well layer one (11), and a lightly doped P-well layer two (12).

3. The VDMOSFET device with an embedded drain-source according to claim 2, characterized in that: The lightly doped P-well layer one (10) is integrated among adjacent MOS cells.

4. The VDMOSFET device with an embedded drain-source according to claim 3, characterized in that: The heavily doped P-well layer one (11) is located on the lower side of the N-well layer, and the heavily doped P-well layer one (11) isolates the lightly doped P-well layer two (12) from the lightly doped P-well layer one (10).

5. The VDMOSFET device with an embedded drain-source according to claim 4, characterized in that: The lightly doped P-well layer two (12) is located near the gate (5), and a charge channel is formed inside the lightly doped P-well layer two (12).

6. The VDMOSFET device with an embedded drain-source according to claim 1, wherein: The N-well layer includes a heavily doped N-well layer (8) and a lightly doped N-well layer (9). Both the heavily doped N-well layer (8) and the lightly doped N-well layer (9) are in contact with the lightly doped P-well layer two (12).

7. The VDMOSFET device with an embedded drain-source according to claim 6, characterized in that: The lightly doped N-well layer (9) inhibits the drift of charges inside the heavily doped N-well layer (8).

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