Semiconductor shockproof chip tray

Abstract

The utility model discloses a semiconductor shockproof chip tray, which belongs to the technical field of chip trays and comprises a tray main body, two sides of the tray main body are respectively provided with a plurality of chip grooves and a plurality of stacking grooves, the peripheral side of the inner wall of each chip groove is provided with an abutting pad, chips are placed in the chip grooves, and the stacking grooves are arranged in the abutting pads. A stacking groove is formed in the bottom of the tray body, a limiting plate is arranged on the peripheral side of the stacking groove, a mounting groove is formed in the limiting plate, a buffer pad is connected into the mounting groove, an anti-vibration pad is arranged on the peripheral side of the bottom of the stacking groove, the adjacent tray bodies are stacked together, the top of the chip abuts against the anti-vibration pad, and the peripheral side of the chip abuts against the buffer pad. The abutting pad abuts against the bottom of the chip. The chip grooves and the stacking grooves are formed in the two sides of the tray body, the abutting pads are arranged on the inner walls of the chip grooves, the abutting pads are anti-static elastic rubber pads, the chip grooves are separated through the abutting pads, it is guaranteed that the anti-static effect can be achieved in the transportation process, and chips are prevented from being damaged.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip trays, and particularly relates to a semiconductor shock-proof chip tray. Background Art

[0002] Chip trays, as indispensable key components in semiconductor packaging and testing and electronic product manufacturing, are of great importance. These trays are designed specifically for chip packaging and testing, and not only have multiple functions such as anti-static, high-temperature resistance, and anti-vibration, but also can effectively protect chips from damage by the external environment, ensuring the integrity and reliability of chips during manufacturing, testing, and transportation.

[0003] However, the existing chip trays are prone to generate static electricity due to friction during transportation, which poses a potential danger to the chips. At the same time, the existing chip trays have poor shock resistance and are prone to damage the chips during transportation. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a semiconductor shock-proof chip tray to solve the problems that the existing chip trays are prone to generate static electricity due to friction during transportation, which poses a potential danger to the chips, and at the same time, the existing chip trays have poor shock resistance and are prone to damage the chips during transportation.

[0005] To achieve the above purpose, the utility model adopts the following technical scheme: a semiconductor shock-proof chip tray, including a tray body. A number of chip slots and a number of stacking slots are respectively arranged on both sides of the tray body. An abutting pad is arranged on the circumferential side of the inner wall of the chip slot. The chip is placed in the chip slot. A limiting plate is arranged on the circumferential side of the stacking slot. An installation slot is arranged in the limiting plate. A buffer pad is connected in the installation slot. An anti-seismic pad is arranged on the circumferential side of the bottom of the stacking slot. Adjacent tray bodies are stacked together. The top of the chip abuts against the anti-seismic pad, and the circumferential side abuts against the buffer pad. The abutting pad abuts against the bottom of the chip.

[0006] As a further description of the above technical scheme:

[0007] A reinforcing abutting plate is arranged between adjacent chip slots, and limiting bodies are arranged on both sides of the reinforcing abutting plate.

[0008] As a further description of the above technical scheme:

[0009] Reinforcing rib plates are arranged between adjacent stacking slots. The reinforcing rib plates extend upward and are connected to the reinforcing abutting plate. A number of fulcrums are arranged between the reinforcing rib plates.

[0010] As a further description of the above technical scheme:

[0011] The limiting body forms a downwardly extending limiting groove on the periphery of the stacking groove. The limiting groove is located on both sides of the reinforcing abutting plate, and the limiting bodies and the limiting grooves on the adjacent stacked tray bodies match each other.

[0012] As a further description of the above technical solution:

[0013] Handles are provided on both sides of the tray body.

[0014] As a further description of the above technical solution:

[0015] A number of through holes are provided in the chip groove.

[0016] In summary, due to the adoption of the above technical solution, the beneficial effects of the present utility model are as follows:

[0017] 1. In the present utility model, by providing a chip groove and a stacking groove on both sides of the tray body, an abutting pad is provided on the inner wall of the chip groove. The abutting pad is made of an anti-static elastic rubber pad, and each chip groove is separated by the abutting pad, so as to ensure that it can achieve the anti-static problem during transportation and avoid damage to the chips.

[0018] 2. In the present utility model, by providing a buffer pad and a shock-resistant pad in the stacking groove at the bottom of the tray body, when the upper and lower tray bodies are stacked, the top of the chip can abut against the shock-resistant pad, and the periphery can abut against the buffer pad. This structure enables the tray bodies to be stacked and transported, and can achieve the functions of shock resistance and anti-static, improve the safety of the chips during transportation, avoid damage to the chips, and ensure the quality of the chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0020] Figure 1 Is a three-dimensional view of a semiconductor shock-proof chip tray Figure 1 .

[0021] Figure 2 Is a three-dimensional view of a semiconductor shock-proof chip tray Figure 2 .

[0022] Legend Explanation:

[0023] 1 - Tray body; 2 - Chip slot; 3 - Stacking slot; 4 - Contact pad; 5 - Limiting plate; 6 - Installation slot; 7 - Buffer pad; 8 - Anti-seismic pad; 9 - Reinforcing contact plate; 10 - Limiting body; 11 - Reinforcing rib plate; 12 - Fulcrum; 13 - Limiting groove; 14 - Handle; 15 - Through hole. Detailed implementation manner

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0025] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0027] It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0028] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "inner", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0029] In the description of the present utility model, it should also be noted that unless otherwise clearly defined and limited, the terms "set", "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0030] Please refer to Figure 1-2 , the present utility model provides a technical solution: a semiconductor shock-proof chip tray, including a tray main body 1, on both sides of the tray main body 1, there are respectively provided a plurality of chip slots 2 and a plurality of stacking slots 3. An abutting pad 4 is provided on the circumferential side of the inner wall of the chip slot 2. A chip is placed in the chip slot 2. A limiting plate 5 is provided on the circumferential side of the stacking slot 3. An installation slot 6 is provided in the limiting plate 5. A buffer pad 7 is connected in the installation slot 6. An earthquake-resistant pad 8 is provided on the circumferential side of the bottom of the stacking slot 3. Adjacent tray main bodies 1 are stacked together. The top of the chip abuts against the earthquake-resistant pad 8, and the circumferential side abuts against the buffer pad 7. The abutting pad 4 abuts against the bottom of the chip.

[0031] A reinforcing abutting plate 9 is provided between adjacent chip slots 2. Limiting bodies 10 are provided on both sides of the reinforcing abutting plate 9.

[0032] A reinforcing rib plate 11 is provided between adjacent stacking slots. The reinforcing rib plate 11 extends upward and is connected to the reinforcing abutting plate 9. A plurality of fulcrums 12 are provided between the reinforcing rib plates 11. To improve the stability of the overall structure.

[0033] The limiting body 10 forms a downwardly extending limiting groove 13 on the circumferential side of the stacking slot 3. The limiting groove 13 is located on both sides of the reinforcing abutting plate 9. The limiting bodies 10 and the limiting grooves 13 on adjacent stacked tray main bodies 1 match each other. To avoid stacking and prevent displacement.

[0034] Handles 14 are provided on both sides of the tray main body 1.

[0035] A plurality of through holes 15 are provided in the chip slot 2. The provision of the through holes reduces stress when the chip is stressed during transportation.

[0036] Working principle: By setting chip slots and stacking slots on both sides of the tray body, anti-contact pads are provided on the inner walls of the chip slots. The anti-contact pads are made of anti-static elastic rubber pads, and each chip slot is separated by an anti-contact pad, so as to ensure that anti-static problems can be achieved during transportation and avoid damage to the chips. At the same time, by setting buffer pads and anti-seismic pads in the stacking slots at the bottom of the tray body, when the upper and lower tray bodies are stacked, the top of the chip can be in contact with the anti-seismic pad, and the periphery can be in contact with the buffer pad. This structure enables multiple tray bodies to be stacked for transportation, and can achieve the functions of anti-seismic and anti-static, improving the safety of the chips during transportation, avoiding damage to the chips, and ensuring the quality of the chips.

[0037] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution of the present invention and its inventive concept, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. A semiconductor shock-proof chip tray, characterized in that, It includes a tray body, on both sides of which there are respectively provided a number of chip slots and a number of stacking slots. An abutting pad is provided on the circumferential side of the inner wall of the chip slot, and a chip is placed in the chip slot. A limiting plate is provided on the circumferential side of the stacking slot, and an installation slot is provided in the limiting plate. A buffer pad is connected in the installation slot. An anti-seismic pad is provided on the circumferential side of the bottom of the stacking slot. Adjacent tray bodies are stacked together, the top of the chip abuts against the anti-seismic pad, the circumferential side abuts against the buffer pad, and the abutting pad abuts against the bottom of the chip.

2. The semiconductor anti-vibration chip tray according to claim 1, wherein A reinforcing abutting plate is provided between adjacent chip slots, and limiting bodies are provided on both sides of the reinforcing abutting plate.

3. The semiconductor anti-vibration chip tray according to claim 2, wherein, A reinforcing rib plate is provided between adjacent stacking slots, the reinforcing rib plate extends upward and is connected to the reinforcing abutting plate, and a number of fulcrums are provided between the reinforcing rib plates.

4. A semiconductor shock-proof chip tray according to claim 2, characterized in that, The limiting body forms a downward-extending limiting slot on the circumferential side of the stacking slot, the limiting slot is located on both sides of the reinforcing abutting plate, and the limiting bodies and the limiting slots on adjacent stacked tray bodies match each other.

5. A semiconductor shock-proof chip tray according to claim 1, characterized in that, Handles are provided on both sides of the tray body.

6. A semiconductor shock-proof chip tray according to claim 1, characterized in that, A number of through holes are provided in the chip slot.

Images