Display substrate and display device
By setting overlapping first and second vias on the display substrate, the problem of poor poop in the liquid crystal display product is solved, and the uniformity of display uniformity and transmittance is achieved, and the picture quality is improved.
Patent Information
- Application Number
- CN202422408140.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-09-30
AI Technical Summary
In high PPI liquid crystal display products, due to the high thickness of the organic film and the small vias, the liquid crystal alignment film material is not easy to flow into the vias, resulting in poor pitting and affecting the quality of the picture.
The first via hole and the second via hole are provided on the display substrate so that the orthoprojected portions on the substrate substrate overlap, ensuring that the liquid crystal alignment film material fully flows into the organic film via holes and achieves uniform diffusion.
Effectively avoid display pitfalls, improve display uniformity and transmittance consistency, and improve the screen quality of the display product.
Smart Images
Figure CN223092264U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technologies. More specifically, it relates to a display substrate and a display device. Background Art
[0002] High pixel density (Pixels Per Inch, PPI) display products are increasingly favored by users, but people's requirements for display quality are getting higher and higher. In high-PPI liquid crystal display products, in order to reduce the load, an organic film solution is generally adopted, that is, an organic film is used between the driving circuit and the pixel electrode layer of the display substrate. Since the thickness of the organic film is relatively high and the vias in high-PPI display products are small, the via size in the organic film is deep and small, and the alignment film material (PI) in the liquid crystal layer is not easily introduced into the vias, resulting in defective stippling, which seriously affects the picture quality. Summary of the Utility Model
[0003] An object of the present disclosure is to provide a display module and a display device to solve at least one of the problems existing in the prior art.
[0004] To achieve the above object, the present disclosure adopts the following technical solutions:
[0005] A first aspect of the present disclosure provides a display substrate, including a first substrate, a second substrate disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate.
[0006] The first substrate includes: a source-drain metal layer, an organic layer, a common electrode signal layer, a first insulating layer, and a pixel electrode layer stacked on a substrate.
[0007] The organic layer includes a plurality of first vias, and the first insulating layer includes a plurality of second vias penetrating through to the organic layer.
[0008] The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the first via on the substrate.
[0009] Optionally, the first substrate includes: a driving circuit layer, a common electrode layer, a common electrode signal layer, a first insulating layer, and a pixel electrode layer stacked on a substrate, and the pixel electrode layer includes pixel electrodes.
[0010] The driving circuit layer includes: an active layer and a source-drain metal layer stacked on a substrate, and the source-drain metal layer includes a first connection line.
[0011] The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first connection line on the substrate, and the pixel electrode is electrically connected to the first connection line via the first via and the second via.
[0012] The orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate do not overlap with the orthographic projection of the active layer on the substrate.
[0013] Optionally, the first substrate includes: a driving circuit layer, a common electrode layer, a common electrode signal layer, a first insulating layer, and a pixel electrode layer stacked on the substrate, and the pixel electrode layer includes pixel electrodes;
[0014] The driving circuit layer includes: an active layer and a source-drain metal layer stacked on the substrate, and the source-drain metal layer includes a source electrode and a drain electrode.
[0015] Wherein, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the drain electrode on the substrate, and the pixel electrode is electrically connected to the drain electrode via the first via and the second via, or the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the source electrode on the substrate, and the pixel electrode is electrically connected to the source electrode via the first via and the second via; and
[0016] Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate overlap with the orthographic projection of the active layer on the substrate.
[0017] Optionally, the driving circuit layer includes: a gate layer, an active layer, and a source-drain metal layer stacked on the substrate, or
[0018] The driving circuit layer includes: an active layer, a gate layer, and a source-drain metal layer stacked on the substrate.
[0019] Optionally, the first via and the second via are connected to form an opening, and at least one cross-section of the opening is stepped.
[0020] Optionally, the display substrate further includes: a common electrode layer disposed between the organic layer and the common electrode signal layer.
[0021] The orthographic projection of the common electrode layer on the substrate does not overlap with the orthographic projection of the first via on the substrate, and the orthographic projection of the common electrode layer on the substrate does not overlap with the orthographic projection of the second via on the substrate.
[0022] Optionally, the orthographic projection of the first via on the substrate falls within the orthographic projection of the source-drain metal layer on the substrate.
[0023] Optionally, the orthographic projection of the first via on the substrate partially overlaps with the orthographic projection of the source-drain metal layer on the substrate.
[0024] Optionally, the display substrate further includes: a second insulating layer disposed between the organic layer and the source-drain metal layer, and the second insulating layer includes a third via, and the orthographic projection of the third via on the substrate falls within the orthographic projection of the first via on the substrate.
[0025] The second aspect of the present disclosure provides a display device, including the display substrate described above.
[0026] The beneficial effects of the present disclosure are as follows:
[0027] In view of the existing problems at present, the present disclosure provides a display substrate and a display device. By overlapping the orthographic projection of the first vias provided in the organic layer on the substrate with the orthographic projection of the second vias in the first insulating layer under the pixel electrode on the substrate, the liquid crystal alignment film material in the liquid crystal layer can fully flow into the organic film vias, ensuring the uniform diffusion of the liquid crystal alignment film in the area around the vias, ensuring the consistency of the overall transmittance of the display product, avoiding display moiré, improving the display uniformity, and having broad application prospects. Description of the Drawings
[0028] The following further describes in detail the specific embodiments of the present disclosure with reference to the drawings.
[0029] Figure 1 Showing a schematic top view of a display substrate in the related art;
[0030] Figure 2 and Figure 3 Showing a scanning electron microscope image of the organic layer via region in the display substrate in the related art;
[0031] Figure 4 Showing a schematic diagram of a display substrate in the related art;
[0032] Figure 5 Showing a cross-sectional view taken along line AA' in Figure 4 ;
[0033] Figure 6 Showing a schematic top view of a display substrate according to an embodiment of the present disclosure;
[0034] Figure 7 Showing a cross-sectional view taken along line BB' in Figure 6 ;
[0035] Figure 8 Showing a cross-sectional view taken along line CC' in Figure 6 ;
[0036] Figure 9 Showing a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure. Specific Embodiments
[0037] To more clearly illustrate the present disclosure, the following further describes the present disclosure in conjunction with embodiments and the accompanying drawings. Similar components in the drawings are denoted by the same or similar reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present disclosure.
[0038] It should be noted that the terms "having", "including", "comprising", etc. described in the present disclosure all have an open meaning. That is, when describing that a module "has", "includes", or "comprises" a first element, a second element, and / or a third element, it means that the module includes other elements in addition to the first element, the second element, and / or the third element. In addition, the ordinal numbers such as "first", "second", and "third" in the present disclosure are not intended to limit the specific order, but only to distinguish each part.
[0039] The terms "on...", "formed on...", and "disposed on..." described in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, that is, there are other layers between the two layers.
[0040] In addition, in the present disclosure, the term "co-layer setting" means that two layers, components, members, elements, or parts can be formed by the same preparation process (such as a patterning process, etc.), and generally, these two layers, components, members, elements, or parts are formed of the same material. For example, when two or more functional layers are co-layer set, it means that these co-layer set functional layers can be formed by using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.
[0041] In the related art, liquid crystal display products, especially high-PPI liquid crystal display products, have problems of poor display with moiré. After research and analysis, the inventor found that the moiré occurs in the display area of the display product, and specifically occurs in the organic film pixel vias and the areas around the vias. Figure 1 A schematic top view showing the display area of a liquid crystal display substrate with moiré defects is shown. In the figure, the vias and the areas around the vias are outlined by a dashed box. As can be seen from the figure, there are vias with no PI at all, vias with partial PI, and vias with no PI at all, and the PI diffusion in the areas around the three types of vias with no PI, partial PI, and no PI in the vias is uneven. Figure 2 A scanning electron microscope image showing a via with no PI is shown, Figure 3 A scanning electron microscope image showing a via with PI is shown. The uneven diffusion of PI in the area around the via results in different liquid crystal driving here from the surrounding area, so that the light transmittance is different, thus forming a brightness difference visually, and further leading to moiré defects.
[0042] Further referring to Figure 4 andFigure 5 As shown, in the analysis and research, the inventors found that the main reason for the above-mentioned defects lies in that in liquid crystal display products, especially in high-PPI liquid crystal display products, in order to reduce the load, a relatively thick organic layer is provided under the pixel electrode of the display substrate. Refer to Figure 5 As shown, the organic layer is provided between the driving circuit layer and the pixel electrode layer (ITO2). The driving circuit layer includes film layers such as a gate layer, a gate insulating layer, an active layer, a source-drain metal layer, and an insulating layer 1. There is an insulating layer 2 between ITO2 and the organic layer, and this insulating layer 2 is usually an insulating layer that separates the common electrode layer (ITO1) and the common electrode signal layer thereon from ITO2. During the display driving process, ITO2 needs to receive a driving signal from the source-drain metal layer through a via hole that penetrates to the source-drain metal layer. Currently, the orthographic projection of the via hole in the insulating layer 2 on the substrate falls within the orthographic projection of the via hole in the organic layer on the substrate. Since the film thickness of the organic layer is much greater than that of other film layers, with a thickness of greater than or equal to 2.5 μm. Considering the high PPI requirement of the display product, the size of this via hole is very small. Such a deep and small via hole is not conducive to the diffusion of PI, thus causing the above-mentioned display defects, and the defect rate is almost 100%.
[0043] To solve the above technical problems, an embodiment of the present disclosure provides a display substrate, including a first substrate, a second substrate disposed in a facing manner, and a liquid crystal layer disposed between the first substrate and the second substrate.
[0044] The first substrate includes: a source-drain metal layer, an organic layer, a common electrode signal layer, a first insulating layer, and a pixel electrode layer stacked on the substrate.
[0045] The organic layer includes a plurality of first via holes, and the first insulating layer includes a plurality of second via holes that penetrate to the organic layer.
[0046] The orthographic projection of the second via hole on the substrate overlaps with the orthographic projection of the first via hole on the substrate.
[0047] In this embodiment, by overlapping the orthographic projection of the first via hole provided in the organic layer on the substrate with the orthographic projection of the second via hole in the first insulating layer under the pixel electrode on the substrate, it can be ensured that the liquid crystal alignment film material in the liquid crystal layer fully flows into the organic film via hole, thereby ensuring the uniform diffusion of the liquid crystal alignment film in the area around the via hole, ensuring the consistency of the overall transmittance of the display product, avoiding display dots, and improving the display uniformity.
[0048] The structure and advantages of the embodiments of the present disclosure will be described in detail below with specific examples.
[0049] Figure 6 A top view of the display substrate according to an embodiment of the present disclosure is shown. Figure 7 Shown according toFigure 6 A schematic cross-sectional view taken along line BB' in Figure 8 is shown according to Figure 6 A schematic cross-sectional view taken along line CC' in
[0050] In a specific example, it is shown that the substrate includes a first substrate and a second substrate arranged in a facing manner, and a liquid crystal layer disposed between the first substrate and the second substrate.
[0051] Referring to Figure 7 and Figure 8 as shown, the first substrate includes: a source-drain metal layer 104, an organic layer 106, a common electrode signal layer 110, a first insulating layer 108, and a pixel electrode layer 109 that are stacked on the substrate 100.
[0052] Among them, the source-drain metal layer 104 may include data signal lines 104-1 that provide data signals required for display and source / drain electrodes 104-2 of thin-film transistors. The common electrode signal layer 110 is used to provide a common electrode signal to the common electrode. The pixel electrode layer 109 includes pixel electrodes 109-1 arranged in an array (specific reference numerals can be seen in Figure 6 ). In this example, the pixel electrode 109-1 can be a hollow pattern. The first insulating layer 108 is disposed between the common electrode signal layer 110 and the pixel electrode layer 109 to electrically isolate the common electrode signal line from the pixel electrode 109-1. The first insulating layer 108 can be an inorganic material, usually referred to as the PVX2 layer.
[0053] The organic layer 106 includes a plurality of first vias TK1, and the first insulating layer 108 includes a plurality of second vias TK2 that penetrate through to the organic layer 106.
[0054] Specifically, referring to Figure 6 and Figure 7 as shown, the orthographic projection of the second via TK2 on the substrate 100 overlaps with the orthographic projection of the first via TK1 on the substrate 100.
[0055] Specifically, the first via TK1 and the second via TK2 are connected to form an opening, and at least one cross-section of the opening is stepped.
[0056] With this setting, by using the first vias TK1 and TK2 with partially overlapping settings, a part of the second via TK2 is located on the surface of the organic layer 106 away from the substrate 100, so that a step is formed from the surface of the first insulating layer 108 away from the substrate 100 to the surface of the organic layer 106 away from the substrate 100, and then a second step is formed from the surface of the organic layer 106 away from the substrate 100 to the surface of the source-drain metal layer in the first via TK1. When the PI material is coated on the first substrate, the stepped shape forms a guiding effect on the PI material to help the PI diffuse uniformly, thereby effectively improving the problem of pit defects.
[0057] The first substrate includes a driving circuit layer stacked between the substrate 100 and the organic layer 106, and thin film transistors for driving the pixel electrodes 109-1 are disposed in the driving circuit layer. The thin film transistors are provided in one-to-one correspondence with the pixel electrodes 109-1. When turned on, the data signals accessed via the data signal lines 104-1 are provided to the pixel electrodes 109-1.
[0058] Continue to refer to Figure 6 and Figure 7 As shown, in this example, the first via TK1 and the second via TK2 are disposed outside the thin film transistor, that is, the orthographic projections of the first via TK1 and the second via TK2 on the substrate 100 do not overlap with the orthographic projection of the active layer 103 on the substrate 100.
[0059] Specifically refer to Figure 6 and 7 As shown, in this example, the driving circuit layer includes: a gate layer 101, a gate insulating layer 102, an active layer 103, and a source-drain metal layer 104 that are sequentially stacked on the substrate 100.
[0060] The material of the gate layer 101 can be a multi-layer metal structure, and the film layer combination can be selected from one or a stack of molybdenum / aluminum / molybdenum (Mo / Al / Mo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi). The material of the gate insulating layer 102 can be other inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the gate insulating layer 102 can be a single-layer or multi-layer structure. The active layer 103 can be a Poly polysilicon layer. The film layer combination of the source-drain metal layer 104 can be selected from one or a stack of Mo / Al / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi, etc., and the source-drain electrodes 104 can be a multi-layer structure or a single-layer metal structure. Although Figure 7Not shown in the figure, a buffer layer may also be included between the driving circuit layer and the substrate 100. The material of the buffer layer may be other inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and it may be a single-layer or multi-layer structure.
[0061] In this example, the driving circuit layer includes a gate layer 101, an active layer 103, and a source-drain metal layer 104 stacked on the substrate 100. That is, the thin-film transistor is a bottom-gate structure. However, those skilled in the art should understand that this is not intended to limit the present disclosure. In some embodiments, the thin-film transistor may also be a top-gate structure. In this case, the driving circuit layer includes an active layer 103, a gate layer 101, and a source-drain metal layer 104 stacked on the substrate 100. The specific film layers are: an active layer, a dielectric layer, a gate layer, a gate insulating layer, and a source-drain metal layer are sequentially stacked on the substrate 100. Among them, the material of the dielectric layer may be an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and it may be a single-layer or multi-layer structure, which will not be elaborated herein.
[0062] In this example, the orthographic projections of the first via TK1 and the second via TK2 on the substrate 100 do not overlap with the orthographic projection of the active layer 103 on the substrate 100. The pixel electrode 109-1 is electrically connected to the first connection line via the first via TK1 and the second via TK2, and receives a data signal via the drain 104-2 electrically connected to the first connection line. Therefore Figure 7 The cross-sectional view shows that the part of the source-drain metal layer 104 is the first connection line. It should be understood that when the other end of the first connection line is electrically connected to the drain 104-2, the source of the thin-film transistor will be electrically connected to the data signal line.
[0063] It should be noted that, optionally, the source of the thin-film transistor may also be electrically connected to the first signal line. In this case, the drain of the thin-film transistor is electrically connected to the data signal line.
[0064] Specifically, referring to Figure 7 and Figure 8 shown, the first substrate includes: a driving circuit layer, a common electrode layer 107, a common electrode signal layer 110, a first insulating layer 108, and a pixel electrode layer 109 stacked on the substrate 100. The source-drain metal layer 104 includes a first connection line. The orthographic projection of the first via TK1 on the substrate 100 overlaps with the orthographic projection of the first connection line on the substrate 100. The pixel electrode 109-1 is electrically connected to the first connection line via the first via TK1 and the second via TK2.
[0065] It should be noted that the position of the common electrode layer 107 is not limited to this. It may be located on the side of the common electrode signal layer close to the substrate 100, or on the side of the common electrode signal layer far from the substrate 100.
[0066] In this example, referring to Figure 7 as shown, the common electrode layer 107 is disposed on the side of the pixel electrode layer 109 close to the substrate 100. Usually, the common electrode layer 107 is laid out in a whole layer or divided into multiple large-area regions. Therefore, the common electrode layer 107 is hollowed out in the region of the first via TK1.
[0067] Specifically, the orthographic projection of the common electrode layer 107 on the substrate 100 does not overlap with the orthographic projection of the first via TK1 on the substrate 100, and the orthographic projection of the common electrode layer 107 on the substrate 100 does not overlap with the orthographic projection of the second via TK2 on the substrate 100.
[0068] Referring to Figure 7 as shown, in this example, the orthographic projection of the first via TK1 on the substrate 100 falls within the orthographic projection of the source-drain metal layer 104 on the substrate 100. In this case, two steps are formed from the first insulating layer 108 to the bottom of the via.
[0069] The present disclosure is not limited thereto. Optionally, the orthographic projection of the first via TK1 on the substrate 100 partially overlaps with the orthographic projection of the source-drain metal layer 104 on the substrate 100. In this case, from the first insulating layer 108 to the surface of the source-drain metal layer 104, there are not only two steps from the first insulating layer 108 to the source-drain metal layer 104, but also at least one step from the upper surface of the source-drain metal layer 104 to the gate insulating layer 102.
[0070] Of course, referring to Figure 7 as shown, in this example, the display substrate further includes a second insulating layer 105 disposed between the organic layer 106 and the source-drain metal layer 104. The second insulating layer 105 includes a third via, and the orthographic projection of the third via on the substrate 100 falls within the orthographic projection of the first via TK1 on the substrate 100. The material of the second insulating layer 105 is usually an inorganic material, which is used to protect the source-drain metal layer 104 from moisture and oxygen erosion.
[0071] The display substrate of the above embodiments has been verified to be effective by the inventor on 23.8UHD, and the defective rate has dropped from 100% in the related art to 0%.
[0072] From the perspective of the manufacturing process, in this example, the process flow of the first substrate may sequentially include depositing and patterning a gate layer 101 on a substrate 100 using a mask, depositing a gate insulating layer 102 on the gate layer 101, sequentially forming an active layer 103 and a source / drain metal layer 104 on the gate insulating layer 102. The active layer 103 and the source / drain metal layer 104 may be patterned using one mask or may be patterned using two masks respectively. Then, a second insulating layer 105 and an organic layer 106 are sequentially formed. Then, a common electrode layer 107, a common electrode signal layer 110, a first insulating layer 108, and a pixel electrode layer 109 are sequentially formed. The common electrode layer 107 and the common electrode signal layer 110 may use two masks or share one mask. The first insulating layer 108 is patterned using one mask, and the pixel electrode layer 109 is patterned using one mask.
[0073] It should be noted that the position of the common electrode layer 107 is not limited to this. It may be located on the side of the common electrode signal layer close to the substrate 100 or on the side of the common electrode signal layer far from the substrate 100.
[0074] Through the setting of the present disclosure, the structures of the first via TK1 and the second via TK2 do not add additional mask processes, thereby avoiding additional process costs while avoiding pitting defects.
[0075] Figure 9 Another alternative embodiment is shown.
[0076] Referring to Figure 9 As shown, the difference between this embodiment and the embodiment described above is that the orthographic projections of the first via TK1' and the second via TK2' on the substrate 100 overlap with the orthographic projection of the active layer 103 on the substrate 100. Exemplarily, the source electrode is connected to the data signal line, and the drain electrode is connected to the pixel electrode. That is, in this embodiment, the first via TK1' and the second via TK2' are disposed above the drain 104-2, and the pixel electrode 109-1 is electrically connected to the drain 104-2 via the first via TK1' and the second via TK2'.
[0077] Of course, the drain electrode may also be connected to the data signal line, and the source electrode is connected to the pixel electrode. Examples of this connection method will not be elaborated below.
[0078] Specifically, the first substrate includes: a driving circuit layer stacked on the substrate 100, a common electrode layer 107, a common electrode signal layer 110, a first insulating layer 108, and a pixel electrode layer 109. The pixel electrode layer 109 includes a pixel electrode 109-1. The driving circuit layer includes: an active layer 103 and a source-drain metal layer 104 stacked on the substrate 100. The source-drain metal layer 104 includes a source electrode and a drain electrode 104-2. The orthographic projection of the first via TK1' on the substrate 100 overlaps with the orthographic projection of the drain electrode 104-2 on the substrate 100.
[0079] Specifically, referring to Figure 9 As shown, the driving circuit layer includes: a gate layer 101, a gate insulating layer 102, an active layer 103, and a source-drain metal layer 104 stacked in sequence on the substrate 100.
[0080] The material of the gate layer 101 can be a multi-layer metal structure, and the film layer combination can be selected from one or more of molybdenum / aluminum / molybdenum (Mo / Al / Mo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi) or its stack. The material of the gate insulating layer 102 can be other inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The gate insulating layer 102 can be a single-layer or multi-layer structure. The active layer 103 can be a Poly polysilicon layer. The film layer combination of the source-drain metal layer 104 can be selected from one or more of Mo / Al / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi, etc., and the source-drain electrode 104 can be a multi-layer structure or a single-layer metal structure. Although Figure 7 not shown in the figure, a buffer layer can also be included between the driving circuit layer and the substrate 100. The material of the buffer layer can be other inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and it can be a single-layer or multi-layer structure.
[0081] In this example, the driving circuit layer includes a gate layer 101, an active layer 103, and a source-drain metal layer 104 stacked on the substrate 100. That is, the thin film transistor is a bottom-gate structure. However, those skilled in the art should understand that it is not intended to limit the present disclosure. In some embodiments, the thin film transistor can also be a top-gate structure. In this case, the driving circuit layer includes an active layer 103, a gate layer 101, and a source-drain metal layer 104 stacked on the substrate 100. The specific film layers are: an active layer, a dielectric layer, a gate layer, a gate insulating layer, and a source-drain metal layer are stacked in sequence on the substrate 100. Among them, the material of the dielectric layer can be an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride, and it can be a single-layer or multi-layer structure, which will not be elaborated herein.
[0082] Optionally, the common electrode layer 107 is disposed on the side of the pixel electrode layer 109 close to the substrate 100. Usually, the entire layer of the common electrode layer 107 is laid or divided into multiple large-area regions. Therefore, the common electrode layer 107 is hollowed out in the region of the first via TK1'.
[0083] Specifically, the orthographic projection of the common electrode layer 107 on the substrate 100 does not overlap with the orthographic projection of the first via TK1' on the substrate 100, and the orthographic projection of the common electrode layer 107 on the substrate 100 does not overlap with the orthographic projection of the second via TK2' on the substrate 100.
[0084] Referring to Figure 9 As shown, the figure shows that the orthographic projection of the first via TK1' on the substrate 100 partially overlaps with the orthographic projection of the source-drain metal layer 104 on the substrate 100. In this case, the first insulating layer 108 includes not only two steps from the first insulating layer 108 to the source-drain metal layer 104, but also two steps from the upper surface of the source-drain metal layer 104 to the gate insulating layer 102.
[0085] Of course, the present disclosure is not limited thereto. Optionally, the orthographic projection of the first via TK1' on the substrate 100 falls within the orthographic projection of the source-drain metal layer 104 on the substrate 100. In this case, two steps are formed from the first insulating layer 108 to the bottom of the via.
[0086] Of course, referring to Figure 9 As shown, in this example, the display substrate further includes a second insulating layer 105 disposed between the organic layer 106 and the source-drain metal layer 104. The second insulating layer 105 includes a third via, and the orthographic projection of the third via on the substrate 100 falls within the orthographic projection of the first via TK1' on the substrate 100. The material of the second insulating layer 105 is usually an inorganic material, which is used to protect the source-drain metal layer 104 from moisture and oxygen erosion.
[0087] The display substrate of the above embodiments has been verified to be effective by the inventor on 23.8UHD, and the defective rate has dropped from 100% in the related art to 0%.
[0088] From the perspective of manufacturing process, in this example, the process flow of the first substrate may sequentially include depositing and patterning a gate layer 101 on a substrate 100 using a mask, depositing a gate insulating layer 102 on the gate layer 101, sequentially forming an active layer 103 and a source / drain metal layer 104 on the gate insulating layer 102. The active layer 103 and the source / drain metal layer 104 may be patterned using one mask or may be patterned using two masks respectively. Then, a second insulating layer 105 and an organic layer 106 are sequentially formed. Then, a common electrode layer 107, a common electrode signal layer 110, a first insulating layer 108, and a pixel electrode layer 109 are sequentially formed. The common electrode layer 107 and the common electrode signal layer 110 may use two masks or share one mask. The first insulating layer 108 is patterned using one mask, and the pixel electrode layer 109 is patterned using one mask.
[0089] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the display substrate described in the above embodiment.
[0090] In this embodiment, the display device may be a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a vehicle-mounted display, a digital photo frame, a navigator, etc., including a liquid crystal display substrate, especially a liquid crystal display substrate provided with an organic layer and having a high PPI. By loading the above display substrate, the display device can avoid defective stippling without increasing the process cost, improve the display uniformity, and significantly improve the picture quality and user experience.
[0091] In view of the existing problems, the present disclosure provides a display module and a display device, and by providing a first shielding layer and a second shielding layer electrically connected via a connection part on both sides of the driving circuit layer, a "Faraday cage" structure surrounding the driving circuit layer is formed in the display product, and the "Faraday cage" is used to form electrostatic shielding protection for the thin film transistors in the driving circuit layer, so as to avoid the characteristic shift of the thin film transistors in an electrostatic environment, ensure the normal display of the display product in an electrostatic environment, improve the display effect and the product life, and has broad application prospects.
[0092] Obviously, the above embodiments of the present disclosure are merely examples for clearly explaining the present disclosure, rather than limitations on the implementation manners of the present disclosure. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation manners here. Any obvious changes or modifications derived from the technical solutions of the present disclosure still fall within the protection scope of the present disclosure.
Claims
1. A display substrate, characterized in that, It includes a first substrate, a second substrate provided for a cell, and a liquid crystal layer provided between the first substrate and the second substrate. The first substrate includes: a source-drain metal layer, an organic layer, a common electrode signal layer, a first insulating layer, and a pixel electrode layer stacked on a substrate; The organic layer includes a plurality of first vias, and the first insulating layer includes a plurality of second vias penetrating through to the organic layer; The orthographic projection of the second via on the substrate partially overlaps with the orthographic projection of the first via on the substrate.
2. The display substrate according to claim 1, wherein The first substrate includes: a driving circuit layer, a common electrode layer, the common electrode signal layer, the first insulating layer, and the pixel electrode layer stacked on the substrate, and the pixel electrode layer includes pixel electrodes; The driving circuit layer includes: an active layer and the source-drain metal layer stacked on the substrate, and the source-drain metal layer includes a first connection line; The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first connection line on the substrate, and the pixel electrode is electrically connected to the first connection line via the first via and the second via; The orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate do not overlap with the orthographic projection of the active layer on the substrate.
3. The display substrate according to claim 1, wherein The first substrate includes: a driving circuit layer, a common electrode layer, the common electrode signal layer, the first insulating layer, and the pixel electrode layer stacked on the substrate, and the pixel electrode layer includes pixel electrodes; The driving circuit layer includes: an active layer and the source-drain metal layer stacked on the substrate, and the source-drain metal layer includes a source electrode and a drain electrode; Wherein, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the drain electrode on the substrate, and the pixel electrode is electrically connected to the drain electrode via the first via and the second via, or the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the source electrode on the substrate, and the pixel electrode is electrically connected to the source electrode via the first via and the second via; and Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate overlap with the orthographic projection of the active layer on the substrate.
4. The display substrate according to claim 2 or 3, characterized in that, The driving circuit layer includes: a gate layer, an active layer, and the source-drain metal layer stacked on the substrate, or The driving circuit layer includes: the active layer, a gate layer, and the source-drain metal layer stacked on the substrate.
5. The display substrate according to claim 1, characterized in that, The first via and the second via are connected to form an opening, and at least one cross-section of the opening is stepped.
6. The display substrate according to claim 1, wherein It further includes: A common electrode layer provided between the organic layer and the common electrode signal layer, The orthographic projection of the common electrode layer on the substrate does not overlap with the orthographic projection of the first via on the substrate, and the orthographic projection of the common electrode layer on the substrate does not overlap with the orthographic projection of the second via on the substrate.
7. The display substrate according to claim 2 or 3, characterized in that, The orthographic projection of the first via hole on the substrate falls within the orthographic projection of the source-drain metal layer on the substrate.
8. The display substrate according to claim 2 or 3, wherein The orthographic projection of the first via hole on the substrate partially overlaps with the orthographic projection of the source-drain metal layer on the substrate.
9. The display substrate according to claim 1, wherein Further comprising: A second insulating layer disposed between the organic layer and the source-drain metal layer, the second insulating layer including a third via hole, and the orthographic projection of the third via hole on the substrate falls within the orthographic projection of the first via hole on the substrate.
10. A display device, characterized in that, A display substrate according to any one of claims 1-9.