Fan-out wafer level packaging unit
By forming grooves on the dielectric layer and filling in metal paste, the problem of high cost and unenvironmental protection in fanout wafer-level packaging technology is solved, and the packaging effect is achieved is achieved, which improves reliability and efficiency.
Patent Information
- Application Number
- CN202421712198.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-19
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-07-19
AI Technical Summary
In the existing fan-out wafer-level packaging technology, the conductor circuit forming method of the heavy wiring layer is costly and not environmentally friendly. At the same time, the antenna arrangement in the package is difficult to meet the design needs of light, thin, short and small.
The guide wiring is made by forming grooves on the dielectric layer and filling in metal paste and grinding them. The antenna is embedded in the package, and the cost is reduced and the process is simplified using nano-silver or copper paste materials.
It realizes the low-cost and environmentally friendly process of the conductor circuit, and the packaging products are thin and short, meeting the design needs of electronic products, and improving reliability and use efficiency.
Smart Images
Figure CN223092889U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art
[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.
[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most crucial. Because the conductive lines in the RDL can cause XY-plane electrical extension and interconnection of multiple pads on the bare die, enabling the formation of a relatively dispersed plurality of pads around the bare die, thereby effectively improving the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating XY-plane electrical extension and interconnection is the most crucial for the fabrication of each conductive line in the RDL.
[0004] However, the forming method of each conductive line in the RDL technology applied in the existing FOWLP packaging technology is to use electroless plating forming technology or electroplating forming technology for fabrication. In this way, in addition to the relatively high material cost and manufacturing cost, the existing manufacturing process also does not meet or is not conducive to environmental protection requirements.
[0005] In addition, current wireless communication technologies have been widely applied in electronic products to receive or transmit various wireless signals. However, in order to meet the requirements of the overall light, thin, short, and small design of electronic products, how to set the antenna in the fan-out wafer-level packaging unit is also a problem that needs to be solved. Summary of the Utility Model
[0006] The main purpose of the utility model is to provide a fan-out wafer-level packaging unit, which includes a carrier plate, a first dielectric layer, at least one antenna, at least one bare die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive lines, a third dielectric layer, a plurality of second conductive lines, and an outer protective layer; wherein each of the first conductive lines and each of the second conductive lines are formed by a technology of first filling metal paste into a groove and then grinding to form the conductive lines; wherein each bare die is electrically connected to each antenna; wherein the bare die can be externally electrically connected through each pad around the chip area on the second surface of the bare die, thereby forming the fan-out wafer-level packaging unit, effectively solving the problem that the existing fan-out packaging technology in the module is prone to high manufacturing costs and is not conducive to environmental protection when fabricating each conductive line.
[0007] To achieve the above object, the present utility model provides a fan-out wafer-level packaging unit, which includes a carrier plate, a first dielectric layer, at least one antenna, at least one bare die, a second dielectric layer, at least one conductive post, a plurality of first connection lines, a third dielectric layer, a plurality of second connection lines, and an outer protective layer. The first dielectric layer is disposed on the carrier plate and has at least one first groove formed by horizontal extension. Each antenna is disposed in each first groove. Each bare die is separated from a wafer, and each bare die has a first surface and a second surface opposite thereto. The first surface of each bare die is fixedly disposed on the first dielectric layer and each antenna. The second surface of each bare die has a plurality of chip pads, and the vertical chip area of the second surface is defined as a chip area. The second dielectric layer is disposed on the first dielectric layer, each antenna, and the second surface of each bare die. The second dielectric layer has a plurality of second grooves formed by horizontal extension and at least one perforation penetrating the second dielectric layer. The plurality of chip pads of each bare die are exposed to the outside through the plurality of second grooves, and each antenna is exposed to the outside through each perforation. Each conductive post is formed in each perforation, and each conductive post is electrically connected to each antenna. Each first connection line is composed of metal paste filled in each second groove, and each first connection line is electrically connected to the plurality of chip pads of each bare die respectively. The third dielectric layer is disposed on the second dielectric layer and has a plurality of third grooves formed by horizontal extension. Each third groove communicates with each second groove. Each second connection line is composed of metal paste filled in the plurality of third grooves, and each second connection line is electrically connected to each first connection line and each conductive post. The outer protective layer is disposed on the third dielectric layer and has a plurality of openings, and at least one of the openings is located around the chip area on the second surface of the bare die. Each second connection line is exposed to the outside through the plurality of openings to form a solder pad in each opening. Each bare die is electrically connected to each antenna in sequence through each first connection line and each conductive post. The bare die can be electrically connected to the outside in sequence through the chip pad, the first connection line, the second connection line, and the solder pad located around the chip area on the second surface of the bare die, thereby forming the fan-out wafer-level packaging unit.
[0008] In a preferred embodiment of the present utility model, the carrier plate includes a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate.
[0009] In a preferred embodiment of the present utility model, the metal paste constituting each of the first conductive lines includes silver paste, nano-silver paste, copper paste or nano-copper paste.
[0010] In a preferred embodiment of the present utility model, the metal paste constituting each of the second conductive lines includes silver paste, nano-silver paste, copper paste or nano-copper paste.
[0011] In a preferred embodiment of the present utility model, the first surface of each die is further disposed on the first dielectric layer and each antenna by using a die attach film (DAF).
[0012] In a preferred embodiment of the present utility model, a solder ball is further provided on each opening, and each solder ball can be electrically connected to each pad in a plurality of the openings.
[0013] In a preferred embodiment of the present utility model, the fan-out wafer-level packaging unit can be electrically connected and disposed on a printed circuit board (PCB) by using each solder ball. Description of the Drawings
[0014] Figure 1 It is a schematic plan view of a side cross-section of an application embodiment of the fan-out wafer-level packaging unit of the present utility model.
[0015] Figure 2 It is a schematic plan view of a side cross-section of the carrier plate of the present utility model.
[0016] Figure 3 It is in Figure 2 A schematic plan view of a side cross-section of an antenna disposed in the first dielectric layer on the carrier plate in.
[0017] Figure 4 It is in Figure 3 A schematic plan view of a side cross-section of a die disposed on the first dielectric layer in.
[0018] Figure 5 It is in Figure 4 A schematic plan view of a side cross-section of a second dielectric layer disposed on the die in.
[0019] Figure 6 It is in Figure 5 A schematic plan view of a side cross-section of conductive pillars disposed on the second dielectric layer in.
[0020] Figure 7 It is in Figure 6 A schematic plan view of a side cross-section of a metal paste filled in the second groove in.
[0021] Figure 8 It is inFigure 7 A schematic plan view of a side cross-section of a first conductive connection line ground and formed in a second groove in
[0022] Figure 9 is provided on Figure 8 A schematic plan view of a side cross-section of a third dielectric layer provided on a second dielectric layer in
[0023] Figure 10 is provided on Figure 9 A schematic plan view of a side cross-section of a metal paste filled in a third groove in
[0024] Figure 11 is provided on Figure 10 A schematic plan view of a side cross-section of a second conductive connection line ground and formed in a third groove in
[0025] Figure 12 is provided on Figure 11 A schematic plan view of a side cross-section of an outer protective layer provided on a third dielectric layer in
[0026] Figure 13 is provided on Figure 12 A schematic plan view of a side cross-section of a solder ball provided in an opening in
[0027] Explanation of reference numerals: 1 - Fan-out wafer-level packaging unit; 1a - Chip area; 10 - Carrier board; 20 - First dielectric layer; 21 - First groove; 30 - Antenna; 40 - Bare die; 41 - First surface; 42 - Second surface; 43 - Die pad; 50 - Second dielectric layer; 51 - Second groove; 52 - Through hole; 60 - Conductive post; 70 - First conductive connection line; 70a - Metal paste; 80 - Third dielectric layer; 81 - Third groove; 90 - Second conductive connection line; 90a - Metal paste; 91 - Solder pad; 100 - Outer protective layer; 101 - Opening; 110 - Chip bonding film; 120 - Solder ball; 2 - Printed circuit board. Detailed description of the specific implementation mode
[0028] In conjunction with the drawings, the structure and technical features of the present invention will be described in detail as follows. Each drawing is only used to illustrate the structural relationship and related functions of the present invention. Therefore, the dimensions of each component in each drawing are not drawn according to the actual proportion and are not used to limit the present invention.
[0029] Referring to Figure 12 , the present invention provides a fan-out wafer-level packaging unit 1, which includes a carrier board 10, a first dielectric layer 20, at least one antenna 30, at least one bare die 40, a second dielectric layer 50, at least one conductive post 60, a plurality of first conductive connection lines 70, a third dielectric layer 80, a plurality of second conductive connection lines 90 and an outer protective layer 100.
[0030] The first dielectric layer 20 is disposed on the carrier board 10. The first dielectric layer 20 has at least one first groove 21 formed to extend in the horizontal direction, as Figure 2 shown.
[0031] Each antenna 30 is disposed in each first groove 21, as Figure 3 shown, that is, each antenna 30 is embedded inside the fan-out wafer-level packaging unit 1. Each of the antennas 30 is composed of a patterned circuit layer formed in each first groove 21. Since the composition of the antenna is a common existing technique, it will not be elaborated here.
[0032] Each bare die 40 is divided from a wafer. Each bare die 40 has a first surface 41 and a second surface 42 opposite thereto. The first surface 41 of each bare die 40 is fixedly disposed on the first dielectric layer 20 and each antenna 30. A plurality of pads 43 are provided on the second surface 42 of each bare die 40, and the vertical chip area of the second surface 42 is defined as a chip area 1a, as Figure 4 shown. In Figure 1 this, one bare die 40 is taken as an example for each bare die 40 included in the fan-out wafer-level packaging unit 1, but it is not intended to limit the present invention. In Figure 4 this, two pads 43 are taken as an example for each pad 43 included in each bare die 40, but it is not intended to limit the present invention.
[0033] The second dielectric layer 50 is disposed on the second surface 42 of the first dielectric layer 20, each antenna 30, and each bare die 40. The second dielectric layer 50 has a plurality of second grooves 51 formed to extend in the horizontal direction and at least one through hole 52 penetrating the second dielectric layer 50, as Figure 5 shown; wherein each pad 43 of each bare die 40 is exposed to the outside through each second groove 51, as Figure 5 shown; wherein each antenna 30 is exposed to the outside through each through hole 52, as Figure 5 shown.
[0034] Each conductive pillar 60 is formed in each through hole 52. Each conductive pillar 60 is electrically connected to each antenna 30, as Figure 6 shown.
[0035] Each first conductive connection line 70 is composed of a metal paste 70a filled in each second groove 51. Each first conductive connection line 70 is electrically connected to each pad 43 of each bare die 40, as Figure 8 shown.
[0036] The third dielectric layer 80 is disposed on the second dielectric layer 50. The third dielectric layer 80 has a plurality of third grooves 81 formed to extend in the horizontal direction. Each third groove 81 communicates with each second groove 51, as Figure 9as shown
[0037] Each second conductive line 90 is formed by filling a metal paste 90a provided in each third groove 81. Each second conductive line 90 is electrically connected to each first conductive line 70 and to each conductive post 60, as Figure 11 shown
[0038] The outer protective layer 100 is provided on the third dielectric layer 80. The outer protective layer 100 has a plurality of openings 101 and at least one of the openings 101 is located around the chip region 1a on the second surface 42 of the bare die 40, as Figure 12 shown; wherein each second conductive line 90 is exposed to the outside through each opening 101 to form a solder pad 91 in each opening 101, as Figure 12 shown. In Figure 12 the example of the outer protective layer 100 has 4 openings 101, but it is not intended to limit the present invention
[0039] Each bare die 40 is electrically connected to each antenna 30 in sequence via each first conductive line 70 and each conductive post 60 for processing the reception and transmission of radiation or electromagnetic signals of the antenna 30, as Figure 12 shown
[0040] The bare die 40 can be electrically connected to the outside in sequence via each chip pad 43, each first conductive line 70, each second conductive line 90, and each solder pad 43 located around the chip region 1a on the second surface of the bare die 40, thereby forming the fan - out wafer - level packaging unit 1, as Figure 12 shown
[0041] The process of manufacturing the fan - out wafer - level packaging unit 1 may include the following steps, but is not limited thereto:
[0042] Step S1: Provide a carrier board 10, as Figure 2 shown
[0043] Step S2: Provide a first dielectric layer 20 on the carrier board 10 and form a plurality of first grooves 21 on the first dielectric layer 20, as Figure 2 shown
[0044] Step S3: Form an antenna 30 in each first groove 21, as Figure 3 shown
[0045] Step S4: Dispose a plurality of bare dies 40 separated from at least one wafer on the first dielectric layer 20 and each antenna 30, as Figure 4As shown; each die 40 has a first surface 41 and a second surface 42 opposite thereto. The first surface 41 of each die 40 is disposed on the first dielectric layer 20 and each antenna 30. A plurality of pads 43 are provided on the second surface 42 of each die 40, and the vertical chip region of the second surface 42 is defined as a chip region 1a, as Figure 4 shown.
[0046] Step S5: Using the technique of first injecting metal paste into the grooves and then grinding and forming conductive lines to form a plurality of first conductive lines 70 on the second surface 42 of each die 40: First, a second dielectric layer 50 is laid on the first dielectric layer 20, each antenna 30, and each die 40, as Figure 5 shown. Then, a plurality of second grooves 51 and a plurality of through holes 52 are formed horizontally on the second dielectric layer 50, and each pad 43 of each die 40 can be exposed to the outside through each second groove 51 and each antenna 30 is exposed to the outside through each through hole 52, as Figure 5 shown. After that, a conductive post 60 is formed in each through hole 52 (as Figure 6 shown), and then metal paste 70a is injected into each second groove 51, and the thickness of the metal paste 70a is higher than the surface of the second dielectric layer 50, as Figure 7 shown. Finally, the metal paste 70a higher than the surface of the second dielectric layer 50 is ground so that the surface of the metal paste 70a is flush with the surface of the second dielectric layer 50 to form a plurality of the first conductive lines 70, as Figure 8 shown.
[0047] Step S6: Using the technique of first injecting metal paste into the grooves and then grinding and forming conductive lines to form a plurality of second conductive lines 90 on the second dielectric layer 50 and each first conductive line 60: First, a third dielectric layer 80 is laid on the second dielectric layer 50 and each first conductive line 60, as Figure 9 shown. Then, a plurality of third grooves 81 are formed horizontally on the third dielectric layer 80, and each first conductive line 70 can be exposed to the outside through each third groove 81, as Figure 9 shown. After that, metal paste 90a is injected into each third groove 81, and the thickness of the metal paste 90a is higher than the surface of the third dielectric layer 80, as Figure 10 shown. Finally, the metal paste 90a higher than the surface of the third dielectric layer 80 is ground so that the surface of the metal paste 90a is flush with the surface of the third dielectric layer 80 to form a plurality of the second conductive lines 90, as Figure 11 shown.
[0048] Step S7: Lay an outer protective layer 100 on the third dielectric layer 80, as Figure 12 shown.
[0049] Step S8: Form a plurality of openings 101 in the outer protective layer 100, and make at least one of the openings 101 formed around the chip region 1a on the second surface 42 of the bare die 40, so that each second conductive line 90 can be exposed to the outside through each opening 101 to form a solder pad 91 in each opening 101, as Figure 12 shown.
[0050] Step S9: Perform a dicing operation to dice and form a plurality of fan-out wafer-level packaging units 1, as Figure 12 shown. Each fan-out wafer-level packaging unit 1 shown in Figure 12 is taken as an example of a fan-out wafer-level packaging unit 1 for illustration, but is not intended to limit the present invention.
[0051] The processes of steps S5 to S6 in the process of manufacturing the above-mentioned fan-out wafer-level packaging unit 1 can be regarded as key steps for fabricating the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1. In step S5, a plurality of the first conductive lines 70 are formed on the second surface 42 of each bare die 40 by using a technique of first filling a metal paste into the grooves and then grinding and forming the conductive lines. In step S6, a plurality of the second conductive lines 90 are formed on the second dielectric layer 50 and each first conductive line 60 by using a technique of first filling a metal paste into the grooves and then grinding and forming the conductive lines. Since steps S5 to S6 are both processes that are easy to implement precisely, the process is relatively simplified, which is sufficient to enable each conductive line in the redistribution layer (RDL) to generate XY-plane electrical extension and interconnection effects, and at the same time, the fabricated fan-out wafer-level packaging unit 1 can still maintain or achieve a certain degree of thin, light, short, and small specific effects.
[0052] Referring to Figure 1 , the carrier plate 10 includes a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate, but is not limited thereto.
[0053] Referring to Figure 8 , the metal paste 70a constituting each first conductive line 70 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The above-mentioned nano-silver paste material has characteristics such as low cost, high conductivity, and the ability to sinter at low temperature. However, since the nano-silver paste material is a common material in the prior art, it will not be elaborated here.
[0054] Referring to Figure 11 , the metal paste 90a constituting each second conductive line 90 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto.
[0055] Referring to Figure 4, the first surface 41 of each bare die 40 is further disposed on the first dielectric layer 20 and each antenna 30 by using a die attach film (DAF), but not limited thereto.
[0056] Reference Figure 13 , a solder ball 120 is further provided on each opening 101, but not limited thereto. Each solder ball 120 can be electrically connected to each pad 91 in each opening 101.
[0057] Reference Figure 1 , the fan-out wafer-level packaging unit 1 can further be electrically connected and disposed on a printed circuit board (PCB) 2 by using each solder ball 120, but not limited thereto.
[0058] Compared with the existing fan-out wafer-level packaging unit technology, the fan-out wafer-level packaging unit 1 of the present utility model has the following advantages:
[0059] (1) In the process of manufacturing the fan-out wafer-level packaging unit 1 of the present utility model, preferably steps S5 to S6. Compared with the related manufacturing technologies of the existing fan-out wafer-level packaging unit, the fan-out wafer-level packaging unit 1 of the present utility model enables the conductive lines in the RDL to have XY-plane electrical extension and interconnection effects through the production of the conductive lines in the RDL. At the same time, it can also maintain or achieve a certain degree of thin, light, short, and small effects. These are all simplified and easily precisely implemented steps, especially beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the fan-out wafer-level packaging unit 1 of the present utility model is not only more simplified and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer-level packaging unit 1.
[0060] (2) In the process of forming the conductive lines in the fan-out wafer-level packaging unit 1 of the present utility model, a technology of first injecting metal paste into the grooves and then grinding to form the conductive lines is used to form multiple first conductive lines 70 on the second surface 42 of each bare die 40, and a technology of first injecting metal paste into the grooves and then grinding to form the conductive lines is used to form multiple second conductive lines 90 on the second dielectric layer 50 and each first conductive line 60. Therefore, the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness easily generated in the production of each conductive line by the existing fan-out packaging technology.
[0061] (3) Each antenna 30 in the fan-out wafer-level packaging unit 1 of the present utility model is embedded inside the fan-out wafer-level packaging unit 1, rather than being additionally added externally after the packaging is completed, which helps to simplify the process and reduce the overall thickness of the packaged product, meeting the requirements of the overall light, thin, short, and small design of electronic products.
[0062] The above are only the preferred embodiments of the present utility model, which are illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.
Claims
1. A fan-out wafer-level packaging unit, characterized in that, Comprising: A carrier board; A first dielectric layer provided on the carrier board, the first dielectric layer having at least one first groove formed to extend in a horizontal direction; At least one antenna, each antenna being disposed in each of the first grooves; At least one bare die, each bare die being diced from a wafer, each bare die having a first surface and a second surface opposite thereto, the first surface of each bare die being fixedly disposed on the first dielectric layer and each antenna, and a plurality of pads being provided on the second surface of each bare die, and a vertical chip area of the second surface being defined as a chip area; A second dielectric layer provided on the second surface of the first dielectric layer, each antenna, and each bare die, the second dielectric layer having a plurality of second grooves formed to extend in a horizontal direction and at least one through hole penetrating the second dielectric layer; wherein the plurality of pads of each bare die are exposed to the outside by the plurality of second grooves; wherein each antenna is exposed to the outside by each through hole; At least one conductive pillar, each conductive pillar being formed in each through hole, and each conductive pillar being electrically connected to each antenna; A plurality of first connection lines, each first connection line being composed of metal paste filled in the plurality of second grooves, and each first connection line being electrically connected to the plurality of pads of each bare die respectively; A third dielectric layer provided on the second dielectric layer, the third dielectric layer having a plurality of third grooves formed to extend in a horizontal direction, and each third groove communicating with each second groove; A plurality of second connection lines, each second connection line being composed of metal paste filled in the plurality of third grooves, and each second connection line being electrically connected to each first connection line and electrically connected to each conductive pillar; and An outer protective layer provided on the third dielectric layer, the outer protective layer having a plurality of openings and at least one of the openings being located around the chip area on the second surface of the bare die; Wherein each second connection line is exposed to the outside by the plurality of openings to form a solder pad in each opening; Wherein each bare die is electrically connected to each antenna sequentially through each first connection line and each conductive pillar; Wherein the bare die can be electrically connected to the outside sequentially through the pad, the first connection line, the second connection line, and the solder pad located around the chip area on the second surface of the bare die, thereby forming the fan-out wafer-level packaging unit.
2. The fan-out wafer-level packaging unit according to claim 1, wherein The carrier board includes a silicon carrier board, a glass carrier board, or a ceramic carrier board.
3. The fan-out wafer-level packaging unit according to claim 1, wherein The metal paste constituting each first connection line includes silver paste, nano silver paste, copper paste, or nano copper paste.
4. The fan-out type wafer-level packaging unit according to claim 1, wherein The metal paste constituting each second connection line includes silver paste, nano silver paste, copper paste, or nano copper paste.
5. The fan-out wafer-level packaging unit according to claim 1, wherein, The first surface of each bare die is disposed on the first dielectric layer and each antenna by using a chip bonding film.
6. The fan-out wafer-level packaging unit as described in claim 1, wherein, A solder ball is further provided on each opening, and each solder ball can be electrically connected to the plurality of solder pads in each opening.
7. The fan-out type wafer-level packaging unit according to claim 6, wherein The fan-out wafer-level packaging unit can be electrically connected and disposed on a printed circuit board by using each solder ball.