Memory element and semiconductor device

Abstract

The utility model provides a memory element and a semiconductor device. In one example, a memory element includes a capacitor and transistors stacked in a compact configuration over the capacitor. The capacitor includes a floating gate, a high-k dielectric layer and a metal gate. The metal gate extends horizontally from the first sidewall to the second sidewall and vertically from the bottom surface to the top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions disposed on the two sidewalls of the metal gate, respectively, and a top portion disposed on the top surface of the metal gate. The transistor also includes two independent S / D regions formed on both side portions of the gate dielectric layer, respectively, and a channel region formed on top of the gate dielectric layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and more particularly to memory devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to many generations of ICs, with each successive generation of circuits being smaller and more complex than the previous one. During the development of ICs, the functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while the geometric dimensions (i.e., the size and / or dimensions and / or pitch between these IC features) have decreased. This process of shrinking the size typically provides advantages such as increased production efficiency and reduced associated costs. However, shrinking the size also increases the complexity of integrated circuit processing and manufacturing. Other methods have been considered to overcome the complexity of manufacturing ICs and to overcome physical limitations. Summary of the Utility Model

[0003] According to some aspects of the present disclosure, a memory element is provided. In one example, the memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The high-k dielectric layer is in contact with the floating gate, and the metal gate is in contact with the high-k dielectric layer. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on a top surface of the metal gate. The transistor further includes two independent source / drain regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on a top portion of the gate dielectric layer. The transistor further includes two independent source / drain electrodes respectively disposed on the two source / drain regions.

[0004] According to some aspects of the present disclosure, a semiconductor device is provided. In one example, the semiconductor device includes a substrate, an interconnect structure disposed on the substrate, a memory element, and a logic device disposed above the logic device. The logic device is disposed on the interconnect structure and electrically connected to the interconnect structure. The memory element and the logic device at least partially overlap in a vertical direction. The memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The metal gate horizontally extends from a first sidewall to a second sidewall and vertically extends from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on a top surface of the metal gate. The transistor further includes two independent source / drain regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on the top portion of the gate dielectric layer. The transistor further includes two independent source / drain electrodes respectively disposed on the two source / drain regions.

[0005] According to some aspects of the present disclosure, a semiconductor device is provided. In one example, the semiconductor device includes a substrate, an interconnect structure disposed on the substrate, a memory element disposed above the logic device, the logic device, and a contact plug portion. The logic device is disposed on the interconnect structure and electrically connected to the interconnect structure. The contact plug portion is disposed above the memory element and electrically connected to the memory element. The memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The metal gate horizontally extends from a first sidewall to a second sidewall and vertically extends from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on a top surface of the metal gate. The transistor further includes two independent source / drain regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on the top portion of the gate dielectric layer. The transistor further includes two independent source / drain electrodes respectively disposed on the two source / drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features may not be drawn to scale. In fact, for the sake of discussion clarity, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-sectional schematic diagram of an exemplary memory device is shown according to some embodiments;

[0008] Figure 1B A circuit diagram of a one-transistor-one-capacitor (1T1C) memory element shown according to some embodiments; Figure 1A

[0009] Figure 2 A flowchart of an exemplary method for manufacturing a memory device shown according to some embodiments; Figure 1A

[0010] Figures 3A to 3H A cross-sectional schematic diagram of an intermediate stage of a memory device being formed shown according to some embodiments; Figure 1A

[0011] Figure 4 A cross-sectional schematic diagram of another example memory device shown according to some embodiments;

[0012] Figure 5 A flowchart of an exemplary method for manufacturing a memory device shown according to some embodiments; Figure 4

[0013] Figures 6A to 6H A cross-sectional schematic diagram of an intermediate stage of a memory device being formed shown according to some embodiments; Figure 4

[0014] Figure 7 A cross-sectional schematic diagram of another example memory device shown according to some embodiments;

[0015] Figure 8 A flowchart of an exemplary method for manufacturing a memory device shown according to some embodiments; Figure 7

[0016] Figures 9A to 9H A cross-sectional schematic diagram of an intermediate stage of a memory device being formed shown according to some embodiments; Figure 7

[0017] Figure 10 A cross-sectional schematic diagram of another example memory device shown according to some embodiments;

[0018] Figure 11 A flowchart of an exemplary method for manufacturing a memory device shown according to some embodiments; Figure 10

[0019] Figures 12A to 12H A cross-sectional schematic diagram of an intermediate stage of a memory device being formed shown according to some embodiments; Figure 10

[0020] Figure 13Schematic cross-sectional views of exemplary stacked structures are shown in accordance with some embodiments;

[0021] Figure 14 A flowchart of an exemplary method for manufacturing a stacked structure is shown in accordance with some embodiments; Figure 13 in accordance with some embodiments;

[0022] Figures 15A to 15Q Schematic cross-sectional views of various stages of manufacturing a stacked structure are shown in accordance with some embodiments;

[0023] Figures 16A to 16D Variation schematic cross-sectional views of a stacked structure are shown in accordance with some embodiments; Figure 13 in accordance with some embodiments;

[0024] Figure 17 Schematic cross-sectional views of another example of a stacked structure are shown in accordance with some embodiments;

[0025] Figure 18 A flowchart of an exemplary method for manufacturing a stacked structure is shown in accordance with some embodiments; Figure 17 in accordance with some embodiments;

[0026] Figures 19A to 19E Schematic cross-sectional views of various stages of manufacturing a stacked structure are shown in accordance with some embodiments.

[0027]

Symbol Description

[0028] 100, 400: Memory device

[0029] 101, 401: Substrate

[0030] 102, 402: 1T1C memory element

[0031] 103, 403: Transistor

[0032] 104, 404: Capacitor

[0033] 106, 406: Gate structure

[0034] 111, 411: Metal gate

[0035] 112, 412: Gate dielectric layer

[0036] 113, 413: Semiconductor layer

[0037] 114, 114a, 114b, 414, 414a, 414b: S / D region 115, 415: Channel region

[0038] 116: Top surface

[0039] 117, 118: Sidewall

[0040] 119, 119a, 119b, 419, 419a, 419b: S / D electrode 120, 420: Dielectric layer

[0041] 121, 421: High-k dielectric layer

[0042] 122, 422: Floating gate

[0043] 123: Bottom surface

[0044] 125, 125a, 125b, 425, 425a, 425b: Via contact 130, 430: Dielectric layer

[0045] 140, 440: Dielectric layer

[0046] 200: Method

[0047] 202, 204, 206, 208, 210, 212, 214, 216: Steps 302: Dielectric layer

[0048] 304a, 304b: Openings

[0049] 500: Method

[0050] 502, 504, 506, 508, 510, 512, 514, 516: Steps 604, 606: First opening

[0051] 608: Second opening

[0052] 610: Bottom surface

[0053] 612, 614: Sidewalls

[0054] 615: Third opening

[0055] 700, 1000: Memory device

[0056] 701, 1001: Substrate

[0057] 702, 1002: Memory element

[0058] 703, 1003: Transistor

[0059] 704, 1004: Capacitor

[0060] 706, 1006: Gate structure

[0061] 711, 1011: Metal gate

[0062] 712, 1012: Gate dielectric layer

[0063] 713, 1013: Semiconductor layer

[0064] 714, 714a, 714b, 1014, 1014a, 1014b: S / D region 715, 1015: Channel region

[0065] 716, 1016: Top surface

[0066] 717, 718, 1017, 1018: Side walls 719, 719a, 719b, 1019, 1019a, 1019b: S / D electrodes 720, 1020: Dielectric layer

[0067] 721, 1021: High-k dielectric layer

[0068] 722, 1022: Floating gate

[0069] 723, 1023: Bottom surface

[0070] 724, 1024: Top surface

[0071] 725, 725a, 725b, 1025, 1025a, 1025b: Via contact 727, 728: Side walls

[0072] 730, 1030: Dielectric layer

[0073] 731a, 731b, 1031a, 1031b: Bottom surface

[0074] 732a, 732b, 1032a, 1032b: Top surface

[0075] 733a, 733b, 1033a, 1033b: Proximal side walls

[0076] 734a, 734b, 1034a, 1034b: Distal side walls

[0077] 740, 1040: Dielectric layer

[0078] 800: Method

[0079] 802, 804, 806, 808, 810, 812, 814, 816: Steps 902: Dielectric layer

[0080] 903: Top surface

[0081] 904, 906: Openings

[0082] 912a, 912b: Bottom surface

[0083] 914a, 914b, 916, 916a, 916b: Side

[0084] 1041: Top surface

[0085] 1100: Method

[0086] 1102,1104,1106,1108,1110,1112,1114,1116: Step 1202: Opening

[0087] 1300: Semiconductor stack structure / Stack structure

[0088] 1301: Carrier substrate

[0089] 1302: Memory element

[0090] 1303: Semiconductor device

[0091] 1304: Interconnection structure

[0092] 1305: Additional metallization layer

[0093] 1306: Transistor portion

[0094] 1307: Transistor

[0095] 1308: Power rail portion

[0096] 1310: Memory element portion

[0097] 1312: Contact plug portion

[0098] 1314: TOV

[0099] 1320: Bonding structure

[0100] 1321: Metal wire

[0101] 1322: Via contact

[0102] 1325: Power rail

[0103] 1326: Metal via

[0104] 1327: Power rail

[0105] 1381: Substrate

[0106] 1382: Metallization layer

[0107] 1400: Method

[0108] 1402,1404,1406,1408,1410,1412,1414,1416,1418,1420: Step 1502: Substrate

[0109] 1507: Sacrificial structure

[0110] 1509: Gap

[0111] 1510: Nanostructured channel

[0112] 1521, 1522: Nanostructured layer

[0113] 1523: SiN layer

[0114] 1528: Sidewall spacer

[0115] 1530: Dielectric layer / ILD layer

[0116] 1555: Superlattice

[0117] 1557: GAA channel region

[0118] 1558: GAA structure

[0119] 1560: Interface layer

[0120] 1561: Gate dielectric layer

[0121] 1562: Work function metal layer

[0122] 1563: Gate electrode

[0123] 1564: Inner spacer

[0124] 1570: S / D region

[0125] 1571: Metal wire

[0126] 1574: Gate contact

[0127] 1580: Insulating layer

[0128] 1583: Gate terminal / gate structure

[0129] 1586: Interface

[0130] 1589: Backside S / D contact

[0131] 1600A, 1600B, 1600C, 1600D: Stacked structure

[0132] 1700: Stacked structure

[0133] 1704: MIM capacitor

[0134] 1704a, 1704b: Electrode

[0135] 1704c: Layer

[0136] 1710: Sealing ring structure

[0137] 1800: Method

[0138] 1802, 1804, 1806, 1808, 1810, 1812: Step 1902: First sealing ring part

[0139] 1904: Second sealing ring part

[0140] 1906: Third sealing ring part

[0141] 1908: Fourth sealing ring part

[0142] B: Back side

[0143] F: Front side

[0144] H1, H2: Height

[0145] L1, L2: Length

[0146] t: Distance

[0147] X: Direction

[0148] Y: Direction

[0149] Z: Direction Detailed implementation manners

[0150] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, forming the first feature on or above the second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features are formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself prescribe the relationship between the various embodiments and / or configurations discussed.

[0151] Furthermore, for ease of description, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship between an element or feature and one or more other elements or features. As shown in the drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0152] Additionally, the source / drain regions may refer to the source or the drain individually or collectively depending on the context. For example, a device may include a first source / drain region and a second source / drain region, as well as other components. The first source / drain region may be the source region, and the second source / drain region may be the drain region, or vice versa. Those of ordinary skill in the art will understand various variations, modifications, and alternatives.

[0153] To facilitate the description, terms such as "about", "approximately", "substantially", "essentially", etc. may be used herein. Those of ordinary skill in the art will understand and derive the meanings of these terms. For example, "about" may represent a variation of 20%, 10%, 5%, etc. in size, but other values may be used when appropriate. Larger features, such as the longest dimension of a semiconductor fin, may have a variation of less than 5%, while very small features, such as the thickness of an interlayer, may have a variation of up to 50%, and both types of variations can be represented by "about". "Substantially" is generally more restrictive than "about" and may be suitable for representing a variation of 10%, 5%, or less, but is not limited thereto. A feature that is "substantially planar" may have a variation of 10% or less compared to a straight line. A material having a "substantially constant concentration" may have a concentration variation within a range of 5% or less along one or more dimensions. Similarly, those of ordinary skill in the art will be able to understand and derive the appropriate meanings of these terms based on industry knowledge, current manufacturing techniques, etc.

[0154] The structures disclosed herein can be patterned by various methods. For example, one or more photolithography processes (including double patterning or multi-patterning processes) can be used to pattern fin structures. Double patterning or multi-patterning processes can combine photolithography and self-alignment processes, thereby allowing the creation of smaller pitches, such as having a pitch smaller than that obtained using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is removed, and the remaining spacers can be used to pattern the fin structure.

[0155] The various layers or components of the device, memory element, and structure suitable for forming the present disclosure, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure CVD (LP-CVD), plasma enhanced CVD (PE-CVD), high density plasma CVD (HDP-CVD), metallorganic CVD (MO-CVD), remote plasma CVD (RP-CVD), atomic layer CVD (AL-CVD), atmospheric pressure CVD (AP-CVD), and / or other suitable techniques.

[0156] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or removed. Some of the features described below may be replaced or removed, and additional features may be added for different embodiments. Although some embodiments perform operations in a specific order during discussion, these operations can be performed in another logical order.

[0157] Overview.

[0158] One or more embodiments of the present disclosure improve the size limitations of integrated circuits (ICs), which can lead to low device density. For example, due to physical limitations, it has become increasingly challenging to reduce the size of components such as transistors or memory elements to increase the integration density. The present disclosure provides novel memory elements with capacitors of transistors having a stacked configuration. The present disclosure also provides novel integrated structures of memory elements with a stacked configuration and logic devices. The novel memory elements and integrated structures can increase the body density.

[0159] An insight provided in this disclosure relates to a novel one-transistor-one-capacitor (1T1C) memory element having a stacked and compact configuration. According to some embodiments, the 1T1C memory element has a three-dimensional (3D) structure having a capacitor enclosed by a transistor portion. The capacitor is a metal-dielectric-metal (MDM) type capacitor. The transistor includes a gate electrode (i.e., the transistor gate electrode), which can be used as a metal electrode of the capacitor. Compared with transistors and capacitors in traditional 1T1C memory elements being isolated from each other or formed in different layers of a memory device, the 1T1C memory element of this disclosure stacks the transistor and the capacitor in a vertical or horizontal direction, and the capacitor is partially enclosed by the transistor, thus forming a more compact or compressed configuration. The memory element according to this disclosure can generally be used in non-volatile memories such as resistive random access memory (RRAM) devices, dynamic random access memory (DRAM) devices, magneto-resistive random access memory (MRAM) devices, ferroelectric random access memory (FeRAM) devices, etc.

[0160] Another insight provided in this disclosure relates to a stacked device structure in which memory elements are stacked on and overlap the back surface of a logic device to increase density. Traditionally, methods for increasing density have mainly targeted configuring memory elements (e.g., DRAM, RRAM, etc.) and logic devices (e.g., integrated circuits) on the front surface of a substrate. That is, the logic device and the memory element are configured side by side on the same plane (i.e., the front side of the substrate). To further increase the density on the front surface, reducing the size of the elements is a key factor.

[0161] Herein, the stacked device structure according to the present disclosure increases the density of components by arranging memory elements and logic devices in an overlapped relationship to further reduce the footprint of the IC. For example, an original substrate can be used to form logic devices (e.g., gate-all-around (GAA) devices). FEOL (front-end-of-line) and MEOL (mid-end-of-line) processes can be performed to form semiconductor devices. After these processes are completed, the front side of the semiconductor device can be bonded to the front side of a carrier wafer face-to-face to form a stacked structure. Next, the stacked structure can be flipped, and the back side of the original substrate can be thinned, leaving only a portion of the silicon or other semiconductor material of the thinned original substrate. On the back side, contact patterning and formation of contact plugs can be performed. Then, the flipped wafer serves as a substrate for forming additional devices on the back side of the original substrate, such as power rails, memory elements (e.g., memory elements having a compact structure currently), and electric routings. Thereafter, through oxide vias (TOVs) can be used to connect the back-side memory elements to the power rails or the front-side logic devices. The additional components and devices formed on the back side of the logic device are at least partially aligned and overlapped in the vertical direction, thereby increasing the overall integration density of the stacked structure.

[0162] An example memory device with a compact 1T1C memory element.

[0163] Figure 1AA cross-sectional schematic diagram of an exemplary memory device 100 is shown according to some embodiments. In the example shown, the memory device 100 includes, among other components, a substrate 101, one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer), and a 1T1C memory element 102. For example, the one or more dielectric layers may include a first interlayer dielectric (ILD) layer 120, a second ILD layer 130, a third ILD layer 140, and so on. The 1T1C memory element 102 has a stacked structure and includes a transistor 103 and a capacitor 104 stacked in a vertical direction (i.e., the Z direction). The transistor 103 is regarded as an access device, and the capacitor 104 is regarded as a memory device. The 1T1C memory element 102 may be formed in a dielectric layer (e.g., ILD layer 120) of the memory device 100. Compared with a conventional 1T1C memory element in which a transistor and a capacitor are disposed in two separate or isolated dielectric layers from each other, the 1T1C memory element 102 according to the present disclosure has a more compact structure, which can improve the overall integration density of the memory device 100.

[0164] The substrate 101 may include an elemental (single-element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP; and / or other suitable materials. The substrate 101 may be a single-layer material with a uniform composition. Alternatively, the substrate 101 may include multiple material layers with similar or different compositions suitable for manufacturing IC devices. In one example, the substrate 101 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 101 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof.

[0165] The dielectric layers 120 / 130 / 140 or any other dielectric layers described herein may include dielectric materials such as tetraethyl orthosilicate (TEOS), low-k dielectric materials, doped silicon oxides (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), etc.) and / or other suitable dielectric materials. The dielectric layers 120 / 130 / 140 may each further include a multi-layer structure having multiple dielectric materials. The dielectric layers 120 / 130 / 140 may be formed by deposition processes such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), and / or other suitable methods.

[0166] The transistor 103 may be a planar field-effect transistor (FET), a thin-film FET, a three-dimensional (3D) FET, a fin field-effect transistor (FinFET), a gate-all-around (GAA) FET, or some other suitable type of semiconductor device. In the illustrated example, the transistor 103 is a 3D FET and includes, among other components, a gate structure 106, two source / drain (S / D) regions 114a and 114b (collectively 114), a channel region 115, two S / D electrodes 119a and 119b (collectively 119). The transistor 103 may also include two via contacts 125a and 125b (collectively 125). The gate structure 106 also includes a metal gate 111 and a gate dielectric layer 112. The capacitor 104 has a planar metal-dielectric-metal (MDM) structure and includes a floating gate 122, a high-k dielectric layer 121, and the metal gate 111. As Figure 1A shown, the transistor 103 and the capacitor 104 share the metal gate 111 and are electrically coupled to each other through the metal gate 111.

[0167] The gate dielectric layer 112 of the gate structure 106 may include dielectric materials such as, but not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) Hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), zirconium silicate, zirconium aluminate, zirconia, titania, aluminum oxide (Al2O3), hafnium dioxide - aluminum oxide (HfO2 - Al2O3) alloy, or a combination thereof. Other dielectric materials suitable for forming the gate dielectric layer 112 are also within the scope of this disclosure.

[0168] The high - k dielectric layer 121 of the capacitor 104 may include a high - k dielectric material. A high - k dielectric material can be defined as a dielectric material having a dielectric constant greater than that of SiO2. In some embodiments, the high - k dielectric layer 121 includes hafnium, oxygen, lanthanum, aluminum, titanium, zirconium, tantalum, silicon, other suitable materials, or a combination thereof. In some embodiments, the high - k dielectric layer 121 is selected from a material in the group consisting of carbon - doped oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In various embodiments, the high - k dielectric layer 121 includes oxides or nitrides of the elements listed above. In an exemplary embodiment, the high - k dielectric layer 121 includes hafnium oxide, such as HfO2.

[0169] In some embodiments, the gate dielectric layer 112 and the high - k dielectric layer 121 can be formed by, for example but not limited to, sputtering, CVD, PVD, ALD, plasma - enhanced ALD, molecular beam epitaxy (MBE), a combination thereof, or other suitable techniques. In some embodiments, the gate dielectric layer 112 and the high - k dielectric layer 121 can each include one or more layers and are each made of one or more of the above - mentioned dielectric materials.

[0170] In Figure 1AIn the capacitor 104 shown, a floating gate 122 is disposed in an IDL layer 120, and a high-k dielectric layer 121 is disposed on and in physical contact with the floating gate 122. A metal gate 111 of a gate structure 106 is disposed on and in physical contact with the high-k dielectric layer 121. In some embodiments, the metal gate 111 may have a 3D configuration, vertically extending from a bottom surface 123 to a top surface 116 and horizontally extending from a first sidewall 117 to a second sidewall 118. The bottom surface 123 of the metal gate 111 is coplanar with the bottom surface of the high-k dielectric layer 121, and the length of the metal gate 111 (i.e., the horizontal dimension in the X direction) is greater than the length of the high-k dielectric layer 121 such that a portion of the high-k dielectric layer 121 surrounds the bottom of the metal gate 111. A gate dielectric layer 112 of the gate structure 106 has two sides, two edge portions, and a top, the two sides are respectively disposed on two sidewalls 117 and 118 of the metal gate 111, the two edge portions are respectively disposed on the top surface 116 near the sidewalls 117 and 118, and the top is disposed on a majority of the center of the top surface 116.

[0171] In some embodiments, the capacitor 104 has a planar shape or configuration. For example, the high-k dielectric layer 121 has a length (L1) defined by a horizontal dimension in the X direction and a height (H1) defined by a vertical dimension in the Z direction. L1 is much greater than H1. In other words, the aspect ratio (H1 / L1) of the high-k dielectric layer 121 is substantially less than 1. The metal gate 111 has a length (L2) defined by a horizontal dimension in the X direction and a height (H2) defined by a vertical dimension in the Z direction. L2 may be equal to, greater than, or less than H2. In other words, the metal gate 111 has an aspect ratio (H2 / L2) equal to, greater than, or less than 1. Comparing the high-k dielectric layer 121 and the metal gate 111, L2 is greater than L1. In some embodiments, H2 is significantly greater than H1.

[0172] The floating gate 122 may include: a conductive material such as polysilicon, silicon nitride (SiN), a metal such as aluminum (Al) or tungsten (W), or a conductive polymer such as poly(3-hexylthiophene) (P3HT) or poly(ethylene dioxythiophene) (PEDOT). The metal gate 111 may include a work function metal such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or a combination thereof. The work function metal may include multiple layers and may be deposited by ALD, CVD, PVD, other suitable processes, or a combination thereof. In some embodiments, the metal gate 111 includes TiN.

[0173] In some embodiments, the transistor 103 further includes a semiconductor layer 113 disposed on the gate dielectric layer 112. Two S / D regions 114a and 114b and a channel region 115 may be formed in the semiconductor layer 113. For example, the two S / D regions 114a and 114b are respectively formed on both sides and / or edge portions of the semiconductor layer 113 located at or near two sidewalls 117 and 118 of the metal gate 111, and the channel region 115 is formed on the top of the semiconductor layer 113 located above and near the top surface 116 of the metal gate 111. The semiconductor layer 113 may include an oxide semiconductor material such as, but not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide (InSnO), tungsten-doped indium oxide (InWO) x ) gallium oxide (GaO x ), indium oxide (InO

[0174] In some embodiments, as described above, the semiconductor layer 113 is an IGZO layer formed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). IGZO is an amorphous semiconductor material with an electron mobility 20 - 50 times that of amorphous silicon. IGZO can be deposited as a uniform amorphous phase while maintaining a high carrier mobility. IGZO can be formed at relatively low temperatures and can be used for junctionless transistor operation and avoid charge trapping that occurs in inversion mode operation. Additionally, the ability to deposit IGZO at relatively low temperatures represents a particular advantage. IGZO can also be deposited on sidewalls or conformally deposited on any desired structure with an exact thickness, enabling the fabrication of 3D transistors with any desired geometry. Further, the deposition of IGZO can be compatible with the deposition of many materials such as the gate dielectric layer 112.

[0175] The ratio of gallium to indium in the IGZO layer can be 1:1, the ratio of gallium to indium greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or the ratio of gallium to indium less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). The relative contents of gallium, indium, zinc, and oxygen can vary according to design requirements.

[0176] A synthesis method can be used to fabricate the IGZO layer, such as a low-temperature ALD process, e.g., at 250 °C or below 250 °C. Alternatively, a solution process can be used to fabricate the IGZO layer, such as pulsed laser deposition (PLD) or spin coating, including depositing an In and Ga solution layer onto a hot plate and annealing at a temperature between approximately 200 °C and 400 °C, depending on the target composition. Subsequently, the thin film can be annealed in air. However, in alternative embodiments, other suitable methods can also be used to form the IGZO layer. The thickness of the IGZO layer can be from about 0.1 nanometer (nm) to about 500 nm, from about 0.5 to about 50 nm, or from about 1 nm to about 10 nm.

[0177] In some embodiments, the S / D regions 114 may be formed in the IGZO layer (i.e., the semiconductor layer 113) by doping the corresponding sides and / or edge portions of the semiconductor layer 113 with ionic impurities using a technique such as ion implantation to form the S / D regions 114. Alternatively, the S / D regions 114 may be formed by adjusting the ratios of In, Ga, Zn, and O in the corresponding sides and / or edge portions of the semiconductor layer 113. Or, the S / D regions 114 may be formed by annealing the IGZO layer at a selective temperature after the IGZO layer is formed.

[0178] In some embodiments, a source / drain (S / D) layer (not shown) is disposed on the gate dielectric layer 112 and separated from the semiconductor layer 113. After the S / D regions 114 are formed in the S / D layer, the semiconductor layer 113 is disposed on the S / D layer. The S / D regions 114a and 114b may be formed at two sidewalls 117 and 118 of the metal gate 111 respectively, or in the corresponding portions of the nearby S / D layer. The top portion of the S / D layer between the S / D regions 114a and 114b may be removed to form a gap that separates and isolates the two S / D regions 114a and 114b. A portion of the semiconductor layer 113 deposited on the S / D layer may fill the gap and form a channel region 115 that connects the S / D region 114a and the S / D region 114b. The S / D layer may include a semiconductor material such as germanium (Ge) or silicon germanium (SiGe), a metal silicide such as titanium silicide, tungsten silicide, or cobalt silicide, or doped polysilicon. The S / D regions 114 may be formed by doping the corresponding portions of the S / D layer with impurities using a doping technique such as ion implantation.

[0179] Two S / D electrodes 119a and 119b are respectively disposed on the two S / D regions 114a and 114b. The S / D electrode 119 may include a conductive material similar to the metal gate 111, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or a combination thereof. In some embodiments, the S / D electrode 119 includes TiN.

[0180] The memory device 100 may also include two via contacts 125a and 125b (collectively referred to as via contacts 125), which are respectively disposed on two S / D electrodes 119a and 119b and coupled to the two S / D electrodes 119a and 119b. The two via contacts 125a and 125b include a conductive material, and the two via contacts 125a and 125b are configured to electrically connect the two S / D electrodes 119a and 119b to another feature or component in the memory device 100.

[0181] Figure 1B Shown according to some embodiments Figure 1A The circuit diagram of a one-transistor-one-capacitor (1T1C) memory element 102. In the example shown, the 1T1C memory element 102 includes a transistor 103 coupled to a capacitor 104. The drain region 114a / 114b coupled to the transistor 103 via a bit line (BL), the source line (SL) coupled to the source region 114a / 114b, and the word line (WL) coupled to the floating gate 122 of the capacitor 104, such that the 1T1C memory element 102 is electrically addressable. As described above, the capacitor 104 is located between the WL and the transistor 103 and coupled to the gate structure 106 of the transistor 103, such that the capacitor 104 and the transistor 103 share a metal gate 111. Thus, the capacitor 104 of the 1T1C memory element 102 is sometimes also referred to as a "WL capacitor". According to some embodiments, multiple 1T1C memory elements 102 may be arranged in rows and columns to form a memory array. Figure 1B The circuit diagram shown may also represent 1T1C memory element 402 ( Figure 4 shown), 1T1C memory element 702 ( Figure 7 shown), and 1T1C memory element 1002 (shown in FIG. 10), which are Figure 1A variations of the 1T1C memory element 102.

[0182] It is worth noting that Figure 1BThe illustrated 1T1C memory element 102 is for illustrative purposes only, and memory elements having multiple transistors and / or multiple capacitors with a stacked and compact structure are also within the scope of the present disclosure. For example, in a manner similar to the 1T1C memory element 102, a 2T2C memory element may have two transistors adjacent to and coupled to each other in a horizontal direction and two capacitors respectively surrounded in the two transistors. Other examples of memory elements having the same or similar compact structure as the memory element 102 (e.g., 1T2C, 2T1C, 4T4C, 8T8C) are also within the scope of the present disclosure.

[0183] Figure 2 A flowchart of an exemplary method 200 for manufacturing Figure 1A the memory device 100 is shown according to some embodiments. The method 200 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after the method 200, and some of the described operations may be replaced, removed, or moved for additional embodiments of this method. The method 200 will be described below in conjunction with Figures 3A to 3H to describe the method 200, Figures 3A to 3H showing a part of the memory device 100 during an intermediate step of the method 200. Figures 3A to 3H A cross-sectional schematic diagram showing an intermediate stage of forming the memory device 100 is shown according to some embodiments.

[0184] At step 202, referring to Figure 3A , a partially formed memory device 100 is provided and received. The illustrated partially formed memory device 100 can be manufactured using any of a variety of processes used in semiconductor manufacturing. The partially formed memory device 100 includes a dielectric layer 120 and a capacitor 104. The capacitor includes a floating gate 122 (i.e., a bottom floating gate) disposed in the dielectric layer 120, a high-k dielectric layer 121 disposed on the floating gate 122, and a metal gate 111 disposed on the high-k dielectric layer 121.

[0185] At step 204, referring to Figure 3B , a gate dielectric layer 112 is formed on the metal gate 111. In some embodiments, the gate dielectric layer 112 is deposited using ALD. The gate dielectric layer 112 is disposed on the top surface 116 of the metal gate 111 and on two sidewalls 117 and 118. The gate dielectric layer 112 and the metal gate 111 form a gate structure 106.

[0186] At step 206, referring to Figure 3C, two S / D regions 114a and 114b and a channel region 115 are formed. In some embodiments, the semiconductor layer 113 is formed and deposited on the gate dielectric layer 112. Then, the two S / D regions 114a and 114b are respectively formed in the two side portions of the semiconductor layer 113. The two S / D regions 114a and 114b are respectively located near the first sidewall 117 and the second sidewall 118 of the metal gate 111. The channel region 115 is formed in the top of the semiconductor layer 113.

[0187] In some embodiments, an S / D layer (not shown) is formed and deposited on the gate dielectric layer 112. The two S / D regions 114a and 114b are respectively formed in the two side portions and / or edge portions of the S / D layer. The top of the S / D layer is removed to form a gap between the two S / D regions 114. This gap separates and isolates the two S / D regions 114a and 114b from each other. Then, the semiconductor layer 113 is formed and deposited on the S / D layer and fills the gap between the two S / D regions 114. In some embodiments, the semiconductor layer 113 is an IGZO layer deposited using ALD.

[0188] At step 208, refer to Figure 3D , a dielectric layer 130 is formed. The dielectric layer 130 is deposited on the semiconductor layer 113 and covers the semiconductor layer 113. A planarization such as a chemical mechanical polish (CMP) process can be performed to planarize the top surface of the dielectric layer 130.

[0189] At step 210, refer to Figure 3E , two openings 304a and 304b are formed in the dielectric layer 130. The openings 304a and 304b can be formed by performing a patterning and etching process to remove a portion of the dielectric layer 130 and expose the corresponding S / D regions 114 of the semiconductor layer 113. The etching process can be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, a neutral beam etching (NBE) process, other suitable methods, or a combination thereof. For example, the dry etching process can use a chlorine-containing gas, a fluorine-containing gas, and / or other etching gases. The wet etching solution can include ammonium hydroxide (NH4OH), hydrofluoric acid (HF), or diluted HF, deionized water, tetramethylammonium hydroxide (TMAH), and / or other suitable wet etching solutions.

[0190] At step 212, refer to Figure 3F, two S / D electrodes 119 are respectively formed. The two S / D electrodes 119a and 119b can be formed by depositing a metal layer to fill the two openings 304a and 304b respectively. A CMP process can be performed to remove the excess metal layer and flatten the top surfaces of the two S / D electrodes 119a and 119b. In this way, the transistor 103 is formed above the capacitor 104. The transistor 103 is aligned with the capacitor 104 in the vertical direction, and the capacitor 104 and the transistor 103 share the metal gate 111, forming a stacked and compact structure of the 1T1C memory element 102.

[0191] At step 214, referring to Figure 3G , a dielectric layer 140 (i.e., the ILD layer 140) is formed. The dielectric layer 140 can be deposited on the two S / D electrodes 119a and 119b and the dielectric layer 302. A CMP process can be performed to flatten the top surface of the dielectric layer 140.

[0192] At step 216, referring to Figure 3H , two S / D via contacts 125a and 125b are formed. The via contacts 125a and 125b can be formed by the following steps: using a patterning and etching process to form two via openings (not shown), respectively exposing the top surfaces of the S / D electrodes 119a and 119b. Depositing a conductive layer to fill the two via openings. Performing a CMP process to remove the excess conductive layer. Flattening the top surfaces of the via contacts 125a and 125b.

[0193] Figure 4 A cross-sectional schematic diagram of another example memory device 400 is shown according to some embodiments. The memory device 400 is Figure 1A a variation of the memory device 100 shown. In the illustrated example, the memory device 400 includes, among other components, a substrate 401, one or more dielectric layers 420 / 430 / 440, and a 1T1C memory element 402. The memory device 400 may also include two via contacts 425a and 425b (collectively referred to as 425). Similar to the 1T1C memory element 102, the 1T1C memory element 402 also has a stacked structure and includes a transistor 403 and a capacitor 404 stacked in the vertical direction (i.e., the Z direction). The difference between the 1T1C memory element 402 and the 1T1C memory element 102 is that the capacitor 404 of the 1T1C memory element 402 is located above the transistor 403 in the 1T1C memory element 402, and the floating gate 422 is located at the top of the 1T1C memory element 402.

[0194] The components and aspects thereof of the memory device 400, such as the substrate 401, the dielectric layers 420 / 430 / 440, the transistor 403, the capacitor 404, and the via contact 425 are similar to the substrate 101, the dielectric layers 120 / 130 / 140, the transistor 103, the capacitor 104, and the via contact 125 of the memory device 100, respectively. Therefore, they will not be repeated unless otherwise specified.

[0195] In the example of the 1T1C memory element 402, the transistor 403 includes two S / D electrodes 419a and 419b (collectively referred to as 419), a semiconductor layer 413 disposed on the two S / D electrodes 419, a gate dielectric layer 412 disposed on the semiconductor layer 413, and a metal gate 411 disposed on the gate dielectric layer 412. The 1T1C memory element 402 may also include two S / D regions 414a and 414b (collectively referred to as 414) and a channel region 415. The two S / D regions 414 are respectively formed in both side portions and / or edge portions of the semiconductor layer 413, and the channel region 415 is formed in the bottom of the semiconductor layer 413. The metal gate 411 and the gate dielectric layer 412 form a gate structure 406. The capacitor 404 includes a metal gate 411, a high-k dielectric layer 421 disposed on the metal gate 411, and a floating gate 422 disposed on the high-k dielectric layer 421. In this arrangement, capacitor 404 is located above and vertically aligned with transistor 403 , and capacitor 404 and transistor 403 share a metal gate 411 .

[0196] Figure 5 According to some embodiments, a method for manufacturing Figure 4 4. A flowchart of an exemplary method 500 of a memory device 400 is provided below. Figures 6A to 6H To describe method 500, Figures 6A to 6H A portion of memory device 400 is shown during an intermediate step of method 500 . Figures 3A to 3H A cross-sectional diagram illustrating an intermediate stage in forming a memory device 400 according to some embodiments.

[0197] At step 502, reference Figure 6A , providing a partially formed memory device 400. The memory device 400 includes a first dielectric layer 420 and two independent via contacts 425a and 425b respectively formed in the top of the first dielectric layer 420. A second dielectric layer 430 (e.g., an oxide layer) is formed on the first dielectric layer 420 and the via contacts 425a and 425b.

[0198] At step 504, reference Figure 6B, two first openings 604 and 606 are respectively formed above the two via contacts 425a and 425b, such that the top surfaces of the via contacts 425a and 425b are respectively exposed to the first openings 604 and 606. The two independent first openings 604 and 606 can be formed by performing a patterning and etching process to remove corresponding portions of the second dielectric layer 430.

[0199] At step 506, referring to Figure 6C , two independent S / D electrodes 419a and 419b are respectively formed. The S / D electrodes 419a and 419b can be formed by depositing a conductive layer to fill the first openings 604 and 606, and then performing a CMP process to remove the excess conductive layer. The two independent S / D electrodes 419a and 419b are respectively coupled to the two via contacts 425a and 425b.

[0200] At step 508, referring to Figure 6D , a second opening 608 is formed. The second opening 608 can be formed by performing a patterning and etching process to respectively remove the inner portions of the two S / D electrodes 419a and 419b, and the main portion of the second dielectric layer 430 between the two S / D electrodes 419a and 419b. The second opening 608 can be characterized by the first sidewall 612 of the S / D electrode 419a, the second sidewall 614 of the S / D electrode 419b, and the bottom surface 610. The bottom surface 610 is located above the bottom surface of the second dielectric layer 430, such that the bottom surfaces of the respective S / D electrodes 419a / 419b remain connected to the corresponding via contacts 425a / 425b.

[0201] At step 510, referring to Figure 6E , two S / D regions 414a and 414b and a channel region 415 are formed. In some embodiments, a semiconductor layer 413 is formed and deposited in the second opening 608. The semiconductor layer 413 can be deposited using ALD, and the semiconductor layer 413 covers the sidewalls 612 and 614 and the bottom surface 610 in the second opening 608. The side portions and edge portions of the semiconductor layer 413 respectively adjacent to the sidewalls 612 and 614 can respectively form the S / D regions 414a and 414b. The bottom of the semiconductor layer 413 can form the channel region 415. In some embodiments, the semiconductor layer 413 is an IGZO layer formed using ALD.

[0202] In an alternative embodiment, an S / D layer (not shown) may be formed in the second opening 608 and cover the sidewalls 612 and 614 and the bottom surface 610 in the second opening 608. The S / D regions 414a and 414b may be formed respectively by processing the corresponding portions of the S / D layer disposed on the sidewalls 612 and 614. The bottom of the S / D layer may be removed to form a gap that separates and isolates the two S / D regions 414. Then, a semiconductor layer 413 is formed and deposited on the S / D layer, and the gap between the two isolated S / D regions 414 is filled. The portion of the semiconductor layer 413 that fills the gap between the two separate S / D regions 414 forms the channel region 415, and the channel region 415 is connected to the two S / D regions 414.

[0203] At step 512, referring to Figure 6F , the gate structure 406 is formed. The gate structure 406 may be formed by the following steps: depositing a gate dielectric layer 412 on the S / D regions 414 and the channel region 415 in the second opening 608, depositing a metal layer on the gate dielectric layer 412 and filling the second opening 608 to form a metal gate 411, and performing a CMP process to remove the excess metal layer and planarize the top surface of the metal gate 411. In some embodiments, the gate dielectric layer 412 and the metal gate 411 are deposited using ALD. In this way, the transistor 403 is formed.

[0204] At step 514, referring to Figure 6G , the third opening 615 is formed. The third opening 615 may be formed by performing a patterning and etching process to remove the top of the metal gate 411.

[0205] At step 516, referring to Figure 6H , the capacitor 404 is formed. In some embodiments, a high-k dielectric layer 421 is deposited on the metal gate 411 and fills the third opening 615, and then a CMP process is performed to remove the excess high-k dielectric layer 421. A third dielectric layer 440 is formed on the second dielectric layer 430 to cover the top surface of the high-k dielectric layer 421, and then a floating gate 422 (i.e., the top floating gate) is formed in the third dielectric layer 440. The floating gate 422 may be formed by the following steps: performing a patterning and etching process to remove a portion of the third dielectric layer 440 and expose the top surface of the high-k dielectric layer 421, depositing a conductive layer on the third dielectric layer 440 and filling the opening to form the floating gate 422, and performing a CMP process to remove the excess metal layer and planarize the top surface of the floating gate 422. In this way, the capacitor 404 is formed above the transistor 403 and is vertically aligned with the transistor 403, and the capacitor 404 and the transistor 403 share the metal gate 411, forming a stacked and compact structure of the 1T1C memory element 402.

[0206] Figure 7 A cross-sectional schematic diagram of another exemplary memory device 700 is shown in accordance with some embodiments. The memory device 700 is Figure 1A a variation of the memory device 100 shown. In the illustrated embodiment, the memory device 700 includes, among other components, a substrate 701, one or more dielectric layers 720 / 730 / 740, and 1T1C memory elements 702. The memory device 700 may also include two via contacts 725a and 725b (collectively 725). Figure 1A The difference between the memory device 100 and the memory device 700 is related to the size and configuration of the capacitor. Comparing capacitor 104 with capacitor 704, capacitor 104 (as Figure 1A shown) has a "planar" shape and profile, where the high-k dielectric layer 121 has a relatively large horizontal dimension and a relatively small vertical dimension, Figure 7 the capacitor 704 of the 1T1C memory element 702 shown has a "cup-shaped" shape and profile, where the high-k dielectric layer 721 has a relatively small horizontal dimension and a relatively large vertical dimension.

[0207] Similar to the 1T1C memory element 102, the 1T1C memory element 702 also has a compact structure and includes a transistor 703 and a capacitor 704 partially surrounding the transistor 703. The transistor 703 has a 3D structure and includes a gate structure 706, two S / D regions 714a and 714b (collectively 714), a channel region 715, and two S / D electrodes 719a and 719b (collectively 719). The gate structure 706 further includes a metal gate 711 and a gate dielectric layer 712. The capacitor 704 includes a metal gate 711, a floating gate 722, and a high-k dielectric layer 721 disposed between the metal gate 711 and the floating gate 722 and surrounded by the metal gate 711 and the floating gate 722. In this configuration, the transistor 703 and the capacitor 704 share the metal gate 711. In the X direction, the capacitor 704 is disposed between the two S / D electrodes 719a and 719b of the transistor 703, resulting in a more compact structure compared to a conventional 1T1C memory element. The floating gate 722 of the capacitor 704 is located at the bottom of the 1T1C memory element 702.

[0208] The floating gate 722 is formed in the first dielectric layer 720. The high-k dielectric layer 721 is disposed on the floating gate 722, vertically extending from the bottom surface 723 (i.e., the top surface of the floating gate 722) to the top surface 724, and horizontally extending from the first sidewall 727 to the second sidewall 728 in the X direction. The metal gate 711 is disposed on the high-k dielectric layer 721 and contacts the top surface 724 and the two sidewalls 727, 728 of the high-k dielectric layer 721. In the X direction, the metal gate 711 vertically extends from the bottom surface (i.e., aligned with the bottom surface 723 of the high-k dielectric layer 721) to the top surface 716 and horizontally extends from the first sidewall 717 to the second sidewall 718. The first sidewall 717 of the metal gate 711 is adjacent to the first sidewall 727 of the high-k dielectric layer 721, and the second sidewall 718 of the metal gate 711 is adjacent to the second sidewall 728 of the high-k dielectric layer 721. The top surface 716 of the metal gate 711 is located above the top surface 724 of the high-k dielectric layer 721 and is vertically aligned with the top surface 724 of the high-k dielectric layer 721.

[0209] In some embodiments, the capacitor 704 has a cup-shaped configuration. For example, the high-k dielectric layer 721 has a length (L1) and a height (H1), and the metal gate 711 has a length (L2) and a height (H2). L2 is greater than L1, and H2 is greater than H1. In some embodiments, H1 is significantly greater than L1, and H2 is significantly greater than L2. In other words, the high-k dielectric layer 721 has an aspect ratio (H1 / L1) substantially greater than 1, and the metal gate 711 has an aspect ratio (H2 / L2) substantially greater than 1.

[0210] Compared with Figure 1A the metal gate 111 of the memory device 100 shown, the metal gate 711 of the memory device 700 has a relatively smaller size (i.e., length) in the X direction, and the high-k dielectric layer 721 of the memory device 700 has a larger vertical size (i.e., height).

[0211] The gate dielectric layer 712 is disposed on the sidewalls 717 and 718 and the top surface 716 of the metal gate 711. In some embodiments, the semiconductor layer 713 is formed on the gate dielectric layer 712. Two S / D regions 714a and 714b are respectively formed in the two side portions and / or edge portions of the semiconductor layer 713 adjacent to the sidewalls 727 and 728 of the metal gate 711. The channel region 715 is formed on the top of the semiconductor layer 713, aligned and close to the top surface 716 of the metal gate 711.

[0212] In some embodiments, an S / D layer (not shown) is formed on the gate dielectric layer 712. Two S / D regions 714a and 714b are respectively formed in two side portions of the S / D layer adjacent to sidewalls 727 and 728 of the metal gate 711. The top of the S / D layer adjacent to the top surface 716 of the metal gate 711 can be removed to form a gap to separate and isolate the two S / D regions 714a and 714b. Then, a semiconductor layer 713 is formed, and the semiconductor layer 713 fills the gap at the top of the top surface 716 of the metal gate 711 and forms a channel region 715, and the channel region 715 is connected to the S / D regions 714a and 714b.

[0213] Two S / D electrodes 719a and 719b are respectively located at two sidewalls 727 and 728 of the metal gate 711 and are aligned in the X direction. The S / D electrode 719a is disposed on the S / D region 714a (i.e., the side of the semiconductor layer 713 adjacent to the sidewall 727 of the metal gate 711), and the S / D electrode 719b is disposed on the S / D region 714b (i.e., the side of the semiconductor layer 713 adjacent to the sidewall 728 of the metal gate 711). The S / D electrode 719a is substantially aligned with the metal gate 711, vertically extends from the bottom surface 731a to the top surface 732a, and horizontally extends from the proximal sidewall 733a (i.e., the sidewall 727 adjacent to the metal gate 711) to the distal sidewall 734a (i.e., the sidewall 727 away from the metal gate 711). Similarly, the S / D electrode 719b is substantially aligned with the metal gate 711, vertically extends from the bottom surface 731b to the top surface 732b, and horizontally extends from the proximal sidewall 733b (i.e., the sidewall 728 adjacent to the metal gate 711) to the distal sidewall 734b (i.e., the sidewall 728 away from the metal gate 711).

[0214] The semiconductor layer 713 may partially surround the S / D electrodes 719a. For example, the S / D region 714a covers the proximal sidewall 733a, and a portion of the semiconductor layer 713 covers the bottom surface 731a and the distal sidewall 734a. In some embodiments, a portion of the semiconductor layer 713 disposed beneath the bottom surface 731a and on the distal sidewall 734a may also serve as an extension of the S / D region 714a. Similarly, the semiconductor layer 713 can also partially surround the S / D electrode 719b. For example, the S / D region 714b covers the proximal sidewall 733b, and a portion of the semiconductor layer 713 covers the bottom surface 731b and the distal sidewall 734b. In some embodiments, a portion of the semiconductor layer 713 disposed beneath the bottom surface 731b and on the distal sidewall 734b may also serve as an extension of the S / D region 714b. The top surfaces 732a and 732b of the S / D electrodes 719a and 719b are coplanar with the top surface of the channel region 715 and are also aligned with the interface between the second dielectric layer 730 and the third dielectric layer 740. Two via contacts 725a and 725b are formed in the third dielectric layer 740 and are respectively coupled to the S / D electrodes 719a and 719b.

[0215] Figure 8 An exemplary method 800 for manufacturing Figure 7 is shown in a flowchart according to some embodiments. The method 800 will be described below in conjunction with Figures 9A to 9H which shows a portion of the memory device 700 during an intermediate step of the method 800. Figures 9A to 9H A cross-sectional schematic view of an intermediate stage of a memory device being formed is shown according to some embodiments. Figures 9A to 9H According to some embodiments, forming Figure 7 is shown in a cross-sectional schematic view of an intermediate stage of a memory device.

[0216] At step 802, referring to Figure 9A , a partially formed memory device 700 is provided and received. The partially formed memory device 700 includes a dielectric layer 720 and a capacitor 704. The capacitor 704 includes a floating gate 722 (i.e., bottom floating gate) disposed in the dielectric layer 720, a high-k dielectric layer 721 disposed on the floating gate 722, and a metal gate 711 disposed on the high-k dielectric layer 721. As described above, the metal gate 711 partially surrounds the high-k dielectric layer 721.

[0217] At step 804, referring to Figure 9B , a dielectric layer 902 containing a gate dielectric material is formed and deposited on the metal gate 711. The dielectric layer 902 is deposited on the top surface 716 of the metal gate 711 and on the two sidewalls 727 and 728. A CMP process may be performed to planarize the top surface of the dielectric layer 902.

[0218] At step 806, referring to Figure 9C , two openings 904 and 906 are respectively formed on both sides of the metal gate 711. The two openings 904 and 906 can be formed by performing a patterning and etching process to remove corresponding portions of the dielectric layer 902. The two openings 904 and 906 are substantially aligned with the metal gate 711 in the X direction. The opening 904 can be characterized by a bottom surface 912a, a proximal side 914a (i.e., the sidewall 717 close to the metal gate 711), and a distal side 916a (i.e., the sidewall 717 far from the metal gate 711). Similarly, the opening 906 can be characterized by a bottom surface 912b, a proximal side 914b (i.e., the sidewall 718 close to the metal gate 711), and a distal side 916b (i.e., the sidewall 718 far from the metal gate 711). The bottom surface 912a and the bottom surface 912b are higher than the top surface of the dielectric layer 720. The remaining portions of the dielectric layer 902 disposed between the sidewall 727 and the proximal side 914a, between the sidewall 728 and the proximal side 914b, and between the top surface 716 and the top surface 903 form the gate dielectric layer 712.

[0219] At step 808, referring to Figure 9D , two S / D regions 714a and 714b and a channel region 715 are formed. In some embodiments, a semiconductor layer 713 is formed in the openings 904 and 906 and above the gate dielectric layer 712. The semiconductor layer 713 is deposited on the top surface 903 of the dielectric layer 902, the two sides 914a / 916a and 914b / 916b, and the bottom surfaces 912a / 912b of the openings 904 / 906. The channel region 715 can be formed on the top of the semiconductor layer 913, where the top of the semiconductor layer 913 is above the top surface 903 and aligned with the metal gate 911. The portions of the semiconductor layer 713 disposed on the two sides 914a and 914b and the bottom surface 912a of the opening 904 are further processed to form the S / D region 714a. The portions of the semiconductor layer 713 disposed on the two sides 914a and 914b and the bottom surface 912b of the opening 904 are further processed to form the S / D region 714b.

[0220] In some embodiments, an S / D layer (not shown) is formed in openings 904 and 906 and above the gate dielectric layer 712. The S / D layer may be deposited on the top surface 903, the two sides 914a / 916a and 914b / 916b, and the bottom surfaces 912a / 912b of the dielectric layer 902. The portions of the S / D layer disposed on the two sides 914a and 914b and the bottom surface 912a of the opening 904 are further processed to form the S / D region 714a. The portions of the S / D layer disposed on the two sides 914a and 914b and the bottom surface 912b of the opening 904 are further processed to form the S / D region 714b. The top of the S / D layer located above the top surface 903 and aligned with the metal gate 911 may be removed to form a gap that separates and isolates the S / D regions 714a and 714b. A semiconductor layer 713 may be formed on the S / D layer and fill the gap between the S / D regions 714a and 714b. The portion of the semiconductor layer 713 filling the gap may form the channel region 715. In some embodiments, the semiconductor layer 713 is an IGZO layer deposited using ALD.

[0221] At step 810, referring to Figures 9E to 9F , two S / D electrodes 719a and 719b are formed. A metal layer 916 is deposited on the dielectric layer 902 and fills the openings 904 and 906 respectively. At step 812, a CMP process is performed to remove the excess metal layer 916 and form two S / D electrodes 719a and 719b respectively. The top surface of the channel region 715 (i.e., the top surface of the semiconductor layer 713) and the top surfaces of the two S / D electrodes 719a and 719b are coplanar. Thus, the transistor 703 is formed. The transistor 703 and the capacitor 704 form the 1T1C memory element 702.

[0222] At step 814, referring to Figure 9G , a patterning and etching process is performed to remove the portions of the dielectric layer 902 near the two S / D electrodes 719a and 719b.

[0223] At step 816, referring to Figure 9H , two via contacts 725a and 725b are formed. In some embodiments, a second dielectric layer 730 is formed on the first dielectric layer 720 and covers both sides of the transistor 703. A CMP process may be performed to planarize the top surface of the second dielectric layer 730. A third dielectric layer 740 may be formed above the second dielectric layer 730. Two via contacts 725a and 725b may be formed in the third dielectric layer 740 and coupled to the top surfaces of the S / D electrodes 719a and 719b respectively.

[0224] Figure 10A cross-sectional schematic diagram showing another example memory device according to some embodiments. The memory device 1000 is Figure 7 a variation of the memory device 700 shown. In the illustrated embodiment, the memory device 100 includes, among other components, a substrate 1001, one or more dielectric layers 1020 / 1030 / 1040, and 1T1C memory elements 1002. The memory device 1000 may also include two via contacts 1025a and 1025b (collectively 1025). Similar to the 1T1C memory element 702, the 1T1C memory element 1002 also has a stacked structure and includes a transistor 1003 and a capacitor 1004 partially surrounding the transistor 1003, and the capacitor 1004 is disposed between two S / D electrodes 1019a and 1019b of the transistor 1003 in the X direction. The difference between the 1T1C memory element 702 and the 1T1C memory element 1002 is that the floating gate 1022 is located on top of the 1T1C memory element 1002.

[0225] Each component of the memory device 1000 and its aspects, such as the substrate 1001, dielectric layers 1020 / 1030 / 1040, transistor 1003, capacitor 1004, and via contact 1025, are respectively similar to the substrate 701, dielectric layers 720 / 730 / 740, transistor 703, capacitor 704, and via contact 725 of the memory device 700. Therefore, they will not be repeated unless otherwise stated.

[0226] In an example of the 1T1C memory element 1002, the transistor 1003 includes two S / D electrodes 1019a and 1019b (collectively 1019), a semiconductor layer 1013 disposed on the two S / D electrodes 1019, a gate dielectric layer 1012 disposed on the semiconductor layer 1013, and a metal gate 1011 disposed on the gate dielectric layer 1012. The 1T1C memory element 1002 may also include two S / D regions 1014a and 1014b (collectively 1014) and a channel region 1015. The two S / D regions 1014 are respectively formed in the two side portions and / or edge portions of the semiconductor layer 1013, and the channel region 1015 is formed in the bottom of the semiconductor layer 1013. The metal gate 1011 and the gate dielectric layer 1012 form a gate structure 1006. The capacitor 1004 includes the metal gate 1011, a high-k dielectric layer 1021 disposed on the metal gate 1011, and a floating gate 1022 disposed on the high-k dielectric layer 1021.

[0227] Figure 11 An exemplary method 1100 for manufacturing Figure 10 the memory device 1000 is shown in a flowchart according to some embodiments. In combination with the followingFigures 12A to 12H to describe method 1100, Figures 12A to 12H showing a part of the memory device 1000 during an intermediate step of method 1100. Figures 12A to 12H A cross-sectional schematic diagram showing an intermediate stage of forming the memory device 1000 is illustrated according to some embodiments.

[0228] At step 1102, referring to Figure 12A , a partially formed device 1000 is provided. The partially formed device 1000 includes a first dielectric layer 1020, two via contacts 1025a and 1025b disposed in the dielectric layer 1020, and two S / D electrodes 1019a and 1019b respectively disposed on and coupled to the two via contacts 1025a and 1025b. The S / D electrode 1019a extends vertically from the bottom surface 1031a to the top surface 1032a and horizontally from the proximal sidewall 1033a to the distal sidewall 1034a. Similarly, in the X direction, the S / D electrode 1019b is substantially aligned with the S / D electrode 1019a, extends vertically from the bottom surface 1031b to the top surface 1032b, and horizontally from the proximal sidewall 1033b to the distal sidewall 1034b. The two S / D electrodes 1019a and 1019b may be formed in a dielectric layer (not shown) disposed on the first dielectric layer 1020, and then a part of the dielectric layer around and between the two S / D electrodes 1019a and 1019b is removed via a patterning and etching process to expose the top surfaces 1032a / 1032b of the S / D electrodes 1019a / 1019b, the sidewalls 1033a / 1033b / 1034a / 1034b of the S / D electrodes 1019a / 1019b, and the top surface 1041 of the first dielectric layer 1020.

[0229] At step 1104, referring to Figure 12B , two S / D regions 1014a and 1014b and a channel region 1015 are formed. In some embodiments, a semiconductor layer 1013 is deposited on the S / D electrodes 1019a and 1019b and covers the top surfaces 1032a / 1032b, the sidewalls 1033a / 1033b / 1034a / 1034b, and the top surface 1041 of the first dielectric layer 1020. The portions of the semiconductor layer 1013 disposed on the proximal sidewalls 1033a and 1033b may be processed respectively to form S / D regions 1014a and 1014b in the semiconductor layer 1013. The portion of the semiconductor layer 1013 disposed on the top surface 1041 between the two S / D electrodes 1019a and 1019b may form the channel region 1015. In some embodiments, the semiconductor layer 1013 is an IGZO layer deposited using ALD.

[0230] In some embodiments, an S / D layer (not shown) is deposited on S / D electrodes 1019a and 1019b. The S / D layer may cover top surfaces 1032a / 1032b, sidewalls 1033a / 1033b / 1034a / 1034b. The portions of the S / D layer disposed on distal sidewalls 1033a and 1033b may be processed separately to form S / D regions 1014a and 1014b in the S / D layer. Then, a semiconductor layer 1013 is deposited on the S / D layer. The portion of the top surface 1041 of the first dielectric layer 1020 between the two S / D electrodes 1019a and 1019b covered by the semiconductor layer 1013 may form a channel region 1015, and the channel region 1015 is connected to two independent S / D regions 1014a and 1014b.

[0231] At step 1106, refer to Figure 12C , a gate dielectric layer 1012 is deposited. The gate dielectric layer 1012 may include a high-k dielectric material deposited using ALD. The gate dielectric layer 1012 is deposited on the semiconductor layer 1013 and covers the S / D regions 1014a and 1014b and the channel region 1015.

[0232] At step 1108, refer to Figure 12D , a second dielectric layer 1030 is formed. The second dielectric layer 1030 is deposited on the gate dielectric layer 1012 and fills the spaces around and between the two S / D electrodes 1019a and 1019b. A CMP process may be performed to planarize the top surface 1037 of the second dielectric layer 1030.

[0233] At step 1110, refer to Figure 12E , an opening 1202 is formed. The opening 1202 may be formed by performing a patterning and etching process to remove portions of the second dielectric layer 1012 between the two S / D electrodes 1019a and 1019b to expose the surface of the gate dielectric layer 1012 disposed on the S / D regions 1014a and 1014b and the channel region 1015.

[0234] At step 1112, refer to Figure 12F , a metal gate 1011 is formed. In some embodiments, a metal layer is deposited on the second dielectric layer 1030 and fills the opening 1202, and then a CMP process is performed to remove the excess metal layer to form a metal gate 1011 between the two S / D electrodes 1019a and 1019b.

[0235] At step 1114, refer to Figure 12G, a high-k dielectric layer 1021 is formed. The high-k dielectric layer 1021 can be formed by performing a patterning and etching process to remove a portion of the metal gate 1011 between the two S / D electrodes 1019a and 1019b, forming an opening, depositing a layer of high-k dielectric material, and performing a CMP process to remove the excess high-k dielectric material, thereby forming the high-k dielectric layer 1021 in the opening.

[0236] At step 1116, referring to Figure 12H , a floating gate 1022 is disposed on the high-k dielectric layer 1021. In some embodiments, a third dielectric layer 1040 is deposited on the second dielectric layer 1030, and the floating gate 1022 is formed in the third dielectric layer 1040. The metal gate 1011, the high-k dielectric layer 1021, and the floating gate 1022 form a capacitor 1004. The capacitor 1004 and the transistor 1003 form a 1T1C memory element 1002.

[0237] An example of a semiconductor stack structure having a compact 1T1C memory element.

[0238] Figure 13 A cross-sectional schematic diagram showing an exemplary semiconductor stack structure 1300 (sometimes also referred to as "stack structure" 1300) according to some embodiments. The semiconductor stack structure 1300 includes one or more of the following: a memory device 100 or its memory element 102, a memory device 400 or its memory element 402, a memory device 700 or its memory element 702, and / or a memory device 1000 or its memory element 1002, with reference to Figure 1A , Figure 4 , Figure 7 and Figure 10 .

[0239] In the Figure 13 illustrated example, the semiconductor stack structure 1300 includes, among other components, a carrier substrate 1301 and a semiconductor device 1303. The semiconductor device 1303 is stacked on top of the carrier substrate 1301 and is bonded to the carrier substrate 1301 via a bonding structure 1320. The semiconductor device 1303 includes an interconnect structure 1304, a transistor portion 1306, a power rail portion 1308, a memory element portion 1310, a contact plug portion 1312, and one or more through oxide vias (TOVs) 1314, stacked in a vertical direction in sequence. The stack structure 1300 has a device area. The transistor portion 1306 may include one or more transistors 1307 in the device area. The memory element portion 1310 includes one or more memory elements 1302 in the device area. Thus, the memory element 1302 covers the transistor 1307 in the device area.

[0240] The memory element 1302 can be a 1T1C memory element, for example, the 1T1C memory elements 102, 402, 702, or 1002 described above. The transistor 1307 can be a field-effect transistor (FET) or device, such as a planar FET, a three-dimensional FET, a fin-line FET (FinFET), a nanosheet FET (NSFET), a nanowire FET (NWFET), or a gate-all-around FET (GAAFET).

[0241] The power rail portion 1308 includes at least one power rail. The power rail can include one or more metal lines and metal vias coupled to a reference voltage, a positive power supply voltage, etc. In the example shown, the first power rail 1325 and the metal via 1326 are electrically connected to the memory element 1302 via TOV1314, and the second power rail 1327 is electrically connected to the transistor 1307.

[0242] The interconnect structure 1304 and the contact plug portion 1312 are sometimes also referred to as electrical routing, and can each include a plurality of metal lines 1321 and metal via contacts 1322. The interconnect structure 1304 is configured to electrically connect the transistor 1307 to another feature or component in the carrier substrate 1301. The contact plug portion 1312 can also be regarded as an interconnect structure or a power routing structure. Similar to the interconnect structure 1304, the contact plug portion is configured to electrically connect the memory element 1302 to TOV1314 or another feature or component in a layer above or below the memory element portion 1310.

[0243] Figure 14 An exemplary method 1400 for manufacturing Figure 13 is shown in a flowchart of the stacked structure 1300 according to some embodiments. For illustrative purposes, the operations will be described with reference to an exemplary process for manufacturing the stacked structure 1300 as Figures 15A to 15Q shown. Figure 14 in the operations shown, Figures 15A to 15Q A cross-sectional schematic diagram showing the various stages of manufacturing the stacked structure 1300 according to some embodiments. Depending on the specific application, the operations can be performed in a different order or not performed. Note that the method 1400 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes can be provided before, during, or after the method 1400, and some of the additional processes may only be briefly described herein.

[0244] Refer to Figure 14, at step 1402, a partially formed semiconductor device 1303 is provided. In some embodiments, a transistor portion 1306 including one or more transistors 1307 is formed on a substrate 1502. As Figures 15A to 15Q shown, according to some embodiments, the transistor portion 1306 is formed on the substrate 1502. The transistor portion 1306 includes the transistors 1307. The transistor portion 1306 may also include two transistors adjacent to each other. Although the transistors 1307 are described herein with respect to nanosheet GAAFET embodiments, the transistors 1307 may be implemented as another type of transistor, such as FinFETs, nanowire FETs, and planar FETs.

[0245] The transistors 1307 may be formed on the substrate 1502, as Figure 15A shown, and the substrate 1502 is similar to Figure 1A the substrate 101. In some embodiments, the substrate 1502 may be a silicon-on-insulator (SOI) substrate that may include a buried layer (not shown). The substrate 1502 may be formed by growing or depositing a buried layer on a semiconductor wafer (e.g., a silicon wafer), and then growing or depositing a top silicon layer on the buried layer. One or more of the buried layer and the top silicon layer may be epitaxially formed.

[0246] Referring to Figure 15A , a SiN layer 1523 is formed on the substrate 1502. A superlattice 1555 may be formed on the SiN layer 1523. The superlattice 1555 may include stacked nanostructured layers 1521 and 1522 configured in an alternating configuration. In some embodiments, the nanostructured layer 1521 includes materials similar to each other (e.g., epitaxial Si), and the nanostructured layer 1522 includes materials similar to each other (e.g., epitaxial SiGe). In some embodiments, the superlattice 1555 is formed by etching a stack of two different semiconductor layers configured in an alternating configuration. The nanostructured layer 1522 will be replaced in a subsequent process, while the nanostructured layer 1521 will remain as part of the transistors 1307. Although Figure 15AThree nanostructured layers 1521 and four nanostructured layers 1522 are shown, but any number of nanostructured layers can be included in the superlattice 355. The alternating arrangement of the superlattice 355 can be achieved by alternately depositing or epitaxially growing SiGe and Si layers after depositing the first SiGe or Si layer on the SiN layer 1523. Etching the Si layer can form the nanostructured layer 1521 interleaved with the SiGe nanostructured layer 1522. Each of the nanostructured layers 1521-1522 can have a thickness between about 1 nm and about 10 nm. In some embodiments, the topmost nanostructured layer (e.g., Si layer) of the superlattice 1555 can be thicker than the underlying nanostructured layers.

[0247] The superlattice 1555, as a multi-layer stack of two different semiconductor materials, can be formed by an epitaxial growth process. The epitaxial growth process can employ (i) CVD, such as low-pressure CVD (LPCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD, reduced pressure CVD (RPCVD), or other suitable CVD processes, (ii) molecular beam epitaxy (MBE) process, (iii) another suitable epitaxial process, or (iv) a combination thereof. In some embodiments, the S / D regions can be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. This repeated deposition / partial etching process is also referred to as the "deposition-etch (CDE) process". In some embodiments, the S / D regions can be grown by selective epitaxial growth (SEG), where an etching gas can be added to facilitate selective growth on the exposed semiconductor surface of the substrate 1502 or fin, but not on the insulating material.

[0248] Within the superlattice 1555, the doping type of the two different semiconductor layers can be determined by introducing one or more precursors during the epitaxial growth process. For example, the stacked semiconductor layers can be in-situ p-type doped during the epitaxial growth process using p-type doping precursors such as diborane (B2H6) and boron trifluoride (BF3). In some embodiments, the stack of two different semiconductor layers can be in-situ n-type doped during the epitaxial growth process using n-type doping precursors such as phosphine (PH3) and arsine (AsH3).

[0249] After forming the superlattice 1555, the substrate 1502 can be etched to form fins to provide structural support for the superlattice 1555 while allowing the formation of shallow trench isolation (STI) regions in the substrate 1502 between adjacent transistors.

[0250] Referring to Figure 15A , a sacrificial structure 1507 is formed around the superlattice 1555. The sacrificial structure 1507 can be made of polysilicon and can include one or more sacrificial hard mask layers and sidewall spacers 1528 (omitted in the figure for simplicity). The sacrificial structure 1507 can be deposited and patterned using a hard mask layer, and the hard mask layer can be retained or removed during additional processing. The hard mask layer can be made of, for example, an oxide material or a silicon nitride (SiN) material grown and / or deposited using an ALD process. Alternatively, a hard mask for patterning a polysilicon layer can be deposited by any suitable method, and a photoresist mask can be used to pattern this hard mask. The sidewall spacers 1528 can be made of, for example, a SiN material that can be grown and / or deposited using an ALD process. The sacrificial structure 1507 is replaced during a later manufacturing process.

[0251] Next, the superlattice 1555 in the S / D regions is removed, as indicated by the opposing arrows in Figure 15A . After the S / D recess, the nanostructured layers 1521 and 1522 remain under the sacrificial structure 1507, as indicated by the dashed lines in Figure 15A . Removing the superlattice 1555 in the S / D regions can be accomplished using, for example, a wet etching process employing dilute hydrofluoric (DHF) acid and an ammonium hydroxide-peroxide water mixture (APM). The DHF can remove the silicon and SiGe nanostructured layers 1521 and 1522 outside the channel region while the channel region is protected by the hard mask and / or spacer layers of the sacrificial structure 1507. If such layers are made of SiN, the DHF will not substantially etch these layers. Alternatively, a dry etching process can be used to remove the superlattice 1555 in the S / D regions.

[0252] Referring to Figure 15B, the epitaxial S / D regions are formed on either side of the sacrificial structure 1507. For example, the S / D regions 1570 may be epitaxially grown from the nanostructured layers 1521 and / or 1522 of the superlattice 1555 below the sacrificial structure 1507. The S / D regions 1570 may be made of SiGe, for example, having a germanium concentration profile as follows: varying from about 35% germanium at the top and bottom of the S / D regions 1570 along the height of the S / D regions 1570 to about 50% to 65% germanium in the middle of the S / D regions 1570. In contrast, the germanium concentration near the bottom of the S / D regions in some existing GAAFETs may be lower, for example, about 25% germanium. The germanium concentration may affect the doping profile, and thus the potential in the S / D regions may affect the channel current. When the germanium concentration profile of the S / D regions 1570 is outside the range of about 35% - 65%, when implemented as a GAAFET, the channel current may be outside the desired range of operation of the transistor 1307. The S / D regions 1570 may be independently formed by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LYE), vapor phase epitaxy (VPE), SEG, or a combination thereof. Additionally, the S / D regions 1570 may be independently doped by in-situ doping during epitaxial growth and / or by implantation after epitaxial growth.

[0253] Referring to Figure 15B , a dielectric layer 1530 (e.g., an ILD layer) is deposited. The sacrificial structure 1507 is removed and replaced with a metal gate structure forming the gate terminal 1583 (or gate structure 1583) as described with respect to Figures 15C to 15G , resulting in the transistor 1307. During the replacement metal gate process, the nanostructured layer 1522 is also selectively removed to form a gate opening in the channel region. The gate opening is filled with metal by depositing the gate structure 1583 to form the GAA channel region 1557, as Figure 15B shown. The remaining nanostructured layer 1521 of the superlattice 1555 forms the nanostructured channels 1510 of two adjacent transistors 1307 sharing the S / D regions 1570. Each GAA channel region 1557 may include a GAA structure 1558 ( Figure 15B three are shown in

[0254] Figures 15C to 15G According to some embodiments, an enlarged cross-sectional view showing the operations for forming the Figure 15B shown gate structure 1583 and GAA channel region 1557 is shown. The GAA channel region 1557 includes a plurality of GAA structures 1558 that surround the channel 1510 to control the current therein.

[0255] Figure 15C Yes Figure 15A An enlarged cross-sectional view of the superlattice 1555 and the sacrificial structure 1507 shown in Figure 15C . As described above, the superlattice 1555 is etched back such that the remaining portion of the superlattice 1555 is located in the GAA channel region 1557 below the sacrificial structure 1507. Figure 15D An enlarged cross-sectional view of the GAA channel region 1557 after forming the inner spacer 1564 and the epitaxial S / D regions 1570 is shown. Figure 15D It shows that the inner spacer 1564 is formed in the GAA channel region 1557 adjacent to the nanostructured layer 1522 before the epitaxial S / D regions 1570 grow laterally outward in the X direction from the nanostructured layer 1521. Figure 15E An enlarged cross-sectional view of the GAA channel region 1557 after extracting the nanostructured layer 1522 and thus forming the void 1509 is shown. Figure 15F An enlarged cross-sectional view of the GAA channel region 1557 after replacing the sacrificial structure 1507 with the metal gate structure 1583 is shown. The sacrificial structure 1507 is removed, leaving the sidewall spacers 1528 in place. The metal gate structure 1583 is formed in a multi-step process to replace the sacrificial structure 1507.

[0256] Refer to Figure 15G , each GAA structure 1558 can be regarded as a radial gate stack, which includes an interface layer 1560, a gate dielectric layer 1561, a work function metal layer 1562, and a gate electrode 1563 from the outermost layer to the innermost layer. The gate electrode 1563 is operable to maintain a capacitively applied voltage across the nanostructured channel 1510. The inner spacer 1564 electrically isolates the GAA structure 1558 from the epitaxial S / D regions 1570 and prevents current leakage from the nanostructured channel 1510. In some embodiments, the inner spacer 1564 can be made of silicon carbonitride (SiCN). When the gate structure 1583 is formed, a radial gate stack is also formed to fill the void 1509 from the outside to the inside, starting from the interface layer 1560 and ending with the gate electrode 1563.

[0257] The interface layer 1560 can be made of silicon oxide and can be formed by a deposition, chemical oxidation, or thermal oxidation process. In some embodiments, the interface layer 1560 is silicon oxide formed using ozone (O3) through standard clean 1 (SC1) and standard clean 2 (SC2) wet cleaning processes. The thickness of the interface layer 1560 can be about Between about 1 and about 15 angstroms. The thickness of the gate dielectric layer 1561 can be between about 1 nm and about 5 nm. The thickness of the gate work function metal layer 1562 can be between about 2 nm and about 15 nm. Any suitable materials, dimensions, and formation methods for the gate dielectric layer 1561, the gate work function metal layer 1562, and the gate electrode 1563 are within the scope and spirit of this disclosure.

[0258] Reference Figure 14 , at step 1404, according to some embodiments, as Figures 15H to 15I shown, an interconnect structure 1304 is formed over the transistor 1307. The interconnect structure 1304 provides a GAAFET electrical connection to the transistor 1307 to a corresponding gate terminal 1583. The interconnect structure 1304 includes at least a first metallization layer, such as a metal wire 1571 coupled to the gate structure 1583 through a gate contact 1574, as Figure 15I shown. The metal wire 1571 can be in the form of copper wiring insulated by ILD layers 1530, 1531, and 1532. The ILD layers 1230, 1531, and 1532 can be made of an oxide (e.g., SiO2) and can be formed on a base layer 1533 made of silicon nitride (SiN). The spacer separating the ILD layer 1530 from the gate terminal 1583 can be made of silicon carbonitride (SiCN). The interconnect structure 1304 can be formed as a damascene structure, where the ILD is deposited, trenches are formed in the ILD by a plasma etching process, and the trenches are filled with copper using, for example, an electroplating process. The interconnect structure 1304 can also include one or more additional metallization layers 1305 formed in a similar manner to the metal wires 1321 and via contacts 1322 disposed in the plurality of ILD layers. The additional metallization layers 1305 are sometimes also regarded as redistribution layers (RDLs) or RDL structures.

[0259] Reference Figure 14 , at step 1406, the Figure 15I partially formed semiconductor device 1303 formed therein is bonded to a carrier substrate 1301, thereby producing a partially formed stacked structure 1300. As Figures 15J to 15KAs shown, a carrier substrate 1301 is provided. The carrier substrate 1301 may include a substrate 1381 and one or more metallization layers (or RDL structures, etc.) disposed on the substrate 1381. The carrier substrate 1301 has a front side (F) and a back side (B), and the substrate 1381 is located on the back side (B), while the topmost metallization layer (i.e., metallization layer 1382) is located on the front side (F). Similarly, the semiconductor device 1303 has a front side (F) and a back side (B). The carrier substrate 1301 is aligned with and stacked on top of the semiconductor device 1303, and the front side (F) of the carrier substrate 1301 and the partially formed semiconductor device 1303 are joined in a face-to-face manner to form a joining structure 1320 (as Figure 15K shown).

[0260] In some embodiments, the carrier substrate 1301 and the semiconductor device 1303 are joined by a hybrid bonding technique, so the joining structure 1320 is a hybrid bonding structure. For example, the hybrid bonding can be performed by directly joining a conductive element (e.g., the metal wire 1321 of the metallization layer 1382) in the carrier substrate 1301 to a corresponding conductive element (e.g., the metal wire 1321 of the metallization layer 1305 is aligned with the metal wire 1321 of the metallization layer 1382) in the partially formed semiconductor device 1303 through metal-to-metal bonding. The topmost dielectric layer (or ILD layer) in the carrier substrate 1301 is directly connected to the corresponding topmost dielectric layer (or ILD layer) in the semiconductor device 1303 through non-metallic covalent bonding (e.g., siloxane bonding or Si-O-Si bonding).

[0261] Compared with traditional bonding, hybrid bonding has many advantages. For example, hybrid bonding generates a very strong bonding strength between two wafers, thus producing a stronger bond than other bonding techniques (such as adhesive bonding or thermocompression bonding). The hybrid bonding process can be carried out with high precision and accuracy, thus obtaining a higher alignment accuracy, which is beneficial for manufacturing complex and multi-layer structures with very small feature sizes. Hybrid bonding can be performed at a relatively low temperature (e.g., below 400 °C), thus minimizing the risk of thermal damage to the wafer or the devices thereon. Different from other bonding techniques, hybrid bonding does not require the use of additional materials, such as adhesives or solders, which may bring contamination or reliability problems.

[0262] Alternatively, a bonding process using a bonding / adhesive layer can be employed to bond the carrier substrate 1301 and the semiconductor device 1303. In some embodiments, an oxide layer (not shown) is deposited on the interconnect structure 1304 as a bonding interface layer. The bonding interface layer can be an oxide deposited using a high-density plasma (HDP) process at a temperature between about 350 °C and about 450 °C. The deposition process can use reaction gases including, for example, SiH4, N2O, and O2, with a pressure between about 5 mTorr and about 20 mTorr and a plasma power between about 4000 W and about 60000 W. To improve its bonding strength, a CMP process can be used to polish the bonding interface layer, thereby forming a smooth surface with a surface roughness less than about

[0263] The semiconductor device 1303 is bonded to the carrier substrate 1301 using the bonding interface layer (i.e., the bonding structure 1320) to form a stacked structure 1300. The bonding process can include pretreatment of the semiconductor device 1303 or the carrier substrate 1301 or both. The pretreatment can include, for example, wet cleaning in water to ensure the presence of OH radicals on one or both of the surfaces to be bonded. After the pretreatment, the front side (F) of the carrier substrate 1301 is bonded to the front side (F) of the semiconductor device 1303 at the bonding interface layer. The bonding process can generally be performed using a bonding tool for wafer on wafer (WOW) bonding. An annealing operation can be performed after the bonding process to ensure high bonding strength.

[0264] Referring to Figure 14 , at step 1408, the stacked structure formed in Figure 15K is flipped such that the back side (B) of the semiconductor device 1303 faces up, as shown in Figure 15L . Figure 14 The remaining portion of the processing operation of

[0265] Referring to Figure 14 , according to some embodiments, at step 1410, the substrate 1502 is thinned to expose the transistor S / D regions 1570, as shown in Figure 15L . A grinding operation is performed on the substrate 1502 to reduce its thickness from about 100 μm to a thickness between about 5 μm and about 6 μm. The remaining silicon can be further reduced to a thickness of about . Thus, almost all of the original substrate 1502 is removed. Thus, the fully formed memory element 1302 can be considered to be formed on the carrier substrate 1301. Referring toFigure 15M In the S / D region 1570, a recess distance (t) can be formed, and the SiN layer 1523 serves as a hard mask for protecting the gate region of the transistor 1307. The recess distance (t) can be between about 20 nm and about 50 nm. The S / D recess operation can be accomplished by a timed plasma etch operation using an anisotropic etch chemistry. Alternatively, a wet etch chemistry (such as DHF and APM) can be used to achieve the S / D recess.

[0266] Referring to Figure 14 According to some embodiments, at step 1412, a backside S / D contact 1589 can be formed as Figure 15N shown. An insulating layer 1500 can be deposited over the recessed S / D region 1570 and the SiN layer 1523. The insulating layer 1500 can be a low-k silicon oxide including carbon. A hard mask (not shown) can be used to pattern the insulating layer 1500, and the hard mask can be patterned using a photoresist mask. A T-shaped via (not shown) can be etched into the insulating layer 1580 using a via etch chemistry selective to SiN and silicon (e.g., a fluorine-based anisotropic plasma etch for removing oxides).

[0267] After forming the T-shaped via, the hard mask is removed, and the T-shaped via is filled with metal to form a backside S / D contact 1589 having a T shape as Figure 15N shown. The bottom width of the T-shaped backside S / D contact 1589 can be between about 20 nm and about 40 nm. The backside S / D contact 1589 is coupled to the shared S / D region 1570 at the interface 1586, where the interface 1586 can include a contact silicide (e.g., titanium silicide (TiSi), nickel silicide (NiSi), and cobalt silicide (CoSi)). The backside S / D contact 1589 can undergo a CMP process to be coplanar with the insulating layer 1580.

[0268] Referring to Figure 14 According to some embodiments, at step 1414, it can be as Figure 15OThe power rail portion 130 can be formed by depositing one or more dielectric layers (or ILD layers) 1581 and forming one or more power rails (e.g., power rails 1325 and 1327) in the dielectric layer 1581. The power rails 1325 and 1327 can be formed by depositing a conductive material. In some embodiments, the power rails 1325 and 1327 can each include a metal layer (or metal line), which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the power rail can also include metal vias (e.g., metal via 1326) coupled to the top surface or bottom surface of the power rail. In some embodiments, the power rails 1325 and 1327 include copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. The power rails 1325 and 1327 can be formed using, for example, PVD, electroplating, etc.

[0269] In Figure 15O the example of, the second power rail 1327 is physically and electrically coupled to the epitaxial S / D region 1570 through the backside S / D contact 1589. Subsequently, a planarization process (e.g., chemical mechanical polishing (CMP), grinding, etch back, etc.) can be performed on the surface of the second power rail 1327. As a result of the thinning process, the thickness of the power rail 1327 can be in the range of about 10 nm to about 200 nm. Subsequently, the first power rail 1325 and the metal via 1326 are formed in the dielectric layer 1581 above the second power rail 1327 using a similar process. The first power rail 1325 is electrically connected to a component or device (e.g., memory element 1302) above the first power rail 1325.

[0270] The widths of the power rails 1325 and 1327 can be in the range of about 20 nm to about 40 nm. The power rails 1325 and 1327 are formed on the backside of the transistor 1307 instead of the front side of the transistor 1307, allowing for a larger power rail width, which helps to reduce resistance. For example, the widths of the power rails 1325 and 1327 can be more than twice the width of the front-side power rails. Since the power rail area is not limited by the interconnect structures present on the front side of the transistor 1307, a larger power rail width can be achieved when the power rails are formed on the backside of the transistor 1307. Note that the widths of the power rails 1325 and 1327 can vary according to design requirements. In other words, the width and thickness of the first power rail 1325 can be equal to, greater than, or less than the second power rail 1327.

[0271] Referring Figure 14 , according to some embodiments, at step 1416, it can be as Figure 15PMemory element portion 1310 is formed as shown. A dielectric layer (e.g., an ILD layer) can be formed on power rail portion 1308, and one or more memory elements 1302 can be formed in metallization layer 1382. In some embodiments, memory element 1302 is a 1T1C memory element, such as memory element 102, 402, 702, or 1002 according to the present disclosure. Memory element 1302 can be electrically connected to first power rail 1325 through via contact 1322 in metallization layer 1382.

[0272] Reference Figure 14 According to some embodiments, at step 1418, Figure 15Q The contact plug portion 1312 is formed as shown. A gap can be formed by removing a portion of the dielectric layer disposed on the memory element portion 1310, and the gap is filled with a conductive material to form a contact plug (i.e., a metal line 1321 or a through-hole contact 1322). The contact plug can be formed using any suitable process (such as deposition, inlay, dual inlay, etc.). The conductive material can be formed of, for example, doped polysilicon, metal, metal silicide, conductive metal nitride, or a combination thereof. One or more contact plugs are used to provide electrical connections to other components within the semiconductor device.

[0273] Reference Figure 14 According to some embodiments, at step 1420, one or more TOVs 1314 are formed, such as Figure 15Q As shown. TOV 1314 can be used to electrically interconnect memory element 1302 and power rail 1325. TOV 1314 can be used to electrically interconnect memory element 1302 to transistor 1307 or other components within stacked structure 1300. TOV 1314 can be formed by etching a via (e.g., a tapered via) through multiple dielectric layers to connect the power rail 1325 of transistor 1307 or S / D region 1570 or another component or device within stacked structure 1300, and filling the tapered via with a metal (e.g., copper) to connect the topmost metallization layer of contact plug portion 1312. In some embodiments, the depth-to-width ratio of tapered TOV 1314 is in the range of about 15:1 to about 25:1. The lower portion of TOV 1314 may also include a diffusion barrier layer and / or a silicide contact, wherein the silicide contact is connected to the power rail 1325 and includes an intervening metal. TOV 1314 may be used in conjunction with power rail 1325 to provide power to memory device 1302 .

[0274] Figures 16A to 16D is a cross-sectional schematic diagram showing an additional example stacking structure, which is Figure 13 The stacking structure 1300 is changed. Figure 16AIn the example shown, the stacked structure 1600A includes semiconductor devices 1303 stacked above and bonded to a carrier substrate 1301. The semiconductor device 1303 includes a memory element portion 1310, and the memory element portion 1310 further includes 1T1C memory elements 102. As described above, the 1T1C memory element 102 has a compact structure and includes a transistor 103 stacked above a capacitor 104. The transistor 103 and the capacitor 104 share a metal gate 111. The capacitor 104 has a floating gate 122 disposed at the bottom of the 1T1C memory element 102. Two S / D electrodes 119a / 119b can be coupled to the power rail 1325 through via contacts 125a / 125b, a contact plug portion 1312, and a TOV 1314. In some embodiments, the floating gate 122 can be electrically coupled to the power rail 1325 directly or through one or more via contacts.

[0275] Similarly, in Figure 16B the example shown, the stacked structure 1600B includes 1T1C memory elements 402 in the memory element portion 1310. As described above, the 1T1C memory element 402 has a compact structure and includes a capacitor 404 stacked above a transistor 403. The transistor 403 and the capacitor 404 share a metal gate 411. The capacitor 404 has a floating gate 422 disposed at the top of the 1T1C memory element 402. The floating gate 422 can be coupled to the power rail 1325 through a contact plug portion 1312 and a TOV 1314. In some embodiments, two S / D electrodes 419 can be electrically coupled to the power rail 1325 directly or through one or more contact plugs.

[0276] Similarly, in Figure 16C the example shown, the stacked structure 1600C includes 1T1C memory elements 702 in the memory element portion 1310. As described above, the 1T1C memory element 702 has a compact structure and includes a capacitor 704 partially surrounded by a transistor 703. The transistor 703 and the capacitor 704 share a metal gate 711. The capacitor 704 has a floating gate 722 disposed at the bottom of the 1T1C memory element 702. The floating gate 722 can be coupled to the power rail 1325 directly or through one or more contact plugs. In some embodiments, two S / D electrodes 419 can be electrically coupled to the power rail through via contacts 725a / 725b, a contact plug portion 1312, and a TOV 1314.

[0277] Similarly, in Figure 16DIn the example shown, the stacked structure 1600D includes the 1T1C memory element 1002 in the memory element portion 1310. As described above, the 1T1C memory element 1002 has a compact structure and includes a capacitor 1004 stacked above the transistor 1003. The transistor 1003 and the capacitor 1004 share the metal gate 1011. The capacitor 1004 has a floating gate 1022 disposed on top of the 1T1C memory element 1002. The floating gate 1022 can be coupled to the power rail 1325 through the contact plug portion 1312 and the TOV 1314. In some embodiments, the two S / D electrodes 1019 can be directly or electrically coupled to the power rail 1325 through one or more contact plugs.

[0278] Figure 17 Another example of a semiconductor stacked structure 1700 according to some embodiments of the present disclosure is shown. The semiconductor stacked structure 1700 is Figure 13 a variation of the semiconductor stacked structure 1300. In the example shown, the semiconductor stacked structure 1700 includes a device region and a seal ring region. The various components in the device region of the semiconductor stacked structure 1700 are similar to those in the semiconductor stacked structure 1300 and will not be repeated unless otherwise specified.

[0279] At least one difference between the semiconductor stacked structure 1700 and the semiconductor stacked structure 1300 is that the semiconductor stacked structure 1700 further includes a metal-insulator-metal (MIM) capacitor 1704 in the device region of the carrier substrate 1301. The MIM capacitor 1704 can provide additional storage capacity for the stacked structure 1700. The MIM capacitor 1704 can be a planar, cylindrical, cup-shaped, or strip-shaped MIM structure, and each MIM capacitor 1704 includes a top electrode (e.g., Figure 17 the electrode 1704a), a bottom electrode (e.g., Figure 17 the electrode 1704b), and a dielectric / insulating layer (e.g., Figure 17 the layer 1704c) on either side. In some embodiments, the MIM capacitor 1704 can be electrically coupled to the transistor 1307 to form another memory element (e.g., a 1T1C memory element or a 2T1C memory element) in the device region. In some embodiments, the MIM capacitor 1704 is a ferroelectric capacitor. In this configuration, the memory element 1302 (i.e., the compact 1T1C memory element 102, 402, 702, or 1002), the transistor 1307, and the MIM capacitor 1704 are vertically stacked, and these components at least partially overlap each other in the vertical direction. This configuration is beneficial for increasing the element density in an integrated circuit wafer.

[0280] At least another difference between semiconductor stack structure 1700 and semiconductor stack structure 1300 is that semiconductor stack structure 1700 further includes a seal ring structure 1710 disposed in a seal ring region. The seal ring region may be close to the periphery of stack structure 1700. For simplicity, Figure 17 only a part of the seal ring region is shown, and it can be understood that the seal ring region may continuously surround the device region. One or more seal rings 1710 (sometimes also referred to as "seal ring elements") may be formed in the seal ring region. The seal ring 1710 can be used to help protect functional components in the device region. The seal ring 1710 further strengthens the stack structure 1700 and the final package or product derived from the stack structure 1700, improves the robustness of the stack structure, and prevents or reduces damage during subsequent dicing processes. Additionally, if needed, the seal ring 1710 can be electrically connected to functional circuit elements within the device region to provide electrical connection to those elements. The seal ring 1710 can include a conductive material, such as copper, aluminum, tungsten, their alloys, etc. However, other materials, such as a conductive material layer and an insulating material layer, can be alternatively used. The width of the seal ring 1710 can be formed to be between about 5 μm and about 300 μm, such as about 10 μm.

[0281] Figure 18 An exemplary method 1800 for manufacturing Figure 17 the stack structure 1700 is shown in a flowchart according to some embodiments. For illustrative purposes, the operations shown in Figure 18 will be described with reference to an exemplary process for manufacturing the stack structure 1700, as Figures 19A to 19E shown, Figures 19A to 19E Cross-sectional schematic views showing various stages of manufacturing the stack structure 1700 are shown according to some embodiments. Method 1800 is a similar variation of method 1400, and similar operations will not be repeated unless otherwise specified.

[0282] Referring to Figure 18 , according to some embodiments, at step 1802, a partially formed semiconductor device 1303 is provided. According to some embodiments, at step 1804, a carrier substrate 1301 is provided. As Figure 19AAs shown, both the semiconductor device 1303 and the carrier substrate 1301 have a device area and a seal ring area that are vertically aligned face-to-face. The semiconductor device 1303 includes a substrate 1502, a transistor 1307 in the transistor portion 1306, an interconnect structure 1304 above the transistor portion 1306 in the device area, and a first seal ring portion 1902 in the seal ring area. The carrier substrate 1301 includes a substrate 1381, a MIM capacitor 1704, and a topmost metallization layer 1382 in the device area, and a second seal ring portion 1904 in the seal ring area. The transistor 1307 and the interconnect structure 1304 can be formed in the device area of the semiconductor device 1303 while (or during the same process) the first seal ring portion 1902 is formed. Similarly, the MIM capacitor 1704 and the metallization layer 1382 can be formed in the device area of the carrier substrate 1301 while (or during the same process) the second seal ring portion 1904 is formed.

[0283] At step 1806, the semiconductor device 1303 and the carrier substrate 1301 are aligned and bonded face-to-face (i.e., front-to-front) to form a partially formed stacked structure 1700, as Figure 19B shown. A hybrid bonding process can be performed, for example, a bonding structure 1320 can be formed at the interface of both the device area and the seal ring area. The interconnect structure 1304 and the metallization layer 1382 are bonded at the device area, and the first seal ring portion 1902 and the second seal ring portion 1904 are bonded at the seal ring area.

[0284] At step 1808, the stacked structure 1700 is flipped so that the back side (B) of the semiconductor device 1303 faces up, as Figure 19C shown. At step 1810, backside S / D contacts 1589 and power rail portions 1308 are then formed in the device area, and a third seal ring portion 1906 is formed in the seal ring area during the same process, as Figure 19D shown. The third seal ring portion 1906 is aligned with and connected to the first seal ring portion 1902.

[0285] At step 1812, memory elements 1302 and contact plug portions 1312 are then formed in the device area, and a fourth seal ring portion 1908 is correspondingly formed in the seal ring area during the same process, as Figure 19E shown. The fourth seal ring portion 1908 is aligned with and connected to the third seal ring portion 1906. In this way, the seal ring 1710 is formed in the seal ring area of the stacked structure 1700.

[0286] According to some aspects of the present disclosure, a memory element is provided. In one example, the memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on a top surface of the metal gate. The transistor further includes two independent S / D regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on the top portion of the gate dielectric layer. The transistor further includes two independent S / D electrodes respectively disposed on the two S / D regions.

[0287] In some embodiments, the memory element is a one-transistor-one-capacitor (1T1C) memory element. In some embodiments, the memory element further includes two via contacts respectively disposed on the two S / D electrodes. In some embodiments, the channel region is formed in a semiconductor layer disposed on the top portion of the gate dielectric layer. In some embodiments, the semiconductor layer is an indium gallium zinc (IGZO) layer. In some embodiments, the S / D regions are respectively formed in S / D layers disposed on the side portions of the gate dielectric layer. In some embodiments, the aspect ratio of the high-k dielectric layer is substantially less than 1.

[0288] According to some aspects of the present disclosure, a semiconductor device is provided. In one example, the semiconductor device includes a substrate, an interconnect structure disposed on the substrate, and a memory element disposed above a logic device. The memory element and the logic device at least partially overlap in a vertical direction. The memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on a top surface of the metal gate. The transistor further includes two independent S / D regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on the top portion of the gate dielectric layer. The transistor further includes two independent S / D electrodes respectively disposed on the two S / D regions.

[0289] In some embodiments, the memory element is a transistor-one capacitor (1T1C) memory element. In some embodiments, the memory element further includes a power rail portion disposed between the logic device and the memory element, and the power rail portion at least partially overlaps the logic device and the memory element. The power rail portion includes a first power rail electrically connected to the memory element and a second power rail electrically connected to the logic device. In some embodiments, the first power rail is electrically connected to the floating gate of the memory element. In some embodiments, the first power rail is electrically connected to one or both of the S / D electrodes. In some embodiments, the memory element further includes a contact plug portion disposed above the memory element and electrically connected to the memory element. In some embodiments, the memory element further includes a through oxide via (TOV) electrically connecting the contact plug portion, wherein the memory element is electrically connected to the first power rail through the TOV. In some embodiments, the memory element further includes a passive device disposed between the interconnect structure and the substrate, wherein the passive element at least partially overlaps the logic device and the memory element. In some embodiments, the passive device is a metal-insulator-metal (MIM) capacitor. In some embodiments, a seal ring is further included. In some embodiments, the logic device is a gate-all-around field-effect transistor (GAAFET).

[0290] According to some aspects of the present disclosure, a semiconductor device is provided. In one example, the semiconductor device includes a substrate, an interconnect structure disposed on the substrate, a memory element disposed above the logic device, a logic device, and a contact plug portion. The logic device is disposed on the interconnect structure and electrically connected to the interconnect structure. The contact plug portion is disposed above the memory element and electrically connected to the memory element. The memory element includes a capacitor and a transistor stacked above the capacitor. The capacitor includes a floating gate, a high-k dielectric layer disposed on the floating gate, and a metal gate disposed on the high-k dielectric layer. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes a metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on two sidewalls of the metal gate and a top portion disposed on the top surface of the metal gate. The transistor further includes two independent source / drain regions respectively formed on two side portions of the gate dielectric layer and a channel region formed on the top portion of the gate dielectric layer. The transistor further includes two independent source / drain electrodes respectively disposed on the two source / drain regions.

[0291] According to some aspects of the present disclosure, a method for manufacturing a memory element, a semiconductor device, and a semiconductor stack structure is provided. In one example, a method includes: forming a transistor on a substrate, the transistor including S / D regions and a gate disposed above the S / D regions; forming an interconnect structure disposed on and in contact with the gate of the transistor; bonding the front surface of the interconnect structure face-to-face with the front surface of a carrier substrate to form a stack structure; inverting the stack structure; thinning the substrate to expose the S / D regions of the transistor; forming back S / D contacts on the S / D regions; forming a plurality of power rails on the back S / D contacts; forming memory elements on the power rails; and forming contact plug portions on the memory elements.

[0292] In some embodiments, the method further includes forming a through-oxide via (TOV) that interconnects the contact plug portion with one of the plurality of power rails.

[0293] The features of several embodiments are outlined above so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein by those skilled in the art.

Claims

1. A memory element, characterized in that, Comprising: A capacitor, comprising: A floating gate; A high-k dielectric layer disposed on and in contact with the floating gate; and A metal gate disposed on and in contact with the high-k dielectric layer, the metal gate extending horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface; and A transistor stacked on the capacitor; wherein the transistor comprises: The metal gate; A gate dielectric layer disposed on the metal gate, the gate dielectric layer comprising side portions respectively disposed on the first sidewall and the second sidewall of the metal gate and a top portion disposed on the top surface of the metal gate; Two independent source / drain regions respectively formed on the two side portions of the gate dielectric layer; A channel region formed on the top portion of the gate dielectric layer; and Two independent source / drain electrodes respectively disposed on the two source / drain regions.

2. The memory element according to claim 1, characterized in that, Wherein the memory element is a one-transistor-one-capacitor memory element.

3. The memory element according to claim 1, wherein Further comprising: Two via contacts respectively disposed on the two source / drain electrodes.

4. The memory element according to claim 1, wherein Wherein the channel region is formed in a semiconductor layer disposed on the top portion of the gate dielectric layer.

5. The memory element according to claim 1, wherein Wherein the two source / drain regions are respectively formed in a source / drain layer disposed on the side portions of the gate dielectric layer.

6. A semiconductor device, characterized in that, Comprising: A substrate; An interconnect structure disposed on the substrate; A logic device disposed on and electrically connected to the interconnect structure; A memory element disposed on the logic device, wherein the memory element comprises: A capacitor, comprising: A floating gate; A high-k dielectric layer disposed on and in contact with the floating gate; and A metal gate disposed on and in contact with the high-k dielectric layer, the metal gate extending horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface; and A transistor stacked on the capacitor; wherein the transistor comprises: The metal gate; A gate dielectric layer disposed on the metal gate, the gate dielectric layer comprising side portions respectively disposed on the first sidewall and the second sidewall of the metal gate and a top portion disposed on the top surface of the metal gate; Two independent source / drain regions respectively formed on the two side portions of the gate dielectric layer; A channel region formed on the top portion of the gate dielectric layer; and Two independent source / drain electrodes respectively disposed on the two source / drain regions; and Wherein in the vertical direction, the memory element at least partially overlaps with the logic device.

7. The semiconductor device according to claim 6, wherein, Further comprising: A power rail portion disposed between the logic device and the memory element, and the power rail portion at least partially overlaps with the logic device and the memory element, the power rail portion comprising a first power rail electrically connected to the memory element and a second power rail electrically connected to the logic device.

8. The semiconductor device according to claim 7, wherein, Wherein the first power rail is electrically connected to the floating gate of the memory element.

9. The semiconductor device according to claim 7, wherein, Wherein the first power rail is electrically connected to one or both of the two source / drain electrodes.

10. A semiconductor device, characterized in that, Comprising: A substrate; An interconnect structure disposed on the substrate; A logic device disposed on the interconnect structure and electrically connected to the interconnect structure; A memory element disposed on the logic device, wherein the memory element comprises: A capacitor, comprising: A floating gate; A high-k dielectric layer disposed on and in contact with the floating gate; and A metal gate disposed on and in contact with the high-k dielectric layer, the metal gate extending horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface; and A transistor stacked on the capacitor; wherein the transistor comprises: The metal gate; A gate dielectric layer disposed on the metal gate, the gate dielectric layer comprising side portions respectively disposed on the first sidewall and the second sidewall of the metal gate and a top portion disposed on the top surface of the metal gate; Two independent source / drain regions respectively formed on the two side portions of the gate dielectric layer; A channel region formed on the top portion of the gate dielectric layer; and Two independent source / drain electrodes respectively disposed on the two source / drain regions; and a contact plug portion disposed above the memory element and electrically connected to the memory element.

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