High-speed data acquisition, storage and playback device

Abstract

The utility model relates to a high-speed data acquisition, storage and playback device. The device comprises a high-speed AD module; a storage module; a high-speed DA module; the computer is provided with a central processing unit; wherein the high-speed AD module is in communication connection with the storage module, the storage module is in communication connection with the computer, and the storage module is in communication connection with the high-speed DA module; wherein the first FPGA is configured to directly control data interaction between the first high-speed communication interface and the storage module and analog-digital signal conversion of the high-speed AD converter in a mode of bypassing the central processing unit; the second FPGA is configured to directly control the access to the DDR cache and the data interaction between the disk array and the second and third high-speed communication interfaces and the network interface in a manner of bypassing the central processing unit; and the third FPGA is configured to directly control data interaction between the fourth high-speed communication interface and the storage module and digital-analog signal conversion of the high-speed DA converter in a manner of bypassing the central processing unit.

Description

Technical Field

[0001] The utility model relates to the field of high-speed data acquisition, storage and data playback devices. Background Art

[0002] In the field of data acquisition, storage and playback, high-speed data acquisition, storage and playback devices are important equipment. It can acquire and store high-speed data and playback it when needed. Such devices are widely used especially in applications that require high-speed data processing and high-precision data storage, such as data center servers, etc., as well as other applications that require high-performance computing, storage and network services. In these scenarios, the importance of high-speed data acquisition, storage and playback devices is particularly prominent. The solution of high-speed data acquisition, storage and playback devices usually consists of a high-speed AD module, a storage module, a high-speed DA module and a computer. The high-speed AD module is used to acquire high-speed data and send the data to the storage module for storage. The storage module is used to store high-speed data and send the data to the high-speed DA module for playback when needed. The high-speed DA module is used to convert the digital signal in the storage module into an analog signal for playback. The computer is used to control the operation of the entire device and can communicate with external devices through a network interface.

[0003] CN202410030844.4 discloses a high-speed SATA storage system, including: a processor module, a flash memory module, an FPGA module, a storage array module, a first memory module and a second memory module. The advantages are: the function of the file system is realized by the processor running the operating system, and files and disks can be conveniently managed. The disadvantages are: the storage and reading instructions need to be sent through the processor, and the real-time performance is poor. The data transmission bandwidth of the SATA interface is limited and cannot meet higher bandwidth requirements.

[0004] CN202311767864.1 discloses a high-speed data storage and transmission method based on ZYNQ, including ZYNQ, SSD and DDR storage and steps. The advantages are: the disk with an NVME interface is adopted, which can meet the requirements of higher-speed data storage bandwidth. The disadvantages are: the real-time performance of ZYNQ still cannot meet the requirements of scenarios with high requirements; the data export rate is slow.

[0005] However, there are some problems with existing high-speed data acquisition, storage, and playback devices in practical applications. First, the data access and interaction of existing devices usually rely on a computer for control, which not only increases the complexity of the system but also limits the portability and flexibility of the device. Second, the existing devices are not ideal in terms of data transmission speed and its stability, as well as data storage capacity, and cannot meet the application requirements of some high-speed data processing and high-precision data storage. In addition, the existing devices also have problems with the accuracy of data playback and the stability of transmission speed, and cannot guarantee the integrity and accuracy of the data. Therefore, there are many problems with existing high-speed data acquisition, storage, and playback devices in practical applications, and there is a need in the industry to further improve and optimize high-speed data acquisition, storage, and playback devices.

[0006] The information included in this background art section of the specification of the present utility model, including any references cited herein and any description or discussion thereof, is included solely for the purpose of technical reference and is not considered to be the subject matter that limits the scope of the present utility model. Summary of the Utility Model

[0007] In view of the above and other more ideas, the present utility model is proposed.

[0008] The prior art can achieve high-speed data storage. However, in the case of high-speed data acquisition, at the same time of high bandwidth, higher real-time performance is required. Traditional high-speed storage devices generally use network interfaces for data transmission and cannot meet the requirement of converting the stored data into analog signals through a high-speed digital-to-analog converter. In particular, in the prior art, high-speed storage devices generally use the average speed within a relatively long time range as the design index. However, the urgent requirements for data storage and reading in high-speed AD / DA conversion are, in addition to high data rates, also the smoothness of the data transmission rate, that is, as small a data rate fluctuation as possible is required.

[0009] According to one aspect of the present utility model, a high-speed data acquisition, storage, and playback device is provided, comprising: a high-speed AD module, which includes: a high-speed AD converter, a first FPGA, and a first high-speed communication interface; a storage module, which includes: a second FPGA; a DDR cache; a disk array for storing data; a second high-speed communication interface; a third high-speed communication interface; and a network interface, wherein the second FPGA within the storage module is configured to be connected to the DDR cache, the second FPGA is connected to the disk array, the second FPGA is connected to the second high-speed communication interface, the third high-speed communication interface, and the network interface and is configured to directly control their data transmission, and the DDR cache is configured for buffered storage of high-speed data; a high-speed DA module, which includes: a fourth high-speed communication interface, a third FPGA, and a high-speed DA converter; a computer, which is configured with a central processing unit; wherein, there is a communication connection between the high-speed AD module and the storage module, a communication connection between the storage module and the computer, and a communication connection between the storage module and the high-speed DA module; wherein, the first FPGA is configured to directly control, in a manner bypassing the central processing unit: the data interaction between the first high-speed communication interface and the storage module; and the analog-to-digital signal conversion of the high-speed AD converter; wherein, the second FPGA is configured to directly control, in a manner bypassing the central processing unit: the access to the DDR cache; the data interaction between the disk array and the second high-speed communication interface, the third high-speed communication interface, and the network interface; wherein, the third FPGA is configured to directly control, in a manner bypassing the central processing unit: the data interaction between the fourth high-speed communication interface and the storage module; and the digital-to-analog signal conversion of the high-speed DA converter.

[0010] According to an embodiment, control software is installed on the computer, and the control software is used to generate control instructions for transmission through the network interface of the computer, and the network interface of the computer is directly connected to the network interface of the storage module.

[0011] According to an embodiment, the control software is configured to send data acquisition and storage instructions to the storage module, and the storage module is configured to accordingly send the data acquisition instructions to the high-speed AD module, whereby the high-speed AD module starts data acquisition work and performs analog-to-digital signal conversion, and the storage module starts storing the corresponding data.

[0012] According to one embodiment, the control software is configured to send a data read and playback instruction to the storage module, and the storage module is configured to send a data read and playback instruction to the high-speed DA module accordingly. Thereby, the storage module starts to store corresponding data, and the high-speed DA module starts to perform digital-to-analog signal conversion for data read and playback.

[0013] According to one embodiment, the DDR cache is a single-group DDR or multiple groups of DDR.

[0014] According to one embodiment, the disk array can be constructed by disks with SATA interfaces or disks with NVME interfaces.

[0015] According to one embodiment, the first high-speed communication interface, the second high-speed communication interface, the third high-speed communication interface, and the fourth high-speed communication interface are selected from any one of the following: fiber optic interface, network twisted pair interface, and high-speed differential signals on a printed circuit board; the high-speed AD converter uses a parallel LVCMOS interface, a parallel LVDS interface, or a JESD204B serial interface; and the high-speed DA converter uses a parallel LVCMOS interface, a parallel LVDS interface, or a JESD204B serial interface.

[0016] According to one embodiment, the average jitter of the high-speed data acquisition, storage, and playback device is less than 1 millisecond.

[0017] According to one embodiment, the total delay of the high-speed data acquisition, storage, and playback device during operation is in the range of 0.2 - 0.3 milliseconds.

[0018] According to one embodiment, the high-speed data acquisition, storage, and playback device is a high-speed data acquisition, storage, and playback device applicable to a data center, such as an Internet data center (IDC).

[0019] Compared with the prior art, the present utility model can solve one or more of the following main technical problems and thus achieve corresponding technical effects:

[0020] 1) Improve the actual data transmission rate and minimize rate fluctuations, reduce system complexity, and enhance the portability and flexibility of the device: Existing high-speed data acquisition, storage, and playback devices usually rely on a computer for control, which not only increases the system complexity but also limits the portability and flexibility of the device. This technical solution realizes the autonomous control and high-speed data transmission of the device by setting an FPGA and a high-speed communication interface in the high-speed AD module, setting an FPGA, a DDR cache, a disk array, a high-speed communication interface A, a high-speed communication interface B, and a network interface in the storage module, and setting an FPGA and a high-speed DA converter in the high-speed DA module. Thus, a high actual data transmission rate and minimal rate fluctuations are achieved, and it becomes possible to reduce system complexity and enhance the portability and flexibility of the device.

[0021] 2) Increase the data transmission speed and data storage capacity: Existing high-speed data acquisition, storage, and playback devices have limitations in data transmission speed and data storage capacity and cannot meet the application requirements of some high-speed data processing and high-precision data storage. This technical solution realizes high-speed data transmission and high-precision data storage by adopting an optical fiber interface, a network twisted pair interface, or a high-speed differential signal on a printed circuit board as the high-speed communication interface, adopting single-group DDR or multi-group DDR as the DDR cache, and constructing a disk array with disks with SATA interfaces or disks with NVME interfaces. Thus, the data transmission speed and data storage capacity are increased.

[0022] 3) Improve the accuracy and stability of data playback: Existing high-speed data acquisition, storage, and playback devices have problems in the accuracy and stability of data playback and cannot guarantee the integrity and accuracy of the data. This technical solution realizes the high-precision conversion of digital signals to analog signals by setting an FPGA and a high-speed DA converter in the high-speed DA module. Thus, the accuracy and stability of data playback are improved, and the integrity and accuracy of the data are guaranteed.

[0023] More embodiments of the present utility model can also achieve other beneficial technical effects that are not listed one by one. Some of these other technical effects may be partially described below and can be expected and understood by those skilled in the art after reading the present utility model. Description of the Drawings

[0024] By referring to the following description in conjunction with the drawings, these features and advantages of these embodiments and other features and advantages and the manner of realizing them will become more apparent, and the embodiments of the present utility model can be better understood.

[0025] Figure 1It is a schematic block diagram of the main configuration and signal transmission / processing logic of a high-speed data acquisition, storage, and playback device according to the first embodiment of the present utility model.

[0026] Figure 2 It can be used for Figure 1 A schematic block diagram of the main configuration of the high-speed AD module of the high-speed data acquisition, storage, and playback device shown.

[0027] Figure 3 It can be used for Figure 1 A schematic block diagram of the main configuration of the storage module of the high-speed data acquisition, storage, and playback device shown.

[0028] Figure 4 It can be used for Figure 1 A schematic block diagram of the main configuration of the high-speed DA module of the high-speed data acquisition, storage, and playback device shown.

[0029] Figure 5 It is Figure 1 A schematic flowchart of data acquisition and storage of the high-speed data acquisition, storage, and playback device shown.

[0030] Figure 6 It is Figure 1 A schematic flowchart of reading and playback of the high-speed data acquisition, storage, and playback device shown. Detailed implementation manners

[0031] In the following descriptions of the drawings and the detailed implementation manners, details of one or more embodiments of the present utility model will be set forth. From these descriptions, the drawings, and the claims, other features, objects, and advantages of the present utility model will be apparent.

[0032] It should be understood that the illustrated and described embodiments are not limited in application to the details of the construction and arrangement of the components set forth in the following description or illustrated in the drawings. The illustrated embodiments may be other embodiments and can be implemented or carried out in various ways. The examples are provided by way of explanation rather than limitation of the disclosed embodiments. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present utility model without departing from the scope or essence of the disclosure of the present utility model. For example, features illustrated or described as part of one embodiment can be used with another embodiment to still produce additional embodiments. Therefore, the disclosure of the present utility model covers such modifications and variations that fall within the scope of the appended claims and their equivalent elements.

[0033] Similarly, it can be understood that the phrases and terms used in this article are for descriptive purposes and should not be considered restrictive. The use of "including", "comprising", or "having" and their variants in this article is intended to open - endedly include the items listed thereafter, their equivalents, and additional items.

[0034] In this utility model, unless otherwise clearly specified and defined, terms such as "installation", "connection", "linkage", etc. should be understood in a broad sense. For example, they can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above - mentioned terms in this utility model can be understood according to specific circumstances.

[0035] The following further describes and explains this utility model in detail with reference to the accompanying drawings and specific embodiments.

[0036] Figure 1 is a schematic block diagram of the main configuration and signal transmission / processing logic of a high - speed data acquisition, storage, and playback device according to the first embodiment of the present utility model. As Figure 1 shown, a high - speed data acquisition, storage, and playback device according to an embodiment of the present utility model is presented. It may include a high - speed AD module, a storage module, a high - speed DA module, a computer, and control software. A communication connection may be provided between the high - speed AD module and the storage module, and the connection method can be optical fiber, network cable, etc., or it can also be high - speed differential signals on a printed circuit board. A connection may be provided between the storage module and the computer, and the connection method can be a network interface, optical fiber, serial port, etc. A connection may be provided between the storage module and the high - speed DA module, and the connection method can be optical fiber, network cable, etc., or it can also be high - speed differential signals on a printed circuit board.

[0037] Figure 2 is applicable to Figure 1 shown is a schematic block diagram of the main configuration of the high - speed AD module of the high - speed data acquisition, storage, and playback device. As Figure 2 shown, the high - speed AD module may include a high - speed AD converter, an FPGA, and a high - speed communication interface. The high - speed AD module is configured to control the working state of the high - speed AD converter, convert the data of the high - speed AD converter, and send the data to the storage module through the high - speed communication interface. For example, the high - speed AD converter can adopt a parallel LVCMOS or LVDS interface, or it can also adopt a JESD204B serial interface as the high - speed communication interface.

[0038] Figure 3 is applicable to Figure 1 shown is a schematic block diagram of the main configuration of the storage module of the high - speed data acquisition, storage, and playback device. As Figure 3As shown in the figure, an FPGA, a DDR cache, a disk array, a high-speed communication interface A, a high-speed communication interface B, and a network interface can be provided inside the storage module. The FPGA inside the storage module can be connected to the DDR cache, the FPGA can be connected to the disk array, the FPGA can be connected to the high-speed communication interface A, the FPGA can be connected to the high-speed communication interface B, and the FPGA can be connected to the network interface. The FPGA can be directly used to control the data transmission of each interface. The DDR cache can be used for buffering and storing high-speed data. The disk array can be used for storing data. The network interface can be used to provide a network connection to the computer for transmitting control instructions or data.

[0039] In the present utility model, the technical route for the FPGA to be mounted on the DDR memory (Double Data Rate SDRAM, that is, Double Rate SDRAM) is mainly to directly access the content in the DDR memory by the FPGA (that is, bypassing the computer CPU) to achieve more efficient and high-speed access. In a preferred technical solution of the present utility model, mainly by mounting the high-speed AD module, the high-speed DA module, the DDR memory, and the NVME hard disk all on the FPGA and streamlining and optimizing the transmission protocol, more high-speed, low-latency, and more stable rate access can be achieved. In contrast, the existing technical solutions are mainly designed for general occasions, and their interface designs often aim at facilitating computer reading and writing access (which is exactly opposite to the above concept of the present utility model - bypassing the computer CPU), providing protocols such as FTP and HTTP with better compatibility with the computer. Essentially, compared with more general high-speed storage devices, the high-speed storage device of the present utility model is especially suitable for specific usage scenarios, such as data centers, especially Internet data centers (IDC), so it can achieve lower latency and can ensure a more stable high-speed transmission rate to provide more efficient, high-speed, and more stable access.

[0040] According to an example, the DDR cache can adopt a single group of DDR or multiple groups of DDR.

[0041] According to an example, the disk array can be constructed by disks with SATA interfaces or by disks with NVME interfaces.

[0042] Figure 4 can be used for Figure 1 The schematic block diagram of the main configuration of the high-speed DA module of the high-speed data acquisition, storage, and playback device shown in the figure. As Figure 4As shown in the figure. The high-speed DA module may be provided with a high-speed communication interface, an FPGA, and a high-speed DA converter. The high-speed DA module can be used to receive the data read out from the storage module, and can convert the digital signal into an analog signal through the high-speed DA converter. The FPGA can be used to control the working states of the high-speed communication interface and the high-speed DA converter. The high-speed communication interface can be used to connect to the storage module to achieve high-speed data transmission. For example, the high-speed DA converter can adopt a parallel LVCMOS or LVDS interface, or can also adopt a JESD204B serial interface.

[0043] The control software can be installed on the computer. The control software can be used to generate control instructions, and the control instructions can be transmitted through the network interface of the computer. The network interface of the computer can be directly connected to the network interface of the storage module.

[0044] Figure 5 is Figure 1 The schematic flowchart of data acquisition and storage of the high-speed data acquisition, storage and playback device shown in the figure. As Figure 5 shown, for example, the control software sends a data acquisition and storage instruction, the storage module receives the instruction, the storage module sends a data acquisition instruction to the high-speed AD module, the high-speed AD module works, and the storage module stores the data. In this way, the data storage is completed.

[0045] Figure 6 is Figure 1 The schematic flowchart of reading and playback of the high-speed data acquisition, storage and playback device shown in the figure. As Figure 6 shown, for example, the control software sends a data reading and playback instruction, the storage module receives the instruction, the storage module sends an instruction to the high-speed DA module, the storage module stores the data, and the high-speed DA module works. In this way, the data reading is completed.

[0046] According to an exemplary but non-limiting embodiment of the present invention, the high-speed data acquisition, storage and playback device provided by this embodiment is specifically implemented as follows.

[0047] Step 1: Set an FPGA and a high-speed communication interface in the high-speed AD module. The FPGA adopts the XC7K325T model of Xilinx Corporation, and the high-speed communication interface adopts an optical fiber interface with a transmission rate up to 10 Gbps.

[0048] Step 2: Set up an FPGA, a DDR cache, a disk array, a high-speed communication interface A, a high-speed communication interface B, and a network interface in the storage module. The FPGA uses the XC7K325T model from Xilinx. An example of the DDR cache can be the K4A8G084PCBB-HC16 model from Samsung, with a capacity of 8 GB. The disk array is connected to 4 hard drives of the WD10EZEX model from Western Digital through SATA interfaces, and each hard drive has a capacity of 1 TB. Both the high-speed communication interface A and the high-speed communication interface B use fiber optic interfaces with a transmission rate of up to 10 Gbps, and the network interface uses a gigabit Ethernet interface.

[0049] Step 3: Set up an FPGA and a high-speed DA converter in the high-speed DA module. The FPGA can use the XC7K325T model from Xilinx, and the high-speed DA converter can use the AD9768 model from ADI, with a sampling rate of up to 200 MSPS.

[0050] Step 4: Install control software on the computer. The control software is written in the LabVIEW programming language and is used to generate control instructions. The control instructions are transmitted through the network interface of the computer, and the network interface of the computer is directly connected to the network interface of the storage module.

[0051] Step 5: The control software sends data acquisition and storage instructions. The storage module receives the instructions, the storage module sends data acquisition instructions to the high-speed AD module, the high-speed AD module works, and the storage module stores the data.

[0052] Step 6: The storage module transmits the stored data to the high-speed DA module through the high-speed communication interface A. The high-speed DA module receives the data and converts the digital signal into an analog signal through the high-speed DA converter, and finally transmits it to the computer through the high-speed communication interface B for data playback.

[0053] The above is the specific description and implementation steps of this embodiment. Through this embodiment, high-rate smoothness, low latency, high-speed data acquisition, storage, and playback can be achieved, the system complexity is reduced, the portability and flexibility of the device are improved, the data transmission speed and data storage capacity are also increased, the accuracy and stability of data playback are ensured, and the integrity and accuracy of the data are guaranteed.

[0054] The technical effects that the present utility model can achieve include but are not limited to the following.

[0055] In the prior art, the industry mainstream latency level of NVME memory is that the read latency can be as low as 1 - 10 microseconds, and the write latency can also be as low as 1 - 10 microseconds. However, these values do not represent the total latency from the issuance of an instruction to the reception of data in practice. In fact, this latency level is also affected by factors such as the time for the operating system to process instructions and the length of the data transceiver path, and the actual latency will be around several hundred milliseconds or even longer.

[0056] In contrast, the present utility model optimizes the cache path by: (1) adding a DDR cache; (3) minimizing the impact of the CPU on latency through a software - hardware collaborative DMA (e.g., through FPGA, direct memory access) solution. For example, the FPGA directly controls the data interaction between the memory and each interface (including direct data transmission), and directly accesses the content in the DDR memory by bypassing the computer CPU to achieve more efficient and high - speed access. For example, in a preferred embodiment of the present utility model, by mounting the high - speed AD module, high - speed DA module, DDR memory, and NVME hard disk all on the FPGA, the access to them can be directly controlled by the FPGA to achieve faster, lower - latency, and more stable access rates; (3) optimizing the transmission latency by streamlining the network protocol. By combining the above technical means with relevant configurations, the present utility model can reduce the total latency to 200 - 300 microseconds (i.e., 0.2 - 0.3 milliseconds) or even shorter, which represents a huge improvement compared to the latency level of the prior art, showing a reduction in latency by an order of magnitude.

[0057] According to the present utility model, an FPGA can be used as the main controller to operate the analog - to - digital and digital - to - analog conversion processes and data storage and reading processes with lower latency, achieving high - speed and low - latency data acquisition and playback. In this case, according to the solution of the present utility model, the data reading process can be fully implemented by the FPGA. With the addition of the DDR cache, the smoothness of the high - speed rate in the high - speed reading scenario can be achieved, and the stored data can be conveniently transmitted to the high - speed DA module to achieve the conversion of digital signals to analog signals.

[0058] According to an embodiment of the high - speed data acquisition, storage, and playback device of the present utility model, the FPGA directly controls the data interaction between the disk and each interface, avoiding the storage and reading latency caused by using the CPU. Among the main technical indicators (i.e., the smoothness of speed) used in the industry to evaluate data acquisition, storage, and playback devices, the existing industry mainstream data transmission jitter is around 10 ms to 50 ms. In contrast, the average jitter of an embodiment of the high - speed data acquisition, storage, and playback device of the present utility model can reach a level of less than 1 ms.

[0059] Compared with the existing technologies, the data acquisition, storage, and playback device according to the present utility model no longer relies on a computer for control. Instead, the FPGA within the storage module controls the data transmission of each interface. This not only simplifies the complexity of the system but also improves the portability and flexibility of the device.

[0060] According to the technical solution of the present utility model, the data transmission speed and data storage capacity have been significantly improved. The connection between the high-speed AD module and the storage module can adopt high-speed connection methods such as optical fiber. At the same time, multiple groups of DDR caches and disk arrays are provided within the storage module. These measures greatly improve the data transmission speed and data storage capacity, meeting the application requirements of high-speed data processing and high-precision data storage.

[0061] According to the present utility model, the accuracy and stability of data playback have been significantly improved. The connection between the high-speed DA module and the storage module can adopt high-speed connection methods such as optical fiber. At the same time, multiple high-speed DA converters are provided within the high-speed DA module. These measures greatly improve the accuracy and stability of data playback, ensuring the integrity and accuracy of the data.

[0062] The data acquisition, storage, and playback device according to the present utility model can have higher scalability and adaptability. The connections between its various modules are all standard interfaces, which can be replaced and upgraded according to actual needs. This makes the present technical solution have higher scalability and adaptability.

[0063] The data acquisition, storage, and playback device according to the present utility model can have lower power consumption and higher reliability. The connections between its various modules adopt low-power connection methods such as high-speed differential signals. At the same time, low-power designs are also adopted within each module. These all greatly reduce the power consumption of the device and improve its reliability.

[0064] The basic concept of the present utility model has been described above in combination with the embodiments. However, the above embodiments are only non-limiting descriptions of the exemplary embodiments of the present utility model. Those skilled in the art will understand that the present utility model is not limited to the specific embodiments described herein. Various obvious changes, readjustments, re-combinations of technical features, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present utility model. The scope of the present utility model is determined by the scope of the appended claims.

Claims

1. A high-speed data acquisition, storage and playback device, characterized in that, The high-speed data acquisition, storage, and playback device includes: A high-speed AD module, which includes: a high-speed AD converter, a first FPGA, and a first high-speed communication interface; A storage module, which includes: a second FPGA; a DDR cache; a disk array for storing data; a second high-speed communication interface; a third high-speed communication interface; and a network interface. Among them, the second FPGA in the storage module is configured to be connected to the DDR cache, the second FPGA is connected to the disk array, the second FPGA is connected to the second high-speed communication interface, the third high-speed communication interface, and the network interface and is configured to directly control their data transmission, and the DDR cache is configured for buffered storage of high-speed data; A high-speed DA module, which includes: a fourth high-speed communication interface, a third FPGA, and a high-speed DA converter; and A computer, which is configured with a central processing unit; Among them, the high-speed AD module is communicatively connected to the storage module, the storage module is communicatively connected to the computer, and the storage module is communicatively connected to the high-speed DA module; Among them, the first FPGA is configured to directly control, in a manner bypassing the central processing unit: the data interaction between the first high-speed communication interface and the storage module; and the analog-to-digital signal conversion of the high-speed AD converter; Among them, the second FPGA is configured to directly control, in a manner bypassing the central processing unit: the access to the DDR cache; the data interaction between the disk array and the second high-speed communication interface, the third high-speed communication interface, and the network interface; and Among them, the third FPGA is configured to directly control, in a manner bypassing the central processing unit: the data interaction between the fourth high-speed communication interface and the storage module; and the digital-to-analog signal conversion of the high-speed DA converter.

2. The high-speed data acquisition, storage and playback device according to claim 1, characterized in that Control software is installed on the computer. The control software is used to generate control instructions for transmission through the network interface of the computer, and the network interface of the computer is directly connected to the network interface of the storage module.

3. The high-speed data acquisition, storage and playback device according to claim 2, wherein The control software is configured to send a data acquisition and storage instruction to the storage module, and the storage module is configured to send the data acquisition instruction to the high-speed AD module accordingly. Thereby, the high-speed AD module starts the data acquisition work and performs analog-to-digital signal conversion, and the storage module starts to store the corresponding data.

4. The high-speed data acquisition, storage and playback device according to claim 2, wherein, The control software is configured to send a data read and playback instruction to the storage module, and the storage module is configured to send the data read and playback instruction to the high-speed DA module accordingly. Thereby, the storage module starts to store the corresponding data, and the high-speed DA module starts to perform digital-to-analog signal conversion for data read and playback.

5. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that The DDR cache is a single-group DDR or multiple groups of DDR.

6. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that, The disk array can be constructed by disks with SATA interfaces or disks with NVME interfaces.

7. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that, The first high-speed communication interface, the second high-speed communication interface, the third high-speed communication interface, and the fourth high-speed communication interface are selected from any one of the following: fiber optic interface, network twisted pair interface, and high-speed differential signal on a printed circuit board; and The high-speed AD converter uses a parallel LVCMOS interface, a parallel LVDS interface, or a JESD204B serial interface; and the high-speed DA converter uses a parallel LVCMOS interface, a parallel LVDS interface, or a JESD204B serial interface.

8. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that, The average jitter of the high-speed data acquisition, storage, and playback device is less than 1 millisecond.

9. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that The total delay of the high-speed data acquisition, storage, and playback device during operation is in the range of 0.2 - 0.3 milliseconds.

10. The high-speed data acquisition, storage and playback device according to claim 1 or 2, characterized in that, The high-speed data acquisition, storage, and playback device is a high-speed data acquisition, storage, and playback device suitable for a data center.

Images