Power amplifier time sequence control circuit

Abstract

The utility model discloses a power amplifier time sequence control circuit, and belongs to the technical field of power amplifiers. The time sequence control circuit comprises a first voltage converter, a second voltage converter, a time delay circuit, a protection circuit and a control circuit. During power-on, the first voltage converter generates a first voltage, the second voltage converter generates a second voltage, and the second voltage can be directly applied to the gate end of the power amplifier. The time-delay circuit generates a control signal to the control circuit based on the second voltage in a time-delay manner, and the control circuit further controls the protection circuit, so that the first voltage can be applied to the drain end of the power amplifier through the protection circuit. During power-off, the second voltage converter works normally based on the first voltage in the power-off process of the first voltage, so that the second voltage can be continuously output. When the first voltage drops to a certain voltage, the second voltage converter does not work any more, so that the second voltage is not applied to the gate end of the power amplifier any more. The power-on and power-off time sequence of the power amplifier can be controlled, so that the power amplifier can meet the use requirements.

Description

Technical Field

[0001] The utility model relates to the technical field of power amplifiers, and particularly to a power amplifier timing control circuit. Background Art

[0002] With the migration of communication frequency bands to higher frequencies, base stations and communication devices require radio frequency devices that support high-frequency performance. With the progress of semiconductor material technology, gallium nitride (GaN) power amplifiers are becoming the first choice for power amplifiers in the medium and high frequency bands due to their advantages such as improved energy efficiency, wider bandwidth, higher power density, and smaller volume. However, gallium nitride (GaN) power amplifiers have strict timing during operation. As shown in Figures 1 to 2 The specific power-on and power-off timing requirements are as follows: during power-on, the gate terminal of the power amplifier is powered on prior to the drain terminal, that is, during power-on, the gate terminal of the power amplifier is powered on first, and the drain terminal is powered on after stabilization; during power-off, the drain terminal of the power amplifier is powered off prior to the gate terminal, that is, during power-off, the drain terminal of the power amplifier is powered off first, and the gate terminal is powered off when the voltage reaches within the safe voltage range.

[0003] However, for the existing power-on and power-off timing control circuits for gallium nitride (GaN) power amplifiers, although they can control the power-on and power-off timing to meet the requirements, they cannot provide corresponding protection when abnormal conditions occur in the timing control circuit.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present utility model and should not be regarded as an admission or any form of implication that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Utility Model

[0005] The purpose of the present utility model is to provide a power amplifier timing control circuit that can provide corresponding protection when abnormal conditions occur in the timing control circuit.

[0006] To achieve the above purpose, an embodiment of the present utility model provides a power amplifier timing control circuit, including

[0007] A first voltage converter for generating a first voltage;

[0008] A second voltage converter connected to the first voltage converter and the gate terminal of the power amplifier for generating a second voltage based on the first voltage;

[0009] A delay circuit connected to the second voltage converter for generating a control signal based on the second voltage with or without delay;

[0010] A protection circuit is connected to the drain terminal of the first voltage converter and the power amplifier, and can be switched between a first state and a second state. When in the first state, the first voltage converter forms a path with the drain terminal of the power amplifier through the protection circuit; when in the second state, the first voltage converter forms an open circuit with the drain terminal of the power amplifier through the protection circuit.

[0011] A control circuit is connected to the delay circuit and the protection circuit, and is used to control the protection circuit to switch between the first state and the second state based on the control signal.

[0012] In one or more embodiments of the present invention, the delay circuit includes

[0013] A conversion circuit is connected to the second voltage converter and is used to generate a first signal based on the second voltage;

[0014] An AND gate circuit is connected to the conversion circuit and can generate a third signal based on at least the first signal and a second signal;

[0015] A watchdog circuit is connected to the AND gate circuit and is used to generate a control signal with or without delay based on the third signal.

[0016] In one or more embodiments of the present invention, the second signal is generated by a control module.

[0017] In one or more embodiments of the present invention, the conversion circuit includes a first triode, a second triode, a pull-down resistor, a current-limiting resistor, a first voltage-dividing circuit, and a second voltage-dividing circuit. Among them,

[0018] The first electrode terminal of the first triode is connected to the second voltage converter through the first voltage-dividing circuit, the second electrode terminal is connected to the base terminal of the second triode through the current-limiting resistor and to the operating voltage through the pull-down resistor, and the base terminal is grounded;

[0019] The first electrode terminal of the second triode is connected to the operating voltage, and the second electrode terminal is connected to the AND gate circuit through the second voltage-dividing circuit.

[0020] In one or more embodiments of the present invention, the AND gate circuit includes at least one AND gate chip or a combination of multiple AND gate chips.

[0021] In one or more embodiments of the present invention, the second signal is input to the AND gate circuit through a filtering circuit.

[0022] In one or more embodiments of the present invention, the filtering circuit includes at least one filtering unit, and each filtering unit includes a resistor and a capacitor.

[0023] In one or more embodiments of the present utility model, the protection circuit includes

[0024] A first switching transistor, connected between the drain terminal of the first voltage converter and the power amplifier;

[0025] A protection chip, including an undervoltage lockout pin connected to the control circuit, which can switch between a first state and a second state based on the voltage input by the control circuit at the undervoltage lockout pin.

[0026] In one or more embodiments of the present utility model, the control circuit includes

[0027] A third voltage dividing circuit, connected in series between the first voltage and the ground, and connected to the undervoltage lockout pin;

[0028] A second switching transistor, connected to the third voltage dividing circuit, for controlling the voltage applied to the undervoltage lockout pin by the first voltage through the third voltage dividing circuit by conduction or cutoff.

[0029] A switching control circuit, connected to the delay circuit and the second switching transistor, for controlling the conduction or cutoff of the second switching transistor based on a control signal.

[0030] In one or more embodiments of the present utility model, the switching control circuit includes

[0031] A fourth voltage dividing circuit, connected in series between the first voltage and the ground, and connected to the gate terminal of the second switching transistor;

[0032] A third switching transistor, with its first electrode terminal connected to the fourth voltage dividing circuit, its second electrode terminal grounded, and its gate terminal connected to the delay circuit, for controlling the voltage applied to the gate terminal of the second switching transistor by the first voltage through the fourth voltage dividing circuit by conduction or cutoff.

[0033] In one or more embodiments of the present utility model, it further includes

[0034] A sampling circuit, connected to the first voltage converter and the protection chip, for sampling the first voltage, or obtaining a current based on the first voltage and inputting it into the protection chip.

[0035] In one or more embodiments of the present utility model, the sampling circuit includes

[0036] One sampling resistor; or

[0037] Multiple sampling resistors connected in parallel.

[0038] Compared with the prior art, (1) the power amplifier timing control circuit according to the embodiment of the present utility model can make corresponding protection against abnormalities occurring during the operation of the power amplifier timing control circuit by setting a protection circuit, so as to avoid damage to the power amplifier and improve safety.

[0039] (2) The power amplifier timing control circuit according to the embodiment of the present utility model, on the one hand, by setting a delay circuit, can ensure delayed signal output when the power amplifier is powered on, thereby ensuring that the power-on timing of the power amplifier meets the requirements. On the other hand, by adopting a second voltage converter, it can ensure that the power-off timing of the power amplifier meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is the power-on timing diagram of a gallium nitride power amplifier according to an embodiment of the present utility model;

[0041] Figure 2 is the power-off timing diagram of a gallium nitride power amplifier according to an embodiment of the present utility model;

[0042] Figure 3 is the schematic structural diagram of a power amplifier timing control circuit according to an embodiment of the present utility model;

[0043] Figure 4 is the schematic structural diagram of a power amplifier timing control circuit according to an embodiment of the present utility model;

[0044] Figure 5 is the schematic circuit diagram of a power amplifier timing control circuit according to an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The following will describe in detail the specific embodiments of the present utility model with reference to the accompanying drawings, but it should be understood that the protection scope of the present utility model is not limited by the specific embodiments.

[0046] Unless otherwise clearly stated, throughout the specification and claims, the term "comprise" or its variations such as "comprises" or "including" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0047] Combined with Figures 3 to 5As shown in the figure, a power amplifier timing control circuit according to a preferred embodiment of the present invention can control the power-on and power-off timing of a power amplifier, so that its power-on and power-off timing meets the following requirements: when powering on, the gate terminal of the power amplifier is powered on prior to the drain terminal, that is, when powering on, the gate terminal of the power amplifier is powered on first, and after stabilization, the drain terminal is powered on. When powering off, the drain terminal of the power amplifier is powered off prior to the gate terminal, that is, when powering off, the drain terminal of the power amplifier is powered off first, and when the voltage reaches within the safe voltage range, the gate terminal is powered off. The power amplifier here refers to a power amplifier, and the power amplifier includes but is not limited to a gallium nitride (GaN) power amplifier. As long as the power-on and power-off timing of the power amplifier meets the above requirements, the power amplifier timing control circuit described in the present invention can be applied.

[0048] Specifically, as shown in Figures 3 to 4 the figure, the power amplifier timing control circuit is used to control the power-on and power-off timing of the power amplifier M. The power amplifier includes a gate terminal Vg and a drain terminal Vd. When the power amplifier is operating normally, the voltage required by the drain terminal Vd of the power amplifier is denoted as the first voltage, and the voltage required by the gate terminal Vg is denoted as the second voltage. Here, controlling the power-on and power-off timing of the power amplifier means that when powering on, the second voltage is controlled to be powered on prior to the first voltage, and when powering off, the second voltage is controlled to be powered off prior to the first voltage.

[0049] As shown in Figure 3 the figure, the power amplifier timing control circuit includes a first voltage converter 100, a second voltage converter 200, a delay circuit 300, a protection circuit 400, and a control circuit 500. Among them,

[0050] the first voltage converter 100 is used to generate the first voltage. For example, in implementation, the first voltage converter 100 converts the externally input voltage into the voltage required by the drain terminal of the power amplifier. For example, the first voltage converter 100 generates a 50V voltage required by the drain terminal of the GaN power amplifier. In this embodiment, since the power amplifier preferably uses a GaN power amplifier, the first voltage converter 100 is preferably a general-purpose 50V voltage converter. Of course, in other embodiments, the first voltage converter can also be selected according to the type of the power amplifier.

[0051] The second voltage converter 200 is connected to the first voltage converter 100 and the gate terminal Vg of the power amplifier, and is used to generate a second voltage based on the first voltage. For example, when implemented, the second voltage converter 200 converts the first voltage into the voltage required for the gate terminal Vg of the power amplifier M. For example, the first voltage is converted into a -6.5V voltage required for the gate terminal of the gallium nitride power amplifier by the second voltage converter 200. In this embodiment, the second voltage converter 200 generates the second voltage based on the first voltage generated by the first voltage converter 100. That is, after the first voltage converter 100 generates the first voltage, it inputs it to the second voltage converter 200, and the second voltage converter 200 further converts the first voltage into the second voltage. Of course, in other embodiments, the second voltage converter 200 can also generate the second voltage based on an externally input voltage. Since the power amplifier is preferably a GaN power amplifier, for this GaN power amplifier, the second voltage converter 200 is preferably a general-purpose -6.5V voltage converter. For example, a voltage converter with the model number SGM61630 is selected. Of course, the corresponding model of the second voltage converter 200 can also be selected according to the type of the power amplifier.

[0052] The delay circuit 300 is connected to the second voltage converter 200 and can at least generate a control signal based on the second voltage with a preset delay. Of course, it can also directly generate a control signal. When specifically implemented, the second voltage generated by the second voltage converter 200 is input to the delay circuit 300. The delay circuit 300 can directly generate a control signal based on this second voltage, or generate a control signal with a preset delay. For example, a control signal is generated after a 200ms delay, or a control signal is generated without a 200ms delay. That is to say, whether the delay circuit 300 generates a control signal with a preset delay depends on the second voltage generated by the second voltage converter 200. For example, when the second voltage converter 200 normally generates the second voltage, the delay circuit 300 outputs a control signal with a preset delay, and when the second voltage converter 200 does not normally generate the second voltage, the delay circuit 300 does not output a control signal without delay.

[0053] The protection circuit 400 is connected between the first voltage converter 100 and the drain terminal of the power amplifier, playing a protective role. It has a first state and a second state, and can be switched between the first state and the second state. Among them, when the protection circuit 400 is in the first state, the first voltage generated by the first voltage converter 100 can be input to the drain terminal Vd of the power amplifier M. That is, at this time, the protection circuit 400 forms a path for the circuit between the first voltage converter 100 and the drain terminal Vd of the power amplifier M, so that the first voltage can be input to the drain terminal Vd of the power amplifier M. When the protection circuit 400 is in the second state, the first voltage generated by the first voltage converter 100 cannot be input to the drain terminal Vd of the power amplifier M. That is, at this time, the protection circuit 400 forms an open circuit for the circuit between the first voltage converter 100 and the drain terminal Vd of the power amplifier M.

[0054] While the control circuit 500 is connected to the protection circuit 400, it is also connected to the delay circuit 300. It can control whether the protection circuit 400 is in the first state or the second state based on the control signal generated by the delay circuit 300, that is, it can control the protection circuit 400 to switch between the first state and the second state based on the control signal. If the control signal is generated after the delay circuit 300 delays for a preset time, the control circuit 500 can control the protection circuit 400 to be in the first state based on this control signal. At this time, a first voltage can be applied to the drain terminal Vd of the power amplifier M. When the control signal is directly generated by the delay circuit 300, the control circuit 500 can control the protection circuit 400 to be in the second state based on this control signal. At this time, the first voltage cannot be applied to the drain terminal Vd of the power amplifier M.

[0055] Combined with Figures 1 to 4 As shown, when the power amplifier timing control circuit is working, for the power-on of the power amplifier M, the first voltage converter 100 generates a first voltage, and the second voltage converter 200 generates a second voltage. The second voltage can be directly applied to the gate terminal Vg of the power amplifier M. At this time, the delay circuit 300 generates a control signal to the control circuit 500 after delaying for a preset time based on the second voltage. The control circuit 500 controls the switch protection circuit 400 to be in the first state based on this control signal, that is, the first voltage can be applied to the drain terminal Vd of the power amplifier M through the protection circuit 400. Since the delay circuit 300 delays for a preset time before outputting the control signal, the control circuit 500 does not apply the first voltage to the drain terminal Vd of the power amplifier M through the control protection circuit 400 until after the preset time. Thus, the requirement that the gate terminal Vg of the power amplifier M is powered on prior to the drain terminal Vd during power-on is achieved.

[0056] For the power-off of the power amplifier M, when the drain terminal Vd of the power amplifier M is powered off, combined with the power-off timing of the first voltage, it can be known that during the power-off process of the first voltage, the second voltage converter 200 can still work normally based on the first voltage, so that the second voltage can continue to output the second voltage. When the second voltage drops to a certain voltage, the second voltage converter 200 cannot work normally, and the second voltage converter 200 cannot output the second voltage. Since the second voltage converter 200 cannot output the second voltage, the delay circuit 300 does not delay for a preset time to generate a control signal based on this second voltage. The control circuit 500 controls the protection circuit 400 to be in the second state based on this control signal, and the first voltage cannot be applied to the drain terminal Vd of the power amplifier M. Thus, the requirement that the drain terminal Vd of the power amplifier M is powered off prior to the gate terminal Vg and the gate terminal Vg is powered off when the voltage reaches within the safe voltage during power-off is achieved.

[0057] Such as Figure 4As shown, the delay circuit 300 includes a conversion circuit 301, an AND gate circuit 302, and a watchdog circuit 303. Among them, the conversion circuit 301 is connected to the second voltage converter 200 and can generate a first signal based on the second voltage output by the second voltage converter 200. Here, the first signal can be a high-level signal or a low-level signal. The AND gate circuit 302 includes a first input terminal INA, a second input terminal INB, and an output terminal OUT. Among them, the first input terminal INA is connected to the output terminal of the conversion circuit 301 for inputting the first signal, and the second input terminal INB is used for inputting the second signal. This second signal can be input by an external module. For example, the second input terminal INB is connected to the MCU (Micro Control Unit) module, and the MCU module generates the second signal and inputs it into the AND gate circuit 302. The AND gate circuit 302 outputs a third signal based on the input first signal and second signal. The watchdog circuit 303 is connected to the output terminal of the AND gate circuit 302 and can generate a control signal with or without delay based on the third signal.

[0058] As Figure 5 As shown, the conversion circuit 301 includes a first triode 301a, a second triode 301b, a first voltage dividing circuit 301c, a second voltage dividing circuit 301d, a current limiting resistor 301e, and a pull-down resistor 301f. Among them, the first voltage dividing circuit 301c is connected between the second voltage and the ground and can generate a voltage division based on the second voltage generated by the second voltage converter 200 to input into the first triode 301a, thereby controlling whether the first triode 301a conducts. Both the first triode 301a and the second triode 301b have a first electrode terminal, a second electrode terminal, and a base terminal. The base terminal of the first triode 301a is grounded, the first electrode terminal is connected to the output terminal of the first voltage dividing circuit 301c, and the second electrode terminal is connected to the base terminal of the second triode 301b through the current limiting resistor 301e. At the same time, the second electrode terminal is also connected to the first electrode terminal of the second triode 301b through the pull-down resistor 301f. The first electrode terminal of the second triode 301b is connected to the working voltage, such as 5V voltage, and the second electrode terminal is grounded through the second voltage dividing circuit 301d. The output terminal of the second voltage dividing circuit 301d is connected to the first input terminal INA of the AND gate circuit 302, and it can generate a voltage division based on the working voltage source to input into the AND gate circuit 302.

[0059] During specific operation, when the second voltage converter 200 normally generates the first voltage, such as normally generating -6.5V voltage, the first voltage is divided by the first voltage dividing circuit 301c to obtain a voltage (such as -4.9V) and applied to the first triode 301a. At this time, the first triode 301a conducts, and the voltage is further applied to the base terminal of the second triode 301b through the current limiting resistor 301e. At this time, the second triode 301b conducts, and the working voltage can generate a voltage division through the second voltage dividing circuit 301d and input it into the first input terminal of the AND gate circuit 302.

[0060] In this embodiment, the first triode 301a is preferably an NPN-type triode, such as a triode of model MMBT4401LT1G, and the second triode 301b is preferably a PNP-type triode, such as a triode of model MMBT2907AWT1G. Both the first voltage dividing circuit 301c and the second voltage dividing circuit 301d include two serially connected voltage dividing resistors, namely the voltage dividing resistors R0 and R1 respectively. The connection point of the two voltage dividing resistors R0 and R1 can be led outwards as an output terminal to be connected to corresponding components. For example, in the first voltage dividing circuit 301c, the connection point A of the two voltage dividing resistors R0 and R1 is connected to the first electrode terminal of the first triode 301a. Here, the resistance values of the voltage dividing resistors R0 and R1 can be set according to actual requirements. Of course, the number of voltage dividing resistors in the voltage dividing circuit can also be set according to actual requirements, such as setting 3 serially connected voltage dividing resistors, etc.

[0061] such as Figure 5 As shown, the AND gate circuit 302 includes an AND gate chip 302a, or a combination of multiple AND gate chips 302a. It includes a first input terminal INA, a second input terminal INB, and an output terminal OUT. Among them, the first input terminal INA is connected to the output terminal of the second voltage dividing circuit 301d to input the voltage divided by the second voltage dividing circuit 301d (i.e., the first signal). For example, the first input terminal INA is connected to the connection point B of the two voltage dividing resistors R0 and R1 in the second voltage dividing circuit 301d; the second input terminal INB is used to input a second signal. In this embodiment, the second input terminal INB is connected to the MCU module to input the second signal.

[0062] In this embodiment, the AND gate circuit 302 includes an AND gate device, preferably an AND gate device of model 74HC1G08. Its two input terminals respectively input the first signal and the second signal. When both of its input terminals input high-level signals, the output terminal outputs a high-level signal, and in other cases, it outputs a low-level signal. Of course, in this embodiment, multiple AND gate devices can also be combined according to actual requirements to meet the requirement that when all input terminals input high-level signals, the output terminal outputs a high-level signal, and in other cases, it outputs a low-level signal.

[0063] Furthermore, as Figure 5As shown, the second input terminal INB is connected to the filter circuit 304, so that the second signal is input into the AND gate chip 302a after being processed by the filter circuit, thereby improving the stability of the input circuit. The filter circuit includes at least one filter unit, and the filter unit includes a resistor Ra and a capacitor Ca. Wherein, one end of the resistor Ra is connected to the MCU module (not shown in the figure), and the opposite end is connected to the second input terminal INB; one end of the capacitor Ca is connected between the resistor Ra and the second input terminal INB, and the opposite end is grounded. In this embodiment, the filter circuit includes two series-connected filter units to form a second-order filter circuit to better improve the quality of the input signal.

[0064] As Figure 5 shown, the watchdog circuit 303 includes a watchdog chip 303a, which is connected to the AND gate chip 302a, as Figure 5 shown, the nMR pin (manual reset pin) of the watchdog chip 303a is connected to the output terminal of the AND gate chip 302a, so that the AND gate chip 302a outputs a corresponding third signal into the watchdog chip 303a, and the nRESET pin is used as an output pin to output a control signal. The watchdog chip 303a can determine whether to delay the generation of a control signal based on the third signal output by the AND gate chip 302a. In this embodiment, when the third signal output by the AND gate chip 302a is a high-level signal, that is, the nMR pin receives a high-level signal, the watchdog chip 303a can delay a preset time (such as 200 ms) to generate a control signal, and this control signal is a high-level signal; when the third signal output by the AND gate chip 302a is a low-level signal, that is, the nMR pin receives a low-level signal, the watchdog chip 303a does not delay the preset time to generate a control signal, and this control signal is a low-level signal. In this embodiment, the watchdog chip is preferably a chip of model SGM823-SXN5G.

[0065] As Figure 5 shown, the protection circuit 400 includes a first switching transistor 401 and a protection chip 402. Wherein, the first switching transistor 401 has a first electrode terminal, a second electrode terminal and a gate terminal. Its first electrode terminal is connected to the first voltage converter 100, the second electrode terminal is connected to the drain terminal Vd of the power amplifier, and the gate terminal is connected to the protection chip 402.

[0066] Further, as Figure 5As shown, the protection chip 402 has UVLO (Under-Voltage Lock-Out) pins, OVLO (Over-Voltage Lock-Out) pins, and Gate pins. Among them, the ULVO pin is connected to the control circuit 500 and can be used to receive the voltage input by the control circuit 500. The Gate pin is connected to the gate terminal of the first switching transistor 401 to control whether the first switching transistor 401 is turned on. When the voltage input to the UVLO pin is within the turn-on voltage range [UVLO, OVLO] of the protection chip 402, it is in the normal working state (i.e., the first state). When the voltage input to the UVLO pin is not within the turn-on voltage range of the protection chip 402, it cannot work properly and is in the abnormal working state (i.e., the second state). When the protection chip 402 is in the normal working state, the protection chip 402 can control the first switching transistor 401 to be in the on state, and finally the first voltage can be input to the drain terminal Vd of the power amplifier M. When the protection chip 402 is in the abnormal working state, the protection chip 402 can control the first switching transistor 401 to be in the off state, and finally the first voltage cannot be input to the drain terminal Vd of the power amplifier M. By controlling the first switching transistor 401 to be in the on or off state through the protection chip 402, unnecessary damage to the power amplifier caused by the power amplifier timing control circuit during abnormal operation can be avoided. That is to say, by setting the protection circuit 400, damage to the power amplifier caused by the power amplifier timing control circuit 500 during abnormal operation can be avoided. In this embodiment, the preferred model of the protection chip 402 is the chip SGM25701A.

[0067] Furthermore, as shown in combination with Figures 4 to 5 The protection circuit further includes a sampling circuit 403. The sampling circuit 403 is connected to the first voltage converter 100 and the protection chip 402, and can sample the first voltage output by the first voltage converter 100 and input it into the protection chip 402. The protection chip 402 can determine whether it works normally based on the sampling result. For example, when the voltage detected by the protection chip exceeds 55 mV, it indicates that the circuit is in an over-current state at this time. At this time, the fault timer is started. When a fault is detected, the device will enter the automatic retry mode to make the chip return to the normal working mode. In addition, the output current will stop in the over-voltage and under-voltage states of the circuit. None of the above faults can turn on the first switching transistor 401, and the first voltage cannot be applied to the power amplifier, thus playing the function of fault protection. Of course, in other embodiments, a corresponding sampling circuit can also be determined based on the first voltage for the protection chip 402 to determine whether it works normally.

[0068] Such as Figure 5As shown in the figure, the control circuit 500 includes a third voltage dividing circuit 501, a second switching transistor 502, and a switching control circuit 503. Among them, the third voltage dividing circuit 501 is connected between the first voltage and the ground, and its output terminal is connected to the ULVO pin of the protection chip 402. The second switching transistor 502 has a first electrode terminal, a second electrode terminal, and a gate terminal. The first electrode terminal of the second switching transistor 502 is connected to the third voltage dividing circuit 501, the second electrode terminal is grounded, and the gate terminal is connected to the switching control circuit 503. The switching control circuit 503 is connected to the output terminal of the delay circuit 300, and can control whether the second switching transistor 502 is turned on based on the control signal output by the delay circuit 300.

[0069] In a specific implementation, when the switching control circuit 503 controls the second switching transistor 502 to turn off based on the control signal output by the delay circuit 300, the first voltage generates a partial voltage through the third voltage dividing circuit 501, and this partial voltage is input to the ULVO pin. Since the partial voltage generated through the third voltage dividing circuit 501 is within the turn-on threshold range of the protection chip 402, the protection chip 402 is in a normal working state. When the switching control circuit 503 controls the second switching transistor 502 to turn on based on the control signal output by the delay circuit 300, the first voltage is grounded through the third voltage dividing circuit 501, so that the voltage input to the ULVO pin of the protection chip 402 is lower than the turn-on threshold of the protection chip 402, and the protection chip 402 is in an abnormal working state.

[0070] Furthermore, as Figure 5 shown, the third voltage dividing circuit 501 includes three voltage dividing resistors connected in series, denoted as voltage dividing resistors R0, R1, and R2 respectively. Among them, one end of the voltage dividing resistor R0 is connected to the first voltage, and the opposite end is connected to the voltage dividing resistor R1 to form a connection point C. The voltage dividing resistor R1 is further grounded through the voltage dividing resistor R2. This connection point C is further connected to the ULVO pin of the protection chip 402 to input a voltage to the protection chip 402. At the same time, this connection point C is also connected to the first electrode terminal of the second switching transistor 502, so that when the second switching transistor 502 is turned on, the first voltage is grounded through the voltage dividing resistor R0, so that the voltage input to the UVLO pin is pulled down.

[0071] In this embodiment, the control circuit 500 further includes a voltage dividing circuit connected to the OVLO pin of the protection chip 402 to input a corresponding voltage to the OVLO pin through the voltage dividing circuit to avoid overvoltage lock-up of the protection chip 402. As Figure 5 shown, the OVLO pin of the protection chip 402 is connected to the voltage dividing circuit composed of the voltage dividing resistors R0 to R2.

[0072] As Figure 5As shown, the switch control circuit 503 includes a fourth voltage dividing circuit and a third switching transistor 503a. The fourth voltage dividing circuit is connected between the first voltage and the ground, and its output terminal is connected to the gate terminal of the second switching transistor 502. The third switching transistor 503a has a first electrode terminal, a second electrode terminal, and a gate terminal. The first electrode terminal of the third switching transistor 503a is connected to the fourth voltage dividing circuit, the second electrode terminal is grounded, and the gate terminal is connected to the output terminal of the delay circuit 300, and whether the third switching transistor 503a is turned on can be controlled based on the control signal output by the delay circuit 300. In this embodiment, the fourth voltage dividing circuit includes two voltage dividing resistors connected in series between the first voltage and the ground, denoted as voltage dividing resistors R0 and R1 respectively. Among them, the connection point D formed by the series connection of the two voltage dividing resistors R0 and R1 is connected to the first electrode terminal of the third switching transistor 503a, and at the same time, is connected to the gate terminal of the second switching transistor 502.

[0073] In specific implementation, when the third switching transistor 503a is turned on based on the control signal, the first voltage is grounded through the voltage dividing resistor in the fourth voltage dividing circuit, so that the voltage at the gate terminal of the second switching transistor 502 is pulled down, and then the second switching transistor 502 is turned off. At this time, the first voltage generates a voltage division through the third voltage dividing circuit 501, and this voltage division is input to the ULVO pin. Since the voltage division generated by the third voltage dividing circuit 501 is within the turn-on threshold range of the protection chip 402, the protection chip 402 is in a normal working state. When the third switching transistor 503a is turned off based on the control signal, the first voltage generates a voltage through the voltage dividing resistor of the fourth voltage dividing circuit and applies it to the second switching transistor 502, so that the second switching transistor 502 is turned on, and the first voltage is grounded through the voltage dividing resistor in the third voltage dividing circuit 501, so that the voltage input to the ULVO pin of the protection chip 402 is lower than the turn-on threshold of the protection chip 402, and the protection chip 402 is in an abnormal working state.

[0074] In this embodiment, the first switching transistor 401 is preferably an N-type MOS transistor, such as a MOS transistor of model CJB3R0SN10B; the second switching transistor 502 and the third switching transistor 503a are also preferably N-type MOS transistors, such as MOS transistors of model CJB3R0SN10B.

[0075] The following takes the power amplifier timing control circuit diagram as shown in Figure 5 as an example to illustrate in detail how the power amplifier timing control circuit controls the power-on and power-off timing of the gallium nitride power amplifier.

[0076] When powering on the gallium nitride power amplifier, the first voltage converter 100 generates a first voltage, such as 50V. When the second voltage converter 200 outputs a second voltage based on the first voltage, such as a -6.5V voltage, the second voltage is divided by two voltage-dividing resistors (voltage-dividing resistor R0 and voltage-dividing resistor R1) in the first voltage-dividing circuit 301c to obtain a negative voltage larger than -6.5V (such as around -4.9V), enabling the collector and emitter of the first triode 301a to conduct. The negative voltage then reaches the base terminal of the second triode through a current-limiting resistor, causing the second triode 301b to conduct. The operating voltage (5V) is divided by two voltage-dividing resistors (voltage-dividing resistor R0 and voltage-dividing resistor R1) in the second voltage-dividing circuit 301d and output to the first input terminal INA of the AND gate chip 302a. When the second voltage is not output normally, the first triode 301a is cut off, the collector of the first triode is in a floating state, the second triode 301b cannot conduct, and thus the operating voltage (5V) cannot be divided and supplied to the subsequent circuit;

[0077] In the AND gate circuit 302, the second signal output by the MCU module is input to the second input terminal INB of the AND gate chip 302a through the filter circuit 304. Since the output terminal OUT of the AND gate chip is directly connected to the manual reset pin nMR of the watchdog chip 303a, the AND gate chip 302a can output a third signal to the watchdog chip 303a. The watchdog chip 303a generates a control signal based on the third signal.

[0078] When the control signal is at a high level (i.e., the control signal is a delayed-generated signal), the third switch tube 503a conducts based on the control signal, and the first voltage is grounded through the voltage-dividing resistor in the fourth voltage-dividing circuit, causing the voltage at the gate terminal of the second switch tube 502 to be pulled down, and further causing the second switch tube 502 to turn off. At this time, the first voltage generates a partial voltage through the third voltage-dividing circuit 501, and this partial voltage is input to the ULVO pin. Since the partial voltage generated through the third voltage-dividing circuit 501 is within the turn-on threshold range of the protection chip 402, the protection chip 402 is in a normal operating state.

[0079] When the control signal is at a low level, the third switch tube 503a turns off based on the control signal, and the first voltage generates a partial voltage through the fourth voltage-dividing circuit and applies it to the second switch tube 502, causing the second switch tube 502 to conduct. The first voltage is grounded through the voltage-dividing resistor in the third voltage-dividing circuit 501, causing the voltage input to the ULVO pin of the protection chip 402 to be lower than the turn-on threshold of the protection chip 402, and the protection chip 402 is in an abnormal operating state;

[0080] When the protection chip 402 is in a normal working state, the protection chip 402 can control the first switching transistor 401 to be in a conducting state, and finally the first voltage can be input to the drain terminal Vd of the power amplifier M. Finally, the requirement that the power-on of 50V lags behind -6.5V to reach the power amplifier is achieved.

[0081] When powering down the gallium nitride power amplifier, when the 50V voltage generated by the first voltage converter 100 starts to power down, the input voltage of the second voltage converter 200 can make it work normally, and then the output -6.5V voltage can be maintained; when the 50V powers down to 0V, at this time the input voltage of the second voltage converter 200 is lower than the working voltage range of the second voltage converter 200, and the -6.5V voltage cannot be output; since the second voltage converter 200 cannot output the second voltage, the delay circuit 300 generates a control signal based on the non-delay preset time of the second voltage, and the control circuit 500 controls the protection circuit 400 to be in the second state based on this control signal, and the first voltage cannot be applied to the drain terminal Vd of the power amplifier M. Thus, when powering down, the drain terminal Vd of the power amplifier M powers down first, and when the safe voltage is reached, the gate terminal Vg powers down again.

[0082] The foregoing description of the specific exemplary embodiments of the present invention is for the purposes of illustration and exemplification. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is obvious that many changes and variations are possible in light of the above teaching. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical applications, so that those skilled in the art can implement and utilize the various different exemplary embodiments of the present invention, as well as various different selections and changes. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. An amplifier power supply timing control circuit, characterized in that, including a first voltage converter for generating a first voltage; a second voltage converter connected to the gate terminal of the power amplifier and the first voltage converter, for generating a second voltage based on the first voltage; a delay circuit connected to the second voltage converter, for generating a control signal based on the second voltage with or without delay; a protection circuit connected to the drain terminal of the first voltage converter and the power amplifier, and capable of switching between a first state and a second state. When in the first state, the first voltage converter forms a path with the drain terminal of the power amplifier through the protection circuit. When in the second state, the first voltage converter forms an open circuit with the drain terminal of the power amplifier through the protection circuit; a control circuit connected to the delay circuit and the protection circuit, for controlling the protection circuit to switch between the first state and the second state based on the control signal.

2. The power amplifier timing control circuit according to claim 1, wherein The delay circuit includes a conversion circuit connected to the second voltage converter, for generating a first signal based on the second voltage; an AND gate circuit connected to the conversion circuit, capable of generating a third signal based on at least the first signal and a second signal; a watchdog circuit connected to the AND gate circuit, for generating a control signal based on the third signal with or without delay.

3. The power amplifier timing control circuit according to claim 2, characterized in that, The second signal is generated by a control module.

4. The power amplifier timing control circuit according to claim 2, wherein, The conversion circuit includes a first triode, a second triode, a pull-down resistor, a current-limiting resistor, a first voltage-dividing circuit, and a second voltage-dividing circuit. Among them, the first electrode terminal of the first triode is connected to the second voltage converter through the first voltage-dividing circuit, the second electrode terminal is connected to the base terminal of the second triode through the current-limiting resistor and to the operating voltage through the pull-down resistor, and the base terminal is grounded; the first electrode terminal of the second triode is connected to the operating voltage, and the second electrode terminal is connected to the AND gate circuit through the second voltage-dividing circuit.

5. The power amplifier timing control circuit according to claim 2, wherein The AND gate circuit includes at least one AND gate chip, or a combination of multiple AND gate chips.

6. The power amplifier timing control circuit according to claim 2, wherein, The second signal is input to the AND gate circuit through a filtering circuit.

7. The power amplifier timing control circuit according to claim 6, characterized in that, The filtering circuit includes at least one filtering unit, and each filtering unit includes a resistor and a capacitor.

8. The power amplifier timing control circuit according to claim 1, wherein The protection circuit includes a first switching tube connected between the first voltage converter and the drain terminal of the power amplifier; a protection chip including an under-voltage lockout pin connected to the control circuit, capable of switching between the first state and the second state based on the voltage input by the control circuit at the under-voltage lockout pin.

9. The power amplifier timing control circuit according to claim 8, wherein The control circuit includes a third voltage-dividing circuit connected in series between the first voltage and the ground, and connected to the under-voltage lockout pin; a second switching tube connected to the third voltage-dividing circuit, for controlling the voltage applied to the under-voltage lockout pin by the first voltage through the third voltage-dividing circuit by conduction or cutoff; a switching control circuit connected to the delay circuit and the second switching tube, for controlling the second switching tube to conduct or cutoff based on the control signal.

10. The power amplifier timing control circuit according to claim 9, wherein The switching control circuit includes a fourth voltage-dividing circuit connected in series between the first voltage and the ground, and connected to the gate terminal of the second switching tube; A third switching transistor, with its first electrode terminal connected to the fourth voltage dividing circuit, its second electrode terminal grounded, and its gate terminal connected to a delay circuit, is configured to control, through conduction or cutoff, the voltage applied to the gate terminal of the second switching transistor by using the fourth voltage dividing circuit to utilize the first voltage.

11. The power amplifier timing control circuit according to claim 1, characterized in that, Further included is a sampling circuit, connected to the first voltage converter and the protection chip, for sampling the first voltage or obtaining a current based on the first voltage and inputting the same into the protection chip.

12. The power amplifier timing control circuit according to claim 11, characterized in that, The sampling circuit includes a sampling resistor; or a plurality of sampling resistors connected in parallel.

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